KR0173178B1 - Etching process for metal layer of semiconductor - Google Patents
Etching process for metal layer of semiconductor Download PDFInfo
- Publication number
- KR0173178B1 KR0173178B1 KR1019960050298A KR19960050298A KR0173178B1 KR 0173178 B1 KR0173178 B1 KR 0173178B1 KR 1019960050298 A KR1019960050298 A KR 1019960050298A KR 19960050298 A KR19960050298 A KR 19960050298A KR 0173178 B1 KR0173178 B1 KR 0173178B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- photoresist
- etching process
- metal
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 title abstract description 35
- 239000002184 metal Substances 0.000 title abstract description 35
- 239000010408 film Substances 0.000 claims abstract description 104
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 230000001681 protective effect Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000003870 refractory metal Substances 0.000 claims 1
- 229920000642 polymer Polymers 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010931 gold Substances 0.000 description 28
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 21
- 229910052737 gold Inorganic materials 0.000 description 21
- 239000010949 copper Substances 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
금속막 표면에 폴리머가 형성되는 것을 방지할 수 있는 금속막 식각공정이 개시되어 있다.A metal film etching process capable of preventing formation of a polymer on the surface of a metal film is disclosed.
본 발명은, 반도체기판의 층간절연막 상부에 증착된 도전체막을 선택적으로 제거하여 전극배선을 형성하는 박막 식각공정에 있어서, 도전체막 상부에 보호막을 형성하는 단계와, 상기 보호막 상부에 사진공정을 실시하여 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트를 마스크로 사용하여 상기 보호막을 선택적으로 제거하는 단계와, 상기 포토레지스트를 제거하고 상기 보호막을 마스크로 사용하여 상기 도전체막을 선택적으로 제거하여 전극배선을 형성하는 단계와, 상기 전극배선 상부의 보호막을 제거하는 단계로 구성됨을 특징으로 한다.The present invention relates to a thin film etching process for forming an electrode wiring by selectively removing a conductive film deposited on an interlayer insulating film of a semiconductor substrate, comprising the steps of: forming a protective film on the conductive film; Selectively removing the protective film using the photoresist as a mask; and removing the photoresist and selectively removing the conductive film using the protective film as a mask, A step of forming a wiring, and a step of removing a protective film on the electrode wiring.
따라서, 본 발명은 금속전극의 저항을 감소시킬 수 있을 뿐만 아니라 금속전극 간의 절연 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, the present invention has the effect of not only reducing the resistance of the metal electrode but also improving the insulation reliability between the metal electrodes.
Description
본 발명은 반도체 박막 식각공정에 관한 것으로서, 특히 금속막을 선택적으로 식각하여 전극 패턴을 형성하는 금속막 식각공정에 관한 것이다.The present invention relates to a semiconductor thin film etching process, and more particularly, to a metal film etching process for forming an electrode pattern by selectively etching a metal film.
반도체 제조공정에 있어서, 전극배선을 형성하기 위한 금속막 형성공정은 공정의 안정성과 전극의 전기적 특성을 향상시키기 위하여 다층금속막을 사용하게 되는데, 통상적으로 배리어 메탈로 사용되는 타이타늄텅스텐막(TiW), 주전극 배선용으로 사용되는 구리막(Cu) 및 구리막의 표면이 산화되는 것을 방지하기 위한 금막(Au)으로 이루어진 TiW/Cu/Au 구조의 다층금속막을 형성하게 된다.In a semiconductor manufacturing process, a metal film forming process for forming electrode wirings uses a multilayer metal film in order to improve process stability and electrical characteristics of electrodes. Typically, a titanium tungsten film (TiW) used as a barrier metal, A copper film (Cu) used for the main electrode wiring and a multilayered metal film of a TiW / Cu / Au structure composed of a gold film (Au) for preventing the surface of the copper film from being oxidized are formed.
상기와 같은 다층금속막을 형성하고 난 후 사진 및 식각공정을 실시하여 전극 배선을 형성하게 되는데, Tiw/Cu/Au 구조의 다층금속박막 식각공정에서 상부막인 금막(Au)을 식각하는데에는 두 가지 방법이 사용된다. 첫번째 방법은 습식식각 방법으로서 KI:I2:H20 용액을 사용하는 방법인데, 이러한 습식식각방법은 금막의 불균일한 식각, 금막의 하부막과의 식각속도 차이로 인한 측벽 식각 문제, 부산물 잔류에 따른 식각시간 설정의 어려움 등 많은 문제점이 발생한다. 두번째 방법으로는 건식 식각공정중의 하나인 반응성이온식각(RIE)에 의한 방법인데, 이 방법은 플라즈마 상태에서 진행되므로 금막과 포토레지스트 사이에 상호반응을 유발하여 금막과 포토레지스트 계면에서 폴리머가 형성되기 때문에 포토레지스트 제거 공정시 금막 표면에 폴리머가 잔존하게 되는 문제점이 있다.After forming the multi-layered metal film as described above, photo and etching processes are performed to form electrode wirings. In etching the Au film, which is a top film in the multi-layered metal film etching process of a Ti / Cu / Au structure, Method is used. The first method uses a KI: I2: H2O solution as a wet etching method. Such a wet etching method is a method in which uneven etching of a gold film, etching of a side wall due to a difference in etching rate between a gold film and a lower film, And difficulty in setting the time. The second method is reactive ion etching (RIE), which is one of the dry etching processes. Since this process proceeds in a plasma state, a reaction occurs between the gold film and the photoresist to form a polymer at the interface between the gold film and the photoresist There is a problem that the polymer remains on the surface of the gold film in the photoresist removing step.
도 2 의 (a) 내지 (d) 는 종래의 금속전극배선 패턴을 형성하는 공정을 나타내는 개략적인 도면이다.2 (a) to 2 (d) are schematic views showing a process of forming a conventional metal electrode wiring pattern.
먼저, 도 2 (a) 를 참조하면, 각각의 소자들을 전기적으로 절연하기 위한 HTO, BPSG 등의 층간절연막(12)을 형성한 후 반도체기판 전면에 배리어 메탈로서 타이타늄텅스텐막(TiW)(14)을 증착하고 그 위에 구리막(16)을 증착한 후 구리막(16)의 산화를 방지하기 위하여 상기 구리막(16) 위에 산화 포텐셜이 높은 금막(Au)(18)을 증착하여 TiW/Cu/Au 구조의 다층금속막을 형성하게 된다.2 (a), an interlayer insulating film 12 such as HTO or BPSG is formed for electrically insulating each element, and then a titanium tungsten film (TiW) 14 is formed as a barrier metal on the entire surface of the semiconductor substrate. (Au) 18 having a high oxidation potential is deposited on the copper film 16 to prevent oxidation of the copper film 16 after the copper film 16 is deposited on the TiW / Cu / Layer structure of Au structure.
그 다음, 도 2 (b) 에 도시된 바와 같이, 반도체 기판에 사진공정을 실시하여 상기 금막(18) 위에 포토레지스트(22) 패턴을 형성하게 되는데, 상기 사진공정에는 포토레지스트(22)의 식각에 대한 저항성을 증가시키기 위하여 열 또는 빛으로 포토레지스트(22)를 경화시키는 베이크공정이 포함된다.Next, as shown in FIG. 2B, a photolithography process is performed on the semiconductor substrate to form a photoresist 22 pattern on the gold film 18. In the photolithography process, And a baking step of curing the photoresist 22 with heat or light to increase the resistivity to the resist.
이어서, 도 2 (c) 를 참조하면, 반도체기판에 건식식각공정을 실시하여 노출된 금막(18)을 선택적으로 제거하고 이때 노출되는 구리막(16)을 습식식각하며 다시 노출되는 타이타늄텅스텐막(14)을 습식식각함으로써 금속전극배선(24) 패턴을 형성하게 되는데, 상기 건식식각공정은 플라즈마 상태에서 실시된다.2 (c), a dry etching process is performed on the semiconductor substrate to selectively remove the exposed gold film 18, wet-etch the exposed copper film 16, and expose the exposed titanium tungsten film 14 are wet-etched to form a metal electrode wiring pattern 24, which is performed in a plasma state.
상기 공정에서 상기 금막(18)과 상기 포토레지스트(22)의 계면 영역에는 상기 베이크공정과 상기 건식식각공정에서 가해지는 열로 인하여 다층금속막을 이루는 금막(18)이 포토레지스트(22)와 반응하여 폴리머(26)를 형성하게 된다.The gold film 18 forming the multilayered metal film reacts with the photoresist 22 due to the heat applied in the baking step and the dry etching step in the interface region between the gold film 18 and the photoresist 22 in the above- (26).
이후, 상기 포토레지스트(22)를 제거하게 되는데, 금막(18) 표면에 형성된 상기 폴리머(26) 성분은 제거가 되지 않고, 도 2 (d) 에 도시된 바와 같이, 금막(18) 표면에 남게 되어 전극배선(24)의 전기적 특성에 악영향을 미치게 된다.Then, the photoresist 22 is removed. The polymer 26 component formed on the surface of the gold film 18 is not removed, but remains on the surface of the gold film 18 as shown in FIG. 2 (d) And the electrical characteristics of the electrode wiring 24 are adversely affected.
또한, 상기 건식식각공정에서 제거되는 금막(18)과 포토레지스트(22)가 반응하여 형성되는 폴리머가 금속전극배선들(24) 사이에 브리지를 형성하는 현상이 일어날 수 있다.In addition, the polymer formed by the reaction of the gold film 18 and the photoresist 22 removed in the dry etching process may form a bridge between the metal electrode wirings 24.
따라서, 종래의 금속막 식각공정은 금속전극의 저항을 증가시키며 각각의 금속전극들을 전기적으로 절연시키기 어려운 문제점이 있었다.Therefore, the conventional metal film etching process increases the resistance of the metal electrode, and it is difficult to electrically insulate each metal electrode.
본 발명의 목적은 상기 문제점을 해결하기 위한 것으로서, 전극배선의 표면에 폴리머가 형성되는 것을 방지할 수 있는 반도체 금속막 식각공정을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a semiconductor metal film etching process capable of preventing formation of polymer on the surface of an electrode wiring.
상기 목적을 달성하기 위한 본 발명의 박막 식각공정은, 반도체기판의 층간절연막 상부에 증착된 도전체막을 선택적으로 제거하여 전극배선을 형성하는 박막 식각공정에 있어서, 도전체막 상부에 보호막을 형성하는 단계와, 상기 보호막 상부에 사진공정을 실시하여 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트를 마스크로 사용하여 상기 보호막을 선택적으로 제거하는 단계와, 상기 포토레지스트를 제거하고 상기 보호막을 마스크로 사용하여 상기 도전체막을 선택적으로 제거하여 전극배선을 형성하는 단계와, 상기 전극배선 상부의 보호막을 제거하는 단계로 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a thin film etching process for forming an electrode wiring by selectively removing a conductive film deposited on an interlayer insulating film of a semiconductor substrate, Forming a photoresist pattern by photolithography on the protective film; selectively removing the protective film using the photoresist as a mask; removing the photoresist and using the protective film as a mask; Selectively removing the conductive film to form an electrode wiring; and removing the protective film over the electrode wiring.
상기 박막 식각공정에 있어서, 상기 포토레지스트를 마스크로 사용하여 상기 보호막과 상기 도전체막을 선택적으로 연속 제거하는 것도 바람직하다.In the thin film etching step, it is preferable that the protective film and the conductor film are selectively and successively removed using the photoresist as a mask.
도 1 의 (a) 내지 (c) 는 본 발명의 금속막 식각공정의 일 실시예를 설명하기 위한 도면.1 (a) to 1 (c) are diagrams for explaining an embodiment of a metal film etching process of the present invention.
도 2 의 (a) 내지 (d) 는 종래의 금속막 식각공정을 설명하기 위한 도면.2 (a) to 2 (d) are diagrams for explaining a conventional metal film etching process.
* 도면의 주요 부분에 대한 부호 설명DESCRIPTION OF REFERENCE NUMERALS
10 : 반도체기판 12 : 층간절연막10: semiconductor substrate 12: interlayer insulating film
14,20 : 타이타늄텅스텐막 16 : 구리막14,20: Titanium tungsten film 16: Copper film
18 : 금막 22 : 포토레지스트18: gold film 22: photoresist
24 : 금속전극배선 26 : 폴리머24: metal electrode wiring 26: polymer
이하, 본 발명의 구체적인 실시예를 나타내는 첨부된 도면을 참조하여 더욱 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings showing specific embodiments thereof.
도 1 의 (a) 내지 (c) 는 본 발명의 일 실시예에 따른 금속막 식각공정의 실시예를 설명하기 위한 도면이다.1 (a) to 1 (c) are views for explaining an embodiment of a metal film etching process according to an embodiment of the present invention.
먼저 도 1 (a) 를 참조하면, 반도체기판(10)에 각각의 소자들을 전기적으로 절연하기 위한 HTO, BPSG 등의 층간절연막(12)을 형성한 후 반도체기판 전면에 배리어 메탈로서 타이타늄텅스텐막(TiW)(14)을 증착하고 그 위에 구리막(16)을 증착한 후 구리막(16)의 산화를 방지하기 위하여 상기 구리막(16) 위에 산화 포텐셜이 높은 금막(18)을 증착하여 TiW/Cu/Au 구조의 다층금속막을 형성하며, 상기 금막(18)이 후속의 사진공정에서 도포되는 포토레지스트와 반응하는 것을 방지하기 위한 보호막으로서 습식식각법에 의해 쉽게 제거할 수 있는 타이타늄텅스텐막(20)을 상기 금막(18) 표면에 소정의 두께로 형성한다. 그 다음 반도체 기판에 사진공정을 실시하여 상기 타이타늄텅스텐막(20) 위에 포토레지스트(22) 패턴을 형성하게 되는데, 상기 사진공정에는 포토레지스트(22)의 식각에 대한 저항성을 증가시키기 위하여 열 또는 빛으로 포토레지스트(22)를 경화시키는 베이크공정이 포함된다.First, referring to FIG. 1 (a), an interlayer insulating film 12 such as HTO or BPSG is formed on a semiconductor substrate 10 to electrically insulate each element, and then a titanium tungsten film TiW 14 is deposited and a copper film 16 is deposited thereon to prevent oxidation of the copper film 16. A gold film 18 having a high oxidation potential is deposited on the copper film 16 to form a TiW / A titanium tungsten film 20 (which can be easily removed by a wet etching method) as a protective film for forming a multi-layered metal film of Cu / Au structure and preventing the gold film 18 from reacting with a photoresist applied in a subsequent photolithography process Is formed on the surface of the gold film 18 to a predetermined thickness. A photolithography process is then performed on the semiconductor substrate to form a pattern of photoresist 22 on the titanium tungsten film 20. The photolithography process may include forming a photoresist pattern 22 on the titanium tungsten film 20, And a baking step of curing the photoresist 22 with a baking process.
그 다음, 도 1 (b) 에 도시된 바와 같이, 상기 포토레지스트(22)를 마스크로 사용하여 과산화수소수를 이용한 습식식각법으로 타이타늄텅스텐막(20) 하부의 금막(18)이 노출될 때까지 상기 타이타늄텅스텐막(20)을 제거한 후 상기 포토레지스트(22)를 제거한다.Next, as shown in FIG. 1 (b), until the gold film 18 under the titanium tungsten film 20 is exposed by wet etching using hydrogen peroxide solution using the photoresist 22 as a mask After the titanium tungsten film 20 is removed, the photoresist 22 is removed.
이어서, 상기 타이타늄텅스텐막(20)을 마스크로 사용하여 노출된 금막(18)을 그 하부의 구리막(16)이 노출될 때까지 아르곤 스퍼터링 방식으로 제거하고 노출된 구리막(16)을 질산 및 초산으로 구성된 식각액을 사용한 습식식각법으로 제거한 후 이때 노출된 하부의 타이타늄텅스텐막(14)과 상기 마스크로 사용된 타이타늄텅스텐막(20)을 상기한 바의 방법으로 동시에 제거하여 도 1 (c) 에 도시된 바와 같은 전극배선(24)을 형성한다.Subsequently, the exposed gold film 18 is removed by the argon sputtering method until the underlying copper film 16 is exposed using the titanium tungsten film 20 as a mask, and the exposed copper film 16 is removed by nitric acid and / The titanium tungsten film 14 and the titanium tungsten film 20 used as the mask are simultaneously removed by the wet etching method using an etchant composed of acetic acid, Thereby forming an electrode wiring 24 as shown in Fig.
상기와 같이 이루어지는 본 발명의 금속막 식각공정에서는 다층금속막을 이루는 금막(18)과 포토레지스트(22) 사이에 타이타늄텅스텐막(20)이 삽입되어 금막(18)이 포토레지스트(22)와 반응하는 것이 방지되기 때문에 폴리머 형성이 억제되어 깨끗한 금속전극배선(24) 표면을 얻을 수 있으며 상기 타이타늄텅스텐막을 마스크로 사용한 금속막 제거공정에 있어서 금속막 표면에는 포토레지스트가 존재하지 않기 때문에 폴리머가 형성되지 않으므로 금속전극배선(24) 간에 브리지가 형성되는 것이 방지된다.In the metal film etching process of the present invention as described above, a titanium tungsten film 20 is inserted between the gold film 18 forming the multilayered metal film and the photoresist 22 so that the gold film 18 reacts with the photoresist 22 It is possible to obtain a clean surface of the metal electrode wiring 24. In the metal film removing process using the titanium tungsten film as a mask, since no photoresist is present on the surface of the metal film, no polymer is formed A bridge between the metal electrode wirings 24 is prevented.
따라서, 본 발명은 금속전극의 저항을 감소시킬 수 있을 뿐만 아니라 금속전극 간의 절연 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, the present invention has the effect of not only reducing the resistance of the metal electrode but also improving the insulation reliability between the metal electrodes.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960050298A KR0173178B1 (en) | 1996-10-30 | 1996-10-30 | Etching process for metal layer of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960050298A KR0173178B1 (en) | 1996-10-30 | 1996-10-30 | Etching process for metal layer of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980030819A KR19980030819A (en) | 1998-07-25 |
| KR0173178B1 true KR0173178B1 (en) | 1999-03-20 |
Family
ID=19479867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960050298A KR0173178B1 (en) | 1996-10-30 | 1996-10-30 | Etching process for metal layer of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0173178B1 (en) |
-
1996
- 1996-10-30 KR KR1019960050298A patent/KR0173178B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980030819A (en) | 1998-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080145996A1 (en) | Method for Manufacturing Dielectric Thin Film Capacitor | |
| US5266519A (en) | Method for forming a metal conductor in semiconductor device | |
| US7541275B2 (en) | Method for manufacturing an interconnect | |
| KR900001834B1 (en) | Method of manufacturing semiconductor device | |
| US5340773A (en) | Method of fabricating a semiconductor device | |
| JP5111745B2 (en) | Capacitor and manufacturing method thereof | |
| KR0173178B1 (en) | Etching process for metal layer of semiconductor | |
| KR940003566B1 (en) | Making method for multi-layer wiring of semiconductor device | |
| JPS63122248A (en) | Manufacture of semiconductor device | |
| JPH0558653B2 (en) | ||
| JPH07307550A (en) | Manufacture of electronic component | |
| JP3519641B2 (en) | Semiconductor device having gold wiring and method of manufacturing the same | |
| JP3323264B2 (en) | Method for manufacturing semiconductor device | |
| JP2998454B2 (en) | Method for manufacturing semiconductor device | |
| JP2874216B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100216730B1 (en) | Semiconductor metal film etching step | |
| JPH0569308B2 (en) | ||
| JPH0799199A (en) | Manufacture for semiconductor device | |
| KR100802285B1 (en) | Method for fabricating semiconductor device | |
| KR100192173B1 (en) | Method of forming a tungsten plug in a semiconductor device | |
| JPS62245650A (en) | Manufacture of multilayer interconnection structure | |
| KR100255156B1 (en) | Metal wire forming method in a semiconductor device | |
| KR100192553B1 (en) | Method for fabricating multi-layer metal interconnection | |
| JP2929850B2 (en) | Method for manufacturing semiconductor device | |
| JPH077765B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20040924 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |