JP2000232161A - Method for forming tungsten plug - Google Patents
Method for forming tungsten plugInfo
- Publication number
- JP2000232161A JP2000232161A JP11034336A JP3433699A JP2000232161A JP 2000232161 A JP2000232161 A JP 2000232161A JP 11034336 A JP11034336 A JP 11034336A JP 3433699 A JP3433699 A JP 3433699A JP 2000232161 A JP2000232161 A JP 2000232161A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- film
- via hole
- wiring
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁層を介して下
層配線および上層配線が形成される多層配線型の半導体
装置の製造方法に係り、特に、下層配線と上層配線とを
接続するビアホール内にタングステンプラグを形成する
方法に関する。さらに詳しくは、ビアホール内に十分な
タングステン膜を形成し、もって製品の信頼性を向上す
るのに好適なタングステンプラグの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer, and more particularly, to a method of manufacturing a via hole connecting a lower wiring and an upper wiring. And a method of forming a tungsten plug on the substrate. More specifically, the present invention relates to a method for forming a tungsten plug suitable for forming a sufficient tungsten film in a via hole and thereby improving product reliability.
【０００２】[0002]
【従来の技術】絶縁層を介して下層配線および上層配線
が形成される多層配線型の半導体装置の製造において
は、配線間に形成された絶縁層にビアホールを形成し、
このビアホール内にタングステンプラグを形成すること
により、下層配線と上層配線とを電気的に接続するとい
う方法が採用されている。従来、ビアホール内にタング
ステンプラグを形成する方法としては、図２に示すよう
なものがあった。図２は、半導体装置の製造工程の一部
分を示す断面図である。2. Description of the Related Art In the manufacture of a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer, a via hole is formed in an insulating layer formed between the wirings.
A method of electrically connecting the lower wiring and the upper wiring by forming a tungsten plug in the via hole is adopted. Conventionally, as a method of forming a tungsten plug in a via hole, there has been a method as shown in FIG. FIG. 2 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device.
【０００３】まず、図２に示すように、アルミニウム等
の金属材料からなる下層配線１０上に薄いチタンライド
（ＴｉＮ）膜である反射防止膜１４を形成し、下層配線
１０および反射防止膜１４を覆うようにして反射防止膜
１４上に絶縁層２０を形成する。この絶縁層２０は、テ
トラ・エトキシ・シラン膜等の酸化膜２２と、酸化膜２
２の上面を平坦化するためのＳＯＧ(Spin On Glass)層
２４と、テトラ・エトキシ・シラン膜等の酸化膜２６
と、をその順で積層して形成する。First, as shown in FIG. 2, an anti-reflection film 14, which is a thin titanium nitride (TiN) film, is formed on a lower wiring 10 made of a metal material such as aluminum, and the lower wiring 10 and the anti-reflection film 14 are formed. An insulating layer 20 is formed on the anti-reflection film 14 so as to cover it. The insulating layer 20 includes an oxide film 22 such as a tetraethoxysilane film and an oxide film 2.
SOG (Spin On Glass) layer 24 for flattening the upper surface of oxide film 2 and oxide film 26 such as a tetraethoxysilane film
And are laminated in that order.
【０００４】次いで、絶縁層２０上に下層配線１０に対
応して窓が開いたレジストパターンを形成し、ＲＩＥ(R
eactive Ion Etching)等の異方性エッチングを行ってビ
アホール３０を形成する。ビアホール３０が形成された
ら、ビアホール３０を含む絶縁層２０上にＣＶＤ(Chemi
cal Vaper Deposition)法によりタングステン膜４０を
形成し、タングステン膜４０を絶縁層２０表面付近まで
エッチングして、その上にアルミニウム等の金属材料か
らなる上層配線を形成する。Then, a resist pattern having an open window corresponding to the lower wiring 10 is formed on the insulating layer 20, and RIE (R)
The via hole 30 is formed by performing anisotropic etching such as eactive ion etching. After the via hole 30 is formed, the CVD (Chemi) is formed on the insulating layer 20 including the via hole 30.
A tungsten film 40 is formed by a calvaper deposition method, and the tungsten film 40 is etched to near the surface of the insulating layer 20 to form an upper wiring made of a metal material such as aluminum thereon.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
タングステンプラグの形成方法にあっては、ＣＶＤ法に
よりタングステン膜を形成する際に、半導体装置を４５
０［℃］もの高温状態にさらすため、ＳＯＧ膜２４から
水蒸気ガスが発生し、これにより、図２に示すように、
ビアホール３０内にタングステン膜４０が十分に形成さ
れない場合があった。このため、下層配線１０と上層配
線との電気的接続が不良となるばかりか、最悪の場合は
断線状態となることもあり、製品の信頼性を著しく低下
させる原因になっていた。However, in the conventional method of forming a tungsten plug, when a tungsten film is formed by a CVD method, a semiconductor device is not used.
Since the SOG film 24 is exposed to a high temperature of as high as 0 ° C., water vapor gas is generated from the SOG film 24, as shown in FIG.
In some cases, the tungsten film 40 was not sufficiently formed in the via hole 30. For this reason, not only the electrical connection between the lower layer wiring 10 and the upper layer wiring becomes defective, but also in the worst case, a disconnection state may occur, thereby causing a significant reduction in product reliability.
【０００６】そこで、本発明は、このような従来の技術
の有する未解決の課題に着目してなされたものであっ
て、ビアホール内に十分なタングステン膜を形成し、も
って製品の信頼性を向上するのに好適なタングステンプ
ラグの形成方法を提供することを目的としている。Accordingly, the present invention has been made in view of such unresolved problems of the prior art, and forms a sufficient tungsten film in a via hole to improve the reliability of a product. It is an object of the present invention to provide a method for forming a tungsten plug which is suitable for forming a tungsten plug.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明に係る請求項１記載のタングステンプラグの
形成方法は、絶縁層を介して下層配線および上層配線が
形成される多層配線型の半導体装置の製造工程におい
て、下層配線上に絶縁層を形成し、前記絶縁層上に形成
される予定の上層配線と前記下層配線とを接続するビア
ホールを前記絶縁層に形成し、前記ビアホール内にタン
グステンプラグを形成する方法であって、前記ビアホー
ルを含む前記絶縁層上にＣＶＤ法によりタングステン膜
を形成し、前記タングステン膜を前記絶縁層表面付近ま
でエッチングする一連の処理を、繰り返し行う。According to a first aspect of the present invention, there is provided a method of forming a tungsten plug, comprising the steps of: forming a lower wiring and an upper wiring via an insulating layer; Forming an insulating layer on the lower wiring, forming a via hole in the insulating layer to connect the upper wiring and the lower wiring to be formed on the insulating layer, And forming a tungsten film on the insulating layer including the via hole by a CVD method, and repeatedly performing a series of processes of etching the tungsten film to near the surface of the insulating layer.
【０００８】ここで、タングステン膜を絶縁層表面付近
までエッチングする際には、具体的に、ビアホール内に
空洞が生じている場合は、その空洞がタングステン膜上
に現れるまでエッチングを行うのが好ましい。このよう
にエッチングしたのちにＣＶＤ法により再び成膜を行う
と、１回目の成膜で空洞化したビアホールにおいて、ビ
アホール内にある多少のタングステン膜が核となって成
膜が促進するため、ビアホール内にタングステン膜が形
成されやすくなる。Here, when the tungsten film is etched to the vicinity of the surface of the insulating layer, if a cavity is specifically formed in the via hole, it is preferable to perform the etching until the cavity appears on the tungsten film. . When the film is formed again by the CVD method after the etching as described above, in the via hole hollowed out in the first film formation, the tungsten film in the via hole serves as a nucleus to promote the film formation. A tungsten film is easily formed in the inside.
【０００９】また、ビアホール内が空洞化する原因は、
上記のようにＳＯＧ層からの水蒸気ガスが主たるものと
考えられるため、本発明は、絶縁層にＳＯＧ層が用いら
れている半導体装置の製造工程に適用することが特に有
効であるが、これに限らず、絶縁層にＳＯＧ層が用いら
れていない場合であっても、何らかの原因によりビアホ
ール内が空洞化する場合には、本発明を好適に適用する
ことができる。[0009] The cause of hollowing in the via hole is as follows.
As described above, since the steam gas from the SOG layer is considered to be the main one, it is particularly effective to apply the present invention to the manufacturing process of a semiconductor device using the SOG layer for the insulating layer. The present invention is not limited thereto, and the present invention can be suitably applied to a case where the inside of the via hole is hollowed out for some reason, even when the SOG layer is not used for the insulating layer.
【００１０】また、ビアホールとは、下層配線と上層配
線とを電気的に接続するために形成される穴をいい、こ
れには、コンタクトホールやスルーホール等も含まれ
る。さらに、本発明に係る請求項２記載のタングステン
プラグの形成方法は、絶縁層を介して下層配線及び上層
配線が形成される多層配線型の半導体装置の製造工程に
おいて、下層配線上にＳＯＧ層を有する絶縁層を形成
し、前記絶縁層上に形成される予定の上層配線と前記下
層配線とを接続するビアホールを前記絶縁層に形成し、
前記ビアホール内にタングステンプラグを形成する方法
であって、前記ビアホールを含む前記絶縁層上にＣＶＤ
法によりタングステン膜を形成する成膜ステップと、前
記タングステン膜を前記絶縁層表面付近までエッチング
するエッチングステップと、を含み、前記成膜ステップ
及び前記エッチングステップを繰り返し行う。The via hole is a hole formed for electrically connecting a lower wiring and an upper wiring, and includes a contact hole and a through hole. Further, in the method of forming a tungsten plug according to the present invention, the SOG layer is formed on the lower wiring in a manufacturing process of a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer. Forming an insulating layer having, forming a via hole in the insulating layer to connect the upper wiring and the lower wiring to be formed on the insulating layer;
A method of forming a tungsten plug in the via hole, the method comprising: CVD on the insulating layer including the via hole.
A film forming step of forming a tungsten film by a method, and an etching step of etching the tungsten film to near the surface of the insulating layer, wherein the film forming step and the etching step are repeatedly performed.
【００１１】ここで、エッチングステップは、具体的
に、ビアホール内に空洞が生じている場合は、その空洞
がタングステン膜上に現れるまでエッチングを行うのが
好ましい。このようにエッチングしたのちにＣＶＤ法に
より再び成膜を行うと、１回目の成膜で空洞化したビア
ホールにおいて、ビアホール内にある多少のタングステ
ン膜が核となって成膜が促進するため、ビアホール内に
タングステン膜が形成されやすくなる。Here, in the etching step, when a cavity is specifically formed in the via hole, it is preferable to perform etching until the cavity appears on the tungsten film. When the film is formed again by the CVD method after the etching as described above, in the via hole hollowed out in the first film formation, the tungsten film in the via hole serves as a nucleus to promote the film formation. A tungsten film is easily formed in the inside.
【００１２】また、ビアホールとは、上記請求項１記載
のものと同義である。Further, the via hole has the same meaning as that of the first aspect.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しながら説明する。図１（ａ）〜（ｄ）は、本発
明の実施の形態を示す図であって、半導体装置の製造工
程の一部分を示す断面図である。本発明に係るタングス
テンプラグの形成方法は、絶縁層を介して下層配線およ
び上層配線が形成される多層配線型の半導体装置を製造
する一工程であって、まず、図１（ａ）に示すように、
薄い（例えば、１０００［Å］）チタンライド膜である
反射防止膜１２上にアルミニウム等の金属材料からなる
下層配線１０を形成し、さらにこの下層配線１０上に薄
いチタンライド膜である反射防止膜１４を形成し、下層
配線１０および反射防止膜１２，１４を覆うようにして
反射防止膜１４上に絶縁層２０を形成する。この絶縁層
２０は、テトラ・エトキシ・シラン膜等の酸化膜２２
と、下層配線１０により盛り上がった酸化膜２２の上面
を平坦化するためのＳＯＧ層２４と、テトラ・エトキシ
・シラン膜等の酸化膜２６と、をその順で積層して形成
する。なお、ＳＯＧ層２４は、有機溶剤に溶けたガラス
溶液を酸化膜２２上に回転塗布（スピンコート）し、加
熱処理して形成される。Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are views showing an embodiment of the present invention, and are cross-sectional views showing a part of a manufacturing process of a semiconductor device. The method of forming a tungsten plug according to the present invention is a step of manufacturing a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer. First, as shown in FIG. To
A lower wiring 10 made of a metal material such as aluminum is formed on an antireflection film 12 which is a thin (for example, 1000 [Å]) titanium nitride film, and an antireflection film which is a thin titanium oxide film is formed on the lower wiring 10. Then, an insulating layer 20 is formed on the antireflection film 14 so as to cover the lower wiring 10 and the antireflection films 12 and 14. The insulating layer 20 is made of an oxide film 22 such as a tetraethoxysilane film.
Then, an SOG layer 24 for flattening the upper surface of the oxide film 22 raised by the lower wiring 10 and an oxide film 26 such as a tetraethoxysilane film are stacked in this order. The SOG layer 24 is formed by spin-coating (spin-coating) a glass solution dissolved in an organic solvent on the oxide film 22 and performing a heat treatment.
【００１４】次いで、図示しないが、絶縁層２０上に下
層配線１０に対応して窓が開いたレジストパターンを形
成し、ＲＩＥ等の異方性エッチングを行ってビアホール
３０を形成する。ただし、このエッチングの際には、下
層配線１０上の反射防止膜１４は除去せずに残存させ
る。これを満足するエッチングの条件としては、例え
ば、圧力０．８［Torr］、電力７００［Ｗ］で、エッチ
ングガス（ＣＦ4＋ＣＨＦ3＋Ａｒ＋Ｈｅ）を４０：２
０：８００：２０の割合で用いることが挙げられる。Next, although not shown, a resist pattern having an opening corresponding to the lower wiring 10 is formed on the insulating layer 20, and a via hole 30 is formed by performing anisotropic etching such as RIE. However, in this etching, the antireflection film 14 on the lower wiring 10 is left without being removed. Etching conditions that satisfy this are, for example, a pressure of 0.8 [Torr], a power of 700 [W], and an etching gas (CF 4 + CHF 3 + Ar + He) of 40: 2.
It may be used in a ratio of 0: 800: 20.
【００１５】こうしてビアホール３０が形成されたら、
ビアホール３０を含む絶縁層２０上にＣＶＤ法によりタ
ングステン膜４０を形成する。このＣＶＤの条件として
は、例えば、圧力９０［Torr］、温度４５０［℃］で、
ＣＶＤガス（ＷＦ6＋Ｈ3）を１：１０の割合で用いるこ
とが挙げられる。こうした条件下でＣＶＤを行うと、絶
縁層２０に形成されたいくつかのビアホール３０内に
は、ＳＯＧ層２４からの水蒸気ガスにより空洞が生じ
る。After the via hole 30 is formed,
A tungsten film 40 is formed on the insulating layer 20 including the via hole 30 by a CVD method. The conditions of this CVD are, for example, a pressure of 90 [Torr], a temperature of 450 [° C.]
The use of a CVD gas (WF 6 + H 3 ) at a ratio of 1:10 is mentioned. When CVD is performed under such conditions, cavities are generated in some via holes 30 formed in the insulating layer 20 by the steam gas from the SOG layer 24.
【００１６】次いで、図１（ｂ）に示すように、ＲＩＥ
等の異方性エッチングを行ってタングステン膜４０を絶
縁層２０表面付近までエッチングする。具体的には、ビ
アホール３０内に生じた空洞が絶縁層２０表面に現れる
までエッチングを行う。このエッチングの条件として
は、例えば、圧力２００［mTorr］、電力３００［Ｗ］
で、エッチングガス（ＳＦ6＋Ａｒ）を２：１の割合で
用いることが挙げられる。Next, as shown in FIG.
The tungsten film 40 is etched to the vicinity of the surface of the insulating layer 20 by performing anisotropic etching such as. Specifically, the etching is performed until a cavity generated in the via hole 30 appears on the surface of the insulating layer 20. The etching conditions include, for example, a pressure of 200 [mTorr] and a power of 300 [W].
Then, an etching gas (SF 6 + Ar) is used at a ratio of 2: 1.
【００１７】次いで、図１（ｃ）に示すように、上記同
様の条件下で、ビアホール３０を含む絶縁層２０上にＣ
ＶＤ法により再びタングステン膜４０を形成する。する
と、１回目の成膜で空洞化したビアホール３０におい
て、ビアホール３０内にある多少のタングステン膜が核
となって成膜が促進し、ビアホール３０内に十分なタン
グステン膜４０が形成される。Next, as shown in FIG. 1C, under the same conditions as described above, a C layer is formed on the insulating layer 20 including the via hole 30.
The tungsten film 40 is formed again by the VD method. Then, in the via hole 30 hollowed out by the first deposition, the tungsten film in the via hole 30 becomes a nucleus to promote the deposition, and a sufficient tungsten film 40 is formed in the via hole 30.
【００１８】そして、図１（ｄ）に示すように、絶縁層
２０上全体にアルミニウム等の配線材料を塗布し、これ
を公知のフォト・リソ工程により適宜パターンニングし
て、上層配線５０を形成するとともに、下層配線１０と
上層配線５０とを、ビアホール３０内に形成されたタン
グステン膜４０により接続する。このようにして、本実
施の形態では、下層配線１０上に絶縁層２０を形成し、
絶縁層２０上に形成される予定の上層配線５０と下層配
線１０とを接続するビアホール３０を絶縁層２０に形成
した状態において、ビアホール３０を含む絶縁層２０上
にＣＶＤ法によりタングステン膜４０を形成し、タング
ステン膜４０を絶縁層２０表面付近までエッチングする
一連の処理を２回行った。Then, as shown in FIG. 1D, a wiring material such as aluminum is applied to the entire surface of the insulating layer 20 and is appropriately patterned by a known photolithography process to form an upper wiring 50. At the same time, the lower wiring 10 and the upper wiring 50 are connected by the tungsten film 40 formed in the via hole 30. In this manner, in the present embodiment, the insulating layer 20 is formed on the lower wiring 10,
A tungsten film 40 is formed on the insulating layer 20 including the via hole 30 by a CVD method in a state where the via hole 30 connecting the upper wiring 50 and the lower wiring 10 to be formed on the insulating layer 20 is formed in the insulating layer 20. Then, a series of processes for etching the tungsten film 40 to near the surface of the insulating layer 20 was performed twice.
【００１９】このため、１回目の成膜でＳＯＧ層２４か
らの水蒸気ガスによりビアホール３０内が空洞化して
も、２回目の成膜により、ビアホール３０内にある多少
のタングステン膜４０が核となって成膜が促進し、ビア
ホール３０内に十分なタングステン膜４０が形成され
る。したがって、従来に比して、下層配線１０と上層配
線５０との電気的接続が不良となる可能性が低減し、も
って製品の信頼性を向上することができる。For this reason, even if the inside of the via hole 30 is hollowed by the steam gas from the SOG layer 24 in the first film formation, some tungsten film 40 in the via hole 30 becomes a nucleus by the second film formation. As a result, film formation is promoted, and a sufficient tungsten film 40 is formed in the via hole 30. Therefore, the possibility that the electrical connection between the lower wiring 10 and the upper wiring 50 becomes defective is reduced as compared with the related art, and the reliability of the product can be improved.
【００２０】なお、上記実施の形態においては、ビアホ
ール３０を含む絶縁層２０上にＣＶＤ法によりタングス
テン膜４０を形成し、タングステン膜４０を絶縁層２０
表面付近までエッチングする一連の処理を２回行った
が、これに限らず、さらに複数回行ってもよい。このよ
うに多数回にわたって処理を行うと、ビアホール３０内
にタングステン膜４０をより確実に形成することができ
る。In the above embodiment, the tungsten film 40 is formed on the insulating layer 20 including the via hole 30 by the CVD method, and the tungsten film 40 is
Although the series of processes for etching to the vicinity of the surface is performed twice, the present invention is not limited to this, and may be further performed a plurality of times. By performing the process many times as described above, the tungsten film 40 can be more reliably formed in the via hole 30.
【００２１】[0021]
【発明の効果】以上説明したように、本発明に係る請求
項１または２記載のタングステンプラグの形成方法によ
れば、１回目の成膜でビアホール内が空洞化しても、２
回目以降の成膜により、ビアホール内にある多少のタン
グステン膜が核となって成膜が促進し、ビアホール内に
十分なタングステン膜が形成されるので、従来に比し
て、下層配線と上層配線との電気的接続が不良となる可
能性が低減し、もって製品の信頼性を向上することがで
きるという効果が得られる。As described above, according to the method for forming a tungsten plug according to the first or second aspect of the present invention, even if the inside of the via hole is hollowed out by the first deposition,
In the subsequent film formation, a small amount of the tungsten film in the via hole serves as a nucleus to promote film formation, and a sufficient tungsten film is formed in the via hole. And the likelihood that the electrical connection with the semiconductor device becomes defective is reduced, thereby improving the reliability of the product.
【図１】本発明の実施の形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】従来のタングステンプラグの形成方法を示す断
面図である。FIG. 2 is a cross-sectional view illustrating a conventional method for forming a tungsten plug.
１０ 下層配線 １２，１４ 反射防止膜 ２０ 絶縁層 ２２，２６ 酸化膜 ２４ ＳＯＧ層 ３０ ビアホール ４０ タングステン膜 ５０ 上層配線 DESCRIPTION OF SYMBOLS 10 Lower wiring 12,14 Antireflection film 20 Insulating layer 22,26 Oxide film 24 SOG layer 30 Via hole 40 Tungsten film 50 Upper wiring
Claims (2)
形成される多層配線型の半導体装置の製造工程におい
て、下層配線上に絶縁層を形成し、前記絶縁層上に形成
される予定の上層配線と前記下層配線とを接続するビア
ホールを前記絶縁層に形成し、前記ビアホール内にタン
グステンプラグを形成する方法であって、 前記ビアホールを含む前記絶縁層上にＣＶＤ法によりタ
ングステン膜を形成し、前記タングステン膜を前記絶縁
層表面付近までエッチングする一連の処理を、繰り返し
行うことを特徴とするタングステンプラグの形成方法。In a manufacturing process of a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer, an insulating layer is formed on the lower wiring and is formed on the insulating layer. A method of forming a via hole for connecting an upper layer wiring and the lower layer wiring in the insulating layer and forming a tungsten plug in the via hole, wherein a tungsten film is formed on the insulating layer including the via hole by a CVD method. A series of processes for etching the tungsten film up to near the surface of the insulating layer are repeatedly performed.
形成される多層配線型の半導体装置の製造工程におい
て、下層配線上にＳＯＧ層を有する絶縁層を形成し、前
記絶縁層上に形成される予定の上層配線と前記下層配線
とを接続するビアホールを前記絶縁層に形成し、前記ビ
アホール内にタングステンプラグを形成する方法であっ
て、 前記ビアホールを含む前記絶縁層上にＣＶＤ法によりタ
ングステン膜を形成する成膜ステップと、前記タングス
テン膜を前記絶縁層表面付近までエッチングするエッチ
ングステップと、を含み、前記成膜ステップ及び前記エ
ッチングステップを繰り返し行うことを特徴とするタン
グステンプラグの形成方法。2. In a manufacturing process of a multilayer wiring type semiconductor device in which a lower wiring and an upper wiring are formed via an insulating layer, an insulating layer having an SOG layer is formed on the lower wiring and formed on the insulating layer. Forming a via hole connecting the upper wiring and the lower wiring to be formed in the insulating layer, and forming a tungsten plug in the via hole, the tungsten being formed on the insulating layer including the via hole by CVD. A method for forming a tungsten plug, comprising: a film forming step of forming a film; and an etching step of etching the tungsten film to near the surface of the insulating layer, wherein the film forming step and the etching step are repeatedly performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03433699A JP3565316B2 (en) | 1999-02-12 | 1999-02-12 | Method of forming tungsten plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03433699A JP3565316B2 (en) | 1999-02-12 | 1999-02-12 | Method of forming tungsten plug |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000232161A true JP2000232161A (en) | 2000-08-22 |
| JP3565316B2 JP3565316B2 (en) | 2004-09-15 |
Family
ID=12411313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03433699A Expired - Fee Related JP3565316B2 (en) | 1999-02-12 | 1999-02-12 | Method of forming tungsten plug |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3565316B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007081020A (en) * | 2005-09-13 | 2007-03-29 | Denso Corp | Method for manufacturing semiconductor device |
-
1999
- 1999-02-12 JP JP03433699A patent/JP3565316B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007081020A (en) * | 2005-09-13 | 2007-03-29 | Denso Corp | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3565316B2 (en) | 2004-09-15 |
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