JPH09213829A - Ｂｇａ型ｉ／ｏフォーマットを使用した高性能デジタルｉｃパッケージ及びバイメタル充填バイア技術による単層セラミックス基板 - Google Patents

Ｂｇａ型ｉ／ｏフォーマットを使用した高性能デジタルｉｃパッケージ及びバイメタル充填バイア技術による単層セラミックス基板

Info

Publication number
JPH09213829A
JPH09213829A JP8143210A JP14321096A JPH09213829A JP H09213829 A JPH09213829 A JP H09213829A JP 8143210 A JP8143210 A JP 8143210A JP 14321096 A JP14321096 A JP 14321096A JP H09213829 A JPH09213829 A JP H09213829A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
layer
thickness
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8143210A
Other languages
English (en)
Japanese (ja)
Inventor
Norman L Greenman
エル． グリーンマン ノーマン
M P Ramachandra Panicker
ピー． ラマチャンドラ パニッカー エム．
Jorge M Hernandez
エム． ヘルナンデズ ジョージ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Circuit Components Inc
Original Assignee
Circuit Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Circuit Components Inc filed Critical Circuit Components Inc
Publication of JPH09213829A publication Critical patent/JPH09213829A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
JP8143210A 1995-06-06 1996-06-05 Ｂｇａ型ｉ／ｏフォーマットを使用した高性能デジタルｉｃパッケージ及びバイメタル充填バイア技術による単層セラミックス基板 Pending JPH09213829A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47109595A 1995-06-06 1995-06-06
US08/471095 1995-06-06

Publications (1)

Publication Number Publication Date
JPH09213829A true JPH09213829A (ja) 1997-08-15

Family

ID=23870234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8143210A Pending JPH09213829A (ja) 1995-06-06 1996-06-05 Ｂｇａ型ｉ／ｏフォーマットを使用した高性能デジタルｉｃパッケージ及びバイメタル充填バイア技術による単層セラミックス基板

Country Status (6)

Country Link
JP (1) JPH09213829A (en:Method)
KR (1) KR970003879A (en:Method)
DE (1) DE19622650A1 (en:Method)
GB (1) GB2301937A (en:Method)
MX (1) MXPA96002171A (en:Method)
TW (1) TW299487B (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035968A (ja) * 1999-07-01 2001-02-09 Intersil Corp ボールグリッドアレイを具えるパワー半導体実装パッケージ
US10115674B2 (en) 2015-09-11 2018-10-30 Toshiba Memory Corporation Semiconductor device including electromagnetic interference (EMI) shielding layer and method for manufacturing the semiconductor device
WO2026078946A1 (ja) * 2024-10-09 2026-04-16 株式会社村田製作所 モジュール

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
GB9818474D0 (en) * 1998-08-26 1998-10-21 Hughes John E Multi-layer interconnect package for optical devices & standard semiconductor chips
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
GB2377080B (en) 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
TW272311B (en:Method) * 1994-01-12 1996-03-11 At & T Corp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035968A (ja) * 1999-07-01 2001-02-09 Intersil Corp ボールグリッドアレイを具えるパワー半導体実装パッケージ
US10115674B2 (en) 2015-09-11 2018-10-30 Toshiba Memory Corporation Semiconductor device including electromagnetic interference (EMI) shielding layer and method for manufacturing the semiconductor device
WO2026078946A1 (ja) * 2024-10-09 2026-04-16 株式会社村田製作所 モジュール

Also Published As

Publication number Publication date
KR970003879A (ko) 1997-01-29
GB9611726D0 (en) 1996-08-07
GB2301937A (en) 1996-12-18
DE19622650A1 (de) 1996-12-12
MXPA96002171A (es) 2002-04-19
TW299487B (en:Method) 1997-03-01

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