JPH09205236A - Thin-film diode and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film diode which comprises a fine element area exceeding the limit of the resolution of an aligner by a method wherein a metal layer is formed on a glass substrate, a resist pattern is etched, a lower-part electrode is formed, an insulator layer is formed and an upper-part electrode is formed so as to cover the lower-part electrode. SOLUTION: A first metal layer is formed on a glass substrate 1, and a resist pattern whose shape is identical to that of the lower-part electrode is formed so as to be used as a first etching mask. The first metal layer is dry- etched and treated, and a first metal layer 12a comprising a lower step part 6 is formed. A second etching mask 5a is formed on the first metal layer 12a. The second etching mask 5a is removed, and an insulator layer which covers the surface of the lower-part electrode is then formed. A second metal layer is formed so as to cover the insulator layer, a resist pattern is formed on it, and an upper-part electrode is formed. Thereby, a high-definition liquid-crystal display device can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film diode and a method for manufacturing the same, and more particularly to a thin film diode as an active element for driving a liquid crystal and a method for manufacturing the same.

[0002]

2. Description of the Related Art The structure of a thin film diode as an active element for driving a liquid crystal to display a predetermined image,
A conventional example will be described with reference to FIGS. 28 and 29. FIG. 28 is a schematic enlarged view showing the planar shape of the thin film diode in the conventional example. FIG. 29 is a schematic enlarged view showing the AA cross-sectional shape in FIG. 28. As shown in FIG. 28, the conventional thin film diode 39 is a portion where the lower electrode 32 and the upper electrode 34 intersect, and the structure thereof is the lower electrode 32 formed on the glass substrate 31 as shown in FIG. Lower electrode 3
2 and an upper electrode 34 that covers the lower electrode 32 with the insulator layer 33 interposed therebetween, and has a "metal layer-insulator layer-metal layer" structure.

Next, a conventional method of manufacturing a thin film diode will be described with reference to FIGS. 29, 30, 31, and 32. As shown in FIG. 30, a first metal layer 35 is formed on a glass substrate 31 by a sputtering method or a chemical vapor deposition method, and a resist pattern is formed on the first metal layer 35 by a photolithography method. Then, using this resist pattern as an etching mask 36, a lower electrode 32 is formed by a wet etching method or a dry etching method as shown in FIG.
Next, the etching mask 36 is removed, and as shown in FIG. 32, an insulator layer 33 is formed on the surface of the lower electrode 32 by an anodic oxidation method using the lower electrode 32 as an anode. Further, a second metal layer (not shown) is formed on the insulator layer 33 by a sputtering method or a chemical vapor deposition method,
A resist pattern (not shown) is formed on the second metal layer by photolithography. Thereafter, using this resist pattern as an etching mask, patterning is performed by a wet etching method or a dry etching method to form an upper electrode 34 as shown in FIG. As a result, it is possible to form the thin film diode 39 having a "metal layer-insulator layer-metal layer" structure as an active element.

The minimum element size is determined by the resolution of the exposure apparatus used when the lower electrode 32 and the upper electrode 34 are processed and formed by the photolithography technique.

[0005]

When a thin-film diode is used as an active element for driving a liquid crystal to display a predetermined image, the parasitic capacitance of the thin-film diode is set to be equal to the capacitance of the liquid crystal layer in order to improve the device characteristics. It should be about 1. On the other hand, the ratio of the lighting area of the pixel to the MIM element area needs to be as large as possible. On the other hand, if the thickness of the insulator layer is increased, the capacity is reduced, but the driving characteristics are deteriorated. Therefore, it is necessary to reduce the element area of the thin film diode. Although the size of the element pattern currently commercialized is about 3 μm at the smallest, the minimum element area of the thin film diode in the prior art is limited by the resolution of the exposure apparatus.

Particularly in a fine liquid crystal display, the capacitance of the liquid crystal layer becomes smaller as the pixel area is reduced, and it is necessary to further reduce the parasitic capacitance of the thin film diode. Along with this, an exposure apparatus with high resolution for forming fine elements is required, but an exposure apparatus with high resolution has a drawback that throughput is slow. Further, when the element becomes finer and the dimension becomes close to the limit of the exposure apparatus, the slight difference in the focus and the difference in the resist dimension due to the distribution of the exposure amount become a non-negligible amount. That is, there is a problem that it is difficult to manufacture a thin film diode having a fine element area exceeding the resolution limit of the exposure apparatus.

Therefore, an object of the present invention is to provide a thin film diode having a fine element area exceeding the resolution limit of an exposure apparatus and a method for manufacturing the same.

[0008]

In order to achieve the above-mentioned object, a method of manufacturing a thin film diode according to a first aspect of the present invention is to control the element area of the thin film diode and miniaturize it. To etch the first metal layer using the resist pattern,
A technique for reducing the dimension of the resist pattern by ashing is adopted, a new minute exposed portion is formed on the first metal layer, and the first metal layer is formed by using the resist pattern having the reduced dimension of the pattern. By etching, a convex lower electrode having a minute lower step portion is formed.
After that, an insulator layer is formed on the lower part of the lower electrode,
Further, it is characterized in that an upper electrode is formed on the insulator layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a thin film diode, wherein the step of directly forming a resist pattern on the first metal layer is performed on the first metal layer. The present invention is characterized in that an insulating protective layer made of a thin film which is more excellent in etching resistance than a metal layer is formed, and a resist pattern is formed on the insulating protective layer.

According to a third aspect of the present invention, there is provided a method of manufacturing a thin film diode, wherein a lower electrode is formed by etching a first metal layer using a resist pattern, and then a dimension of the resist pattern is reduced by an ashing process. This technique is used to form a new minute exposed portion on the upper surface of the lower electrode. Then, in a state where the resist pattern remains, an insulating layer is formed on a minute exposed portion of the lower electrode, and an upper electrode is further formed on the insulating layer.

According to a fourth aspect of the present invention, a thin film diode is symmetrically arranged with a central convex portion sandwiched therebetween and has a convex lower electrode having a pair of minute lower step portions having substantially the same area, and a lower step of the lower electrode. And an upper electrode formed on the lower step of the lower electrode via the insulating layer, and the pair of parasitic capacitances are substantially equal to each other.

According to a fifth aspect of the present invention, in a thin film diode, a lower electrode is disposed symmetrically in a state of being separated in the center and has a pair of minute exposed portions having substantially the same area, and a minute exposed portion of the lower electrode. An insulating layer to be formed and an upper electrode formed on the minute exposed portion of the lower electrode via the insulating layer are provided, and a pair of parasitic capacitances are substantially equal to each other.

[0013]

The element area of the thin film diode manufactured according to the present invention can be determined by the size of the ashing treatment of the resist pattern used as the etching mask when the lower electrode is formed by the photolithography technique. The size of the resist pattern to be ashed can be controlled by the time of ashing, and the size of the element area can be determined without depending on the resolution of the exposure apparatus. Therefore, it is possible to form a thin film diode having a finer element area that exceeds the resolution limit of the exposure apparatus. Furthermore, the ashing process is isotropic and evenly reduces the overall pattern.
Therefore, a pair of minute exposed portions are formed on the lower electrode so as to be symmetrical with respect to the resist pattern and have substantially the same area. As a result, it is possible to form a pair of thin film diodes that have an extremely minute element area and parasitic capacitance, and their respective values are substantially equal to each other.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic enlarged perspective view of a liquid crystal display device as a target of the first embodiment of the present invention. FIG. 2 is a schematic enlarged view showing a planar shape of a unit pixel and a thin film diode when applied to an active matrix substrate of a liquid crystal display device in the first embodiment of the present invention. FIG. 3 is a schematic enlarged view showing an AA cross-sectional shape in FIG.

First, with respect to the structure of the liquid crystal display device which is the object of the first embodiment of the present invention, the overall structure of the liquid crystal display device for color display will be described with reference to FIG. The two glass substrates 1 and 41 are arranged so as to face each other, and the stripe-shaped data lines 42 and the drive electrodes 43 arranged in a dot matrix form on one glass substrate 1.
And the data line 42 and each drive electrode 43
A thin film diode (TFD) 48 is provided as an active element (switching element) between and. An alignment film 45 made of a polyimide resin film for aligning the liquid crystal is provided on the data line 42, the drive electrode 43, and the thin film diode 48.

On the lower surface of the other glass substrate 41, a color filter 47 is provided so that a black matrix 46 is provided in the boundary area thereof, and red (R), green (G) and blue (B) color filter elements are provided. Correspond to each drive electrode 43 on one glass substrate 1. On the lower surface of the color filter 47, a stripe-shaped scanning electrode (not shown) is provided in a direction orthogonal to the data line 42 on one glass substrate 1 via an insulating film (not shown). Further, an alignment film 51 made of a polyimide resin film for aligning the liquid crystal is provided on the scan electrodes.

Then, a liquid crystal (not shown) is sealed between the alignment film 45 and the alignment film 51, and the polarization axes thereof are orthogonal to each other outside the glass substrates 1 and 41 on the other side. Polarizing plates 49 and 50 are arranged respectively. If the formation of the color filter 47 is omitted, a monochrome display liquid crystal display device is obtained.

Next, the structure of the thin film diode 48 in this liquid crystal display device will be described with reference to FIGS. 2 and 3. As shown in FIG. 3, the thin film diode 48 has a structure in which a convex lower electrode 2 having a minute lower step portion 8 formed on a glass substrate 1 which is an insulator, and a lower step portion 8 of the lower electrode.
A "metal layer-insulation layer-metal layer" structure is formed by the insulator layer 3 formed on the upper electrode and the upper electrode 4 formed on the lower step portion 8 of the lower electrode via the insulator layer 3. There is.

The lower step portions 8 of the lower electrodes are symmetrically arranged with the central convex portion 14 interposed therebetween, and the lower step portions 8 of the pair of lower electrodes are minute and have substantially the same area. Further, as shown in FIG. 2, the upper electrode 4 forms a part of the drive electrode 43 and has a plane pattern shape that intersects with the lower step portion 8 of the lower electrode.

As the material of each member, tantalum (Ta) is used for the lower electrode 2, tantalum oxide (TaOx) formed by anodic oxidation method for the insulator layer 3, and indium tin oxide for the upper electrode 4. (ITO) is used.

Next, the manufacturing process of the thin film diode in the first embodiment of the present invention will be described by taking the case of being applied to the active matrix substrate of the liquid crystal display device as an example. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG.
3 and 14 are schematic enlarged views showing a sectional shape for explaining the manufacturing process of the thin film diode in the first embodiment of the present invention.

First, as shown in FIG. 6, a first metal layer 12 made of tantalum having a film thickness of 50 nm to 500 nm is formed on a glass substrate 1 by a sputtering method.
Next, as shown in FIG. 7, a resist pattern having the same shape as that of the lower electrode 2 is formed on the first metal layer 12 by a photolithography method, and this is used as a first etching mask 5.
And Next, as shown in FIG. 8, a dry etching process is performed on the first metal layer 12 using the first etching mask 5 to advance the etching to a midpoint in the thickness direction to form a convex shape having a lower step portion 6. To form the first metal layer 12a.

The dry etching process for the first metal layer 12 is performed at 100 sccm to 3 in a dry etching apparatus.
Sulfur hexafluoride (SF6) was introduced at a flow rate of 00 sccm, and oxygen of 0 sccm to 100 sccm was added thereto,
The total pressure is 50 mTorr to 200 mTorr, and the RF power of 100 W to 1000 W (13.5
6 MHz) is applied to generate plasma.

Next, as shown in FIG. 9, the pattern size is reduced by ashing the first etching mask 5 on the first metal layer 12a.
The second etching mask 5a is formed. At the same time, a pair of novel minute exposed portions 7 of the first metal layer are formed on the upper step 10 of the first metal layer with the second etching mask 5a interposed therebetween. Since this ashing process is isotropic and uniformly reduces the entire pattern, the minute exposed portions 7 of the pair of first metal layers are symmetrical and substantially equal to each other with the second etching mask 5a interposed therebetween. Formed in the area.

The condition of this ashing treatment is that oxygen is introduced into the dry etching apparatus at a flow rate of 50 sccm to 300 sccm, and 0 sccm to 100 sccc is introduced.
m sulfur hexafluoride (SF6) was added to bring the total pressure to 10
0mTorr ~ 300mToor, 100 to this
It is performed by plasma generated by applying RF power (13.56 MHz) of W to 500 W.

In the etching treatment of the first metal layer 12, as shown in FIG. 12, the etching treatment of the first metal layer 12 is performed until the glass substrate 1 is exposed, and then the first metal layer 12b. Then, the first etching mask 5 may be subjected to an ashing process to form a second etching mask 5a and a minute exposed portion 7a of the first metal layer as shown in FIG. The pattern size (difference in pattern size between the first etching mask 5 and the second etching mask 5a) reduced by this ashing process is 100 nm to 1000 nm.

Next, the first metal layer 12a is formed by using the second etching mask 5a having a small pattern size.
Dry etching process is performed, and as shown in FIG.
A convex lower electrode 2 having a pair of minute lower step portions 8 is formed. The lower step portion 8 of the pair of lower electrodes is provided with the second
Are symmetrically arranged with the etching mask 5a in between, and are formed to have substantially equal areas. The etching processing conditions at this time are the same as the dry etching processing of the first metal layer 12. In the case of the first metal layer 12b shown in FIG. 13, the lower electrode 2 can be formed by the same method.

Further, in this etching process, the etching process time is set so that the lower step portion 8 of the lower electrode shown in FIG. 10 remains, but in the etching of the first metal layer 12a, the first process shown in FIG. The etching process time is set so that the lower step 6 of the metal layer is completely removed and the lower step 8 of the lower electrode shown in FIG. 10 remains. By setting the end of the removal of the lower step portion 6 of the first metal layer as a guide, the etching processing time can be easily set.

Next, as shown in FIG. 11, after removing the second etching mask 5a, tantalum oxide (TaOx) is covered by an anodic oxidation method using the lower electrode 2 as an anode so as to cover the surface of the lower electrode 2. An insulator layer 3 made of is formed. At this time, the anodic oxidation was performed by using a 0.01-1% citric acid solution, and a platinum electrode was used as a cathode.
A voltage of 10 to 100 V is applied between the material and tantalum, which is the material of.

Next, a second metal layer (not shown) made of indium tin oxide (ITO) is formed so as to cover the insulator layer 3 by the sputtering method. The processing condition of the sputtering at this time is 100 s in the sputtering apparatus.
Introducing ccm of argon gas and ₂ sccm of oxygen (O ₂ ) gas, setting the pressure to 5 mTorr to 30 mTorr, and applying 1 KW to 3 KW of RF power (13.56 MH).
z) is applied to generate plasma. Further, the second metal layer is formed on the second metal layer by photolithography, as shown in FIG.
A resist pattern (not shown) having the same shape as that of the upper electrode 4 shown in FIG. 3 is formed, and the upper electrode 4 as shown in FIG. 3 is formed by a wet etching method using the resist pattern as an etching mask.

At this time, the side wall portion 18 of the insulator layer shown in FIG.
The upper electrode 4 is scarcely formed. Therefore, the upper electrode 4 can be separated at the side wall portion 18 of the insulator layer. The side wall portion 1 of the insulator layer
In the case where the upper electrode 4 is slightly formed at 8 and the separation of the upper electrode 4 is insufficient at the side wall portion 18 of the insulator layer, light etching is further performed using a 5% hydrochloric acid aqueous solution. By doing so, it is possible to surely separate them.

Through the above steps, the pair of thin film diodes are arranged symmetrically with the convex portion 14 of the lower electrode interposed therebetween, have an extremely minute element area and parasitic capacitance, and their values are substantially equal to each other. Was completed.

In the dry etching treatment of the first metal layer 12, by controlling the amount of oxygen gas (O ₂ ) introduced into the dry etching apparatus, as shown in FIG. The lower electrode 2c in which the etching sectional shape of the portion 13 is tapered may be formed. As a result, pixel defects due to disconnection in the growth boundary region 23 of the upper electrode 4 shown by the broken line in FIG. 3 can be reduced.

As described above, the thin film diode manufactured according to this embodiment has an extremely fine element area as compared with the conventional thin film diode. The device area of the thin-film diode manufactured by the conventional manufacturing method is the area of the intersection of the lower electrode 32 and the upper electrode 34 as shown in FIG.
The minimum value of the element area depends on the resolution of the exposure apparatus used when the lower electrode 32 and the upper electrode 34 are formed by the photolithography technique. As a result, it is difficult to manufacture a thin film diode having an element area exceeding the resolution limit of the exposure apparatus by the conventional manufacturing method.

However, as shown in FIG. 3, the element area of the thin film diode of this embodiment has the convex lower electrode 2 having a minute lower step portion 8 and the insulation on the lower step portion 8 of the lower electrode. The area of the portion where the upper electrode 4 formed via the body layer 3 overlaps, and the width of the upper electrode 4 shown in FIG. 2 is the exposure used when the upper electrode 4 is formed by a photolithography technique. Although depending on the resolution of the device, the width of the lower step portion 8 of the lower electrode shown in FIG.
It can be determined by the time of ashing treatment of the etching mask used when forming the. As a result, the element area of the thin film diode of this embodiment can be made smaller than the resolution limit of the exposure apparatus.

A second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a schematic enlarged view showing a sectional shape for explaining a thin film diode and a method for manufacturing the same in the second embodiment of the present invention.

As shown in FIG. 4, a convex lower electrode 2 having a minute lower step portion 8 is formed on a glass substrate 1 which is an insulator.
a and an insulator layer 3a formed on the lower step portion 8 of the lower electrode
And the lower step portion 8 of the lower electrode through the insulator layer 3a.
A thin film diode composed of the upper electrode 4a formed above is formed. The lower step portions 8 of the lower electrodes are symmetrically arranged with the central convex portion 14a interposed therebetween, and the lower step portions 8 of the pair of lower electrodes are minute and have substantially equal areas. The material of each member is the same as that of the first embodiment.

Next, the manufacturing process of the thin film diode in the second embodiment of the present invention will be described by taking the case of being applied to the active matrix substrate of the liquid crystal display device as an example. 15, FIG. 16, FIG. 17, FIG. 18, FIG. 19, FIG.
FIG. 1 is a schematic enlarged view showing a cross-sectional shape for explaining a manufacturing process of a thin film diode according to a second embodiment of the present invention.

First, similarly to the first embodiment, the glass substrate 1
50nm-500nm by sputtering method
The first metal layer 12 made of tantalum having a film thickness of is formed. Next, as shown in FIG. 15, tantalum oxide (TaO) having a film thickness of 10 nm, which is superior in etching resistance to tantalum by sputtering, is formed on the first metal layer 12.
x) An insulating protective layer 9 made of a film is formed. Next, a resist pattern having the same shape as the lower electrode 2 is formed on the insulating protective layer 9 by photolithography, and this is used as a first etching mask 5.

Next, the insulating protective layer 9 and the first metal layer 12 are dry-etched by using the first etching mask 5, and the etching is advanced halfway in the thickness direction, as shown in FIG. An insulating protective layer 9a such as
A convex first metal layer 12c having a lower step portion 6 is formed. The dry etching process for the insulating protective layer 9 and the first metal layer 12 is performed under the same process conditions as the dry etching process for the first metal layer 12 in the first embodiment. The portion removed by this etching process is only the insulating protective layer 9 and the first metal layer 12.
May remain as is.

Next, the ashing process of the first etching mask 5 on the insulating protective layer 9a is performed, and the ashing process shown in FIG.
As shown in FIG. 7, a second etching mask 5a smaller than the pattern size of the first etching mask 5 is formed. At the same time, a new minute exposed portion 11 of the insulating protective layer is formed on the insulating protective layer 9a. This ashing process is performed under the same processing conditions as the ashing process in the first embodiment.

In the etching treatment of the insulating protective layer 9 and the first metal layer 12, the first metal layer 1 is exposed until the glass substrate 1 is exposed as shown in FIG.
2 is performed to form the first metal layer 12b, and then the first etching mask 5 is ashed to remove the second etching mask 5a and the insulating protective layer as shown in FIG. The minute exposed portion 11 may be formed.

Next, the insulating protective layer 9a and the first metal layer 12c are dry-etched using the second etching mask 5a having a small pattern size,
As shown in FIG. 18, a convex lower electrode 2a having a pair of minute lower step portions 8 is formed. The lower step portions 8 of the pair of lower electrodes are formed so that their areas are substantially equal to each other, as in the case of the first embodiment.

In this embodiment, the dry etching condition is 100 mtorr to 200 m in total pressure in the dry etching apparatus as compared with the case of the first embodiment.
It was set as high as torr. This increases the isotropy of etching and the provision of the insulating protection layer 9a makes the side wall portion 20 of the upper stage of the lower electrode have an undercut shape as shown in FIG.

The first metal layer 12 shown in FIG.
In the case of b, the lower electrode 2a can be formed by the same method.
In this etching process, the etching process time is set so that the lower step portion 8 of the lower electrode shown in FIG. 18 remains, but in the etching process of the insulating protective layer 9a and the first metal layer 12a shown in FIG. The etching process time is set so that the lower step portion 6 of the first metal layer and the minute exposed portion 11 of the insulating protective layer are completely removed and the lower step portion 8 of the lower electrode remains.

Next, as shown in FIG. 19, after removing the second etching mask 5a, the lower electrode 2a is used as an anode, and is made of tantalum oxide (TaOx) so as to cover the surface of the lower electrode 2a by an anodic oxidation method. Insulator layer 3
a is formed. The anodic oxidation conditions are the same as the anodic oxidation conditions in the first embodiment.

Next, a second metal layer (not shown) made of indium tin oxide (ITO) is formed by sputtering so as to cover the insulator layer 3a. The processing conditions of the sputtering method at this time are the same as in the case of the first embodiment. Further, a resist pattern (not shown) having the same shape as the upper electrode 4a shown in FIG. 4 is formed on the second metal layer by photolithography, and the resist pattern is used as an etching mask to form a resist pattern as shown in FIG. The upper electrode 4a is formed.

At this time, the side wall portion 18 of the insulator layer shown in FIG.
The upper electrode 4a is hardly formed on a. In particular, when the side wall portion 18a of the insulator layer has an undercut shape as in this embodiment, the formation of the upper electrode 4a on the side wall portion 18a of the insulator layer is further restricted. Therefore, the separation of the upper electrode 4a at the side wall portion 18 of the insulator layer becomes easier than in the first embodiment.

If the upper electrode 4a is slightly formed on the side wall 18a of the insulating layer and the separation of the upper electrode 4a at the side wall 18a of the insulating layer is insufficient, further Light separation treatment using a 5% aqueous solution of hydrochloric acid enables reliable separation.

Through the above steps, a pair of thin film diodes are arranged symmetrically with the convex portion 14a of the lower electrode interposed therebetween, have an extremely fine element area and parasitic capacitance, and their values are substantially equal to each other. Was completed.

As described above, the element area of the thin film diode manufactured according to this embodiment can be made smaller than the resolution limit of the exposure apparatus, as in the first embodiment. Further, as shown in FIG. 4, the side wall portion 1 of the insulator layer
8a has an undercut shape. As a result, the formation of the upper electrode 4a on the side wall portion 18a of the insulator layer is further restricted, and the separation at the side wall portion 18a of the upper electrode 4a becomes easier than in the first embodiment.

A third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a schematic enlarged view showing a sectional shape for explaining a thin film diode and a method for manufacturing the same in the third embodiment of the present invention.

As shown in FIG. 5, on the glass substrate 1 which is an insulator, they are symmetrically arranged in a state of being separated at the center,
A lower electrode 2b having a pair of minute exposed portions 19 having substantially the same area, an insulating layer 3b formed so as to cover the surface of the lower electrode 2b, and formed on the lower electrode 2b via the insulating layer 3b. A pair of thin film diodes composed of the upper electrodes 4b are formed. The material of each member is
The same material as in the first embodiment is used.

Next, the manufacturing process of the thin film diode in the third embodiment of the present invention will be explained by taking the case of being applied to the active matrix substrate of the liquid crystal display device as an example. 22, FIG. 23, FIG. 24, and FIG. 25 are schematic enlarged views showing sectional shapes for explaining the manufacturing process of the thin film diode in the third embodiment of the present invention.

First, as shown in FIG. 22, the glass substrate 1
50nm-500nm by sputtering method
Forming a first metal layer 12d of tantalum having a film thickness of, and then forming a resist pattern having the same shape as the pattern of the lower electrode 2b shown in FIG. 5 on the first metal layer 12d by photolithography. This is used as the first etching mask 5.

Next, as shown in FIG. 23, the first metal layer 12d is dry-etched using the first etching mask 5 to form the lower electrode 2b.
The dry etching process for the first metal layer 12d is performed under the same processing conditions as the dry etching process for the first metal layer 12 in the first embodiment.

Next, as shown in FIG. 24, an ashing process is performed on the first etching mask 5 on the lower electrode 2b to form a second etching mask 5a smaller than the pattern size of the first etching mask 5. Form.
At the same time, a pair of new minute exposed portions 19 of the lower electrode are formed on the lower electrode 2b. The minute exposed portions 19 of the pair of lower electrodes are provided with the second etching mask 5
They are arranged symmetrically with respect to a and are formed to have substantially equal areas. The conditions of this ashing process are the same as those of the ashing process of the first embodiment.

Next, as shown in FIG. 25, the lower electrode 2b is left in the state where the second etching mask 5a remains.
An insulating layer 3b made of tantalum oxide (TaOx) is formed so as to cover the surface of the lower electrode 2b by an anodic oxidation method using the as an anode. The conditions for anodic oxidation at this time are as follows:
The conditions are the same as the conditions for the anodic oxidation in the example.

Next, with the second etching mask 5a remaining, the insulator layer 3 is formed by sputtering.
A second metal layer (not shown) made of indium tin oxide (ITO) is formed so as to cover b. The processing conditions of the sputtering method at this time are the same as in the case of the first embodiment. At this time, the second metal layer is separated by the second etching mask 5a at approximately the center of the lower electrode 2b.

Further, a resist pattern having the same shape as the upper electrode 4b shown in FIG. 5 is formed on the second metal layer by photolithography. As shown in FIG. 26, the upper electrode 4b is formed by wet etching using the third etching mask 15. This time,
The upper electrode 4b is separated by the second etching mask 5a at approximately the center of the lower electrode 2b. Finally, as shown in FIG. 5, the third etching mask 15 is removed. At this time, the second etching mask 5a is removed at the same time, but it may be left.

Through the above steps, a pair of thin film diodes, which are symmetrically arranged in the state of being separated at the center, have an extremely minute element area and parasitic capacitance, and have respective values substantially equal to each other, are completed. did.

As described above, the device area of the thin-film diode manufactured according to the present embodiment has the lower electrode 2b and the insulating layer 3 on the minute exposed portion 19 of the lower electrode as shown in FIG.
It is the area of the portion where the upper electrode 4b formed via b overlaps. As a result, similarly to the first embodiment, the element area of the thin film diode can be reduced beyond the resolution limit of the exposure apparatus without depending on the resolution of the exposure apparatus.

In the first to third embodiments, the thin film diode in which the first metal layer is tantalum, the insulator layer is tantalum oxide, and the second metal layer is indium tin oxide is described. The invention is not limited to thin film diodes using such materials.
It is possible to obtain the effect of reducing the element area and the parasitic capacitance of thin film diodes made of materials other than the above.

Further, in the description of the embodiments, the description of the electrode connection method when forming the insulator layer by the anodic oxidation method is omitted, but as shown in FIG. 26, a plurality of adjacent lower electrodes 2 are formed. Are connected by the lower electrode connecting line 22, and anodization is performed, and after forming the upper electrode, the lower electrodes 2 are separated one by one by an etching method. The same applies to the lower electrodes 2a, 2b, 2c.

[0065]

As described above, according to the present invention, the element area of the thin film diode is determined by the time for ashing the etching mask used when the lower electrode is formed by the photolithography technique. As a result, the minimum element area of the thin-film diode can be made smaller than the resolution limit of the exposure apparatus without depending on the resolution of the exposure apparatus, and fine and uniform elements can be formed. As a result, the parasitic capacitance of the thin film diode can be made smaller than that of the conventional one, so that a high-definition liquid crystal display device can be realized. Further, according to the present invention, since a pair of thin film diodes has a structure in which they are combined in series, they can be used as a back-to-back diode.

[Brief description of drawings]

FIG. 1 is a schematic enlarged perspective view illustrating an overall configuration of a liquid crystal display device according to first to third embodiments of the present invention.

FIG. 2 is a schematic enlarged view showing a planar shape for explaining the thin-film diode and the method for manufacturing the same in the first embodiment of the present invention.

3 is a schematic enlarged view showing an AA cross-sectional shape in FIG.

FIG. 4 is a schematic enlarged view showing a cross-sectional shape for explaining a thin film diode and a method for manufacturing the thin film diode according to a second embodiment of the present invention.

FIG. 5 is a schematic enlarged view showing a sectional shape for explaining a thin film diode and a method for manufacturing the same in a third embodiment of the present invention.

FIG. 6 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 7 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 8 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 9 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first example of the present invention.

FIG. 10 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 11 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 12 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first example of the present invention.

FIG. 13 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first embodiment of the present invention.

FIG. 14 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the first example of the present invention.

FIG. 15 is a schematic enlarged view showing the cross-sectional shape for explaining the manufacturing process of the thin film diode in the second embodiment of the present invention.

FIG. 16 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the second example of the present invention.

FIG. 17 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the second example of the present invention.

FIG. 18 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the second example of the present invention.

FIG. 19 is a schematic enlarged view showing the cross-sectional shape for explaining the manufacturing process of the thin film diode in the second example of the present invention.

FIG. 20 is a schematic enlarged view showing the cross-sectional shape for explaining the manufacturing process of the thin film diode in the second embodiment of the present invention.

FIG. 21 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the second example of the present invention.

FIG. 22 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the third embodiment of the present invention.

FIG. 23 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the third embodiment of the present invention.

FIG. 24 is a schematic enlarged view showing a sectional shape for explaining a manufacturing process of the thin film diode in the third example of the present invention.

FIG. 25 is a schematic enlarged view showing a cross-sectional shape for explaining the manufacturing process of the thin film diode in the third embodiment of the present invention.

FIG. 26 is a schematic enlarged view showing the cross-sectional shape for explaining the manufacturing process of the thin-film diode in the third embodiment of the present invention.

FIG. 27 is a schematic enlarged view showing a planar shape for explaining a manufacturing process of the thin film diode in the first to third embodiments of the present invention.

FIG. 28 is a schematic enlarged view showing a planar shape for explaining a thin film diode structure in a conventional example.

29 is a schematic enlarged view showing a cross-sectional shape taken along line AA in FIG. 28.

FIG. 30 is a schematic enlarged view showing a cross-sectional shape for explaining a manufacturing process of a thin film diode in a conventional example.

FIG. 31 is a schematic enlarged view showing a cross-sectional shape for explaining a manufacturing process of a thin film diode in a conventional example.

FIG. 32 is a schematic enlarged view showing a cross-sectional shape for explaining a manufacturing process of a thin film diode in a conventional example.

[Explanation of symbols]

 1 Glass Substrate 2 Lower Electrode 2a Lower Electrode 2b Lower Electrode 2c Lower Electrode 3 Insulator Layer 3a Insulator Layer 3b Insulator Layer 4 Upper Electrode 4a Upper Electrode 4b Upper Electrode 5 First Etching Mask 5a Second Etching Mask 6th Lower part 7 of the first metal layer 7 Micro exposed part of the first metal layer 7a Small exposed part of the first metal layer 8 Lower part of the lower electrode 9 Insulating protective layer 9a Insulating protective layer 10 Of the first metal layer Upper part 11 Minute exposed part of insulating protective layer 12 First metal layer 12a First metal layer 12b First metal layer 12c First metal layer 12d First metal layer 13 Lower electrode Side wall part 14 Convex Part 14a Convex part 15 Third etching mask 18 Side wall part of insulator layer 18a Side wall part of insulator layer 19 Minute exposed part 20 Side wall part of lower electrode upper stage 22 Lower electrode connection line 23 Growth boundary Area 31 Glass Substrate 32 Lower Electrode 33 Insulator Layer 34 Upper Electrode 35 First Metal Layer 36 Etching Mask 39 Thin Film Diode 41 Glass Substrate 42 Data Line 43 Drive Electrode 45 Alignment Film 46 Black Matrix 47 Color Filter 48 Thin Film Diode 49 Polarizing Plate 50 Polarizing plate 51 Alignment film

Claims (5)

[Claims] 1. A step of forming a first metal layer on a glass substrate, and the first metal layer using a resist pattern formed on the surface of the first metal layer by a photolithography method as a first etching mask. And a step of forming a new minute exposed portion of the first metal layer on the first metal layer by reducing the dimension of the resist pattern by ashing, and reducing the dimension of the pattern. Forming a convex lower electrode having a minute lower step by etching the first metal layer using the formed resist pattern as a second etching mask; and anodizing to cover the surface of the lower electrode. To form an insulator layer by the above method, and a step of forming an upper electrode so as to cover at least the lower part of the lower electrode via the insulator layer. A method for manufacturing a thin film diode, which is characterized by the following. 2. A step of forming a first metal layer on a glass substrate, and an insulating protective layer made of a thin film having a higher etching resistance than the first metal layer on the surface of the first metal layer. First, a step of forming and a resist pattern formed by a photolithography method on the surface of the insulating protective layer are formed.
As an etching mask for the insulating protective layer and the first protective layer.
The step of etching the metal layer, the step of forming a minute exposed portion of a new insulating protective layer on the insulating protective layer by reducing the dimension of the resist pattern by an ashing treatment, and the dimension of the pattern. Forming a convex lower electrode having a minute lower step by etching the insulating protective layer and the first metal layer using the reduced resist pattern as a second etching mask; and A thin film diode characterized by including a step of forming an insulator layer by an anodic oxidation method so as to cover the surface, and a step of forming an upper electrode so as to cover at least a lower step portion of the lower electrode via the insulator layer. Manufacturing method. 3. The step of forming a first metal layer on a glass substrate, and the first metal layer using a resist pattern formed on the surface of the first metal layer by a photolithography method as a first etching mask. Forming a lower electrode by etching, forming a new exposed portion of the lower electrode on the lower electrode by reducing the dimension of the resist pattern by ashing, and reducing the pattern dimension. A step of forming an insulator layer by an anodization method so as to cover the surface of the lower electrode with the resist pattern remaining, and the surface of the lower electrode with the resist pattern having a reduced pattern size remaining. And a step of forming an upper electrode so as to cover the insulating layer with an insulating layer interposed therebetween. . 4. A convex lower electrode having a pair of minute lower step portions that are symmetrically arranged with a central convex portion sandwiched therebetween and have substantially equal areas, and an insulator layer formed on the lower step portion of the lower electrode. ,
A thin film diode comprising: an upper electrode formed on a lower portion of a lower electrode via an insulating layer; and a pair of parasitic capacitances being substantially equal to each other. 5. A lower electrode having a pair of minute exposed portions which are symmetrically arranged in a state of being separated at the center and have substantially equal areas, an insulator layer formed on the minute exposed portion of the lower electrode, and the insulating layer. A thin film diode comprising an upper electrode formed on a minute exposed portion of the lower electrode via a body layer and having a pair of parasitic capacitances substantially equal to each other.