JPH0917918A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0917918A JPH0917918A JP7161097A JP16109795A JPH0917918A JP H0917918 A JPH0917918 A JP H0917918A JP 7161097 A JP7161097 A JP 7161097A JP 16109795 A JP16109795 A JP 16109795A JP H0917918 A JPH0917918 A JP H0917918A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- circuit board
- metal block
- heat dissipation
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、移動体通信器やコ−ド
レス電話機などの高周波の電力増幅のために使用され
る、混成集積回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit used for high frequency power amplification in mobile communication devices and cordless telephones.
【０００２】[0002]
【従来の技術】消費電力が大きいパワ−ＦＥＴ等の半導
体チップを用いた混成集積回路では、半導体チップでの
発熱を効率良く逃がすため、種々の工夫がされている。
図４および図５を用いて、従来の集積回路を説明する。2. Description of the Related Art In a hybrid integrated circuit using a semiconductor chip such as a power FET, which consumes a large amount of power, various measures have been taken in order to efficiently dissipate heat generated in the semiconductor chip.
A conventional integrated circuit will be described with reference to FIGS. 4 and 5.
【０００３】混成集積回路は、回路基板１と、放熱板２
と、メタルブロック３と、半導体チップ４と、蓋５とか
ら構成される。The hybrid integrated circuit includes a circuit board 1 and a heat sink 2.
, A metal block 3, a semiconductor chip 4, and a lid 5.
【０００４】回路基板１は四角形状の基板で、基板の表
面には回路パタ−ン６が形成され、基板の裏面には金属
層７が設けられて放熱板２と半田付けされる。なお、基
板にはプリント基板または、セラミック基板が用いられ
ている。また、回路基板１の所定の位置にはメタルブロ
ック３を収容するために、開口が四角形の貫通孔８が設
けられる。貫通孔８を介して対向する開口縁近傍の回路
基板１の表面には、回路パタ−ン６と電気的に接続され
た電極パッド９が形成される。電極パッド９の表面に
は、後述の金線のワイヤ−１４との接続強度を高めるた
め、金メッキ層１０が設けられる。回路パタ−ン６の所
定位置には、チップ抵抗、チップキャパシタ、チップイ
ンダクタ等の回路素子１１が実装される。The circuit board 1 is a quadrangular board, a circuit pattern 6 is formed on the front surface of the board, and a metal layer 7 is provided on the back surface of the board to be soldered to the heat sink 2. A printed board or a ceramic board is used as the board. Further, a through hole 8 having a quadrangular opening is provided at a predetermined position of the circuit board 1 to accommodate the metal block 3. Electrode pads 9 electrically connected to the circuit pattern 6 are formed on the surface of the circuit board 1 near the opening edge facing each other through the through hole 8. A gold plating layer 10 is provided on the surface of the electrode pad 9 in order to enhance the connection strength of a gold wire, which will be described later, with the wire-14. Circuit elements 11 such as a chip resistor, a chip capacitor, and a chip inductor are mounted at predetermined positions of the circuit pattern 6.
【０００５】放熱板２は、真鍮の表面にニッケルメッキ
層（図示せず）および錫メッキ層（図示せず）が積層形
成された長方形の金属板により形成される。錫メッキ層
は、放熱板２の表面と回路基板の裏面の金属層を半田付
けする際に、半田の付着強度を高めるために設けられ
る。また、真鍮の表面には錫メッキ層が形成されにくい
ため、真鍮と錫メッキ層の間にはニッケルメッキ層が介
在して設けられる。金属板の長手方向の両端部は裏面方
向に一旦折り曲げられた後、さらに外側方向に折り曲げ
られる。このように折り曲げられた放熱板２の両端をシ
ャ−シ−等に固定することにより、シャ−シ−等と放熱
板２の中央部の間には空間部Ｓが形成され、放熱のため
の有効面積が確保される。この放熱板２の表面には、回
路基板１の裏面の金属層７が半田１２を用いて固定され
る。The heat dissipation plate 2 is formed of a rectangular metal plate in which a nickel plating layer (not shown) and a tin plating layer (not shown) are laminated on the surface of brass. The tin-plated layer is provided to increase the adhesive strength of the solder when soldering the metal layer on the front surface of the heat dissipation plate 2 and the back surface of the circuit board. Further, since a tin plating layer is hard to be formed on the surface of brass, a nickel plating layer is provided between the brass and the tin plating layer. Both ends in the longitudinal direction of the metal plate are once bent toward the back surface and then further bent outward. By fixing both ends of the heat dissipation plate 2 bent in this way to a chassis or the like, a space S is formed between the chassis or the like and the central part of the heat dissipation plate 2 for heat dissipation. An effective area is secured. The metal layer 7 on the back surface of the circuit board 1 is fixed to the front surface of the heat dissipation plate 2 using solder 12.
【０００６】メタルブロック３は、放熱板２と同様に、
直方体形状の真鍮の表面にニッケルメッキ層および金メ
ッキ層が積層形成されたものである。縦横の寸法は貫通
孔の縦横の寸法よりも一回り小さく形成され、また高さ
は回路基板１とほぼ同じ厚みとなるように形成される。
このため、メタルブロック３を貫通孔８の内部に収容す
ると、メタルブロック３と回路基板１の表面はほぼ同一
平面となる。なお、メタルブロック３の底面は、放熱板
２の表面に半田１２を用いて固定される。The metal block 3 is similar to the heat sink 2 in that
The nickel-plated layer and the gold-plated layer are laminated on the surface of a rectangular parallelepiped brass. The vertical and horizontal dimensions are formed to be slightly smaller than the vertical and horizontal dimensions of the through hole, and the height is formed to be approximately the same thickness as the circuit board 1.
Therefore, when the metal block 3 is housed inside the through hole 8, the surfaces of the metal block 3 and the circuit board 1 are substantially flush with each other. The bottom surface of the metal block 3 is fixed to the surface of the heat dissipation plate 2 with solder 12.
【０００７】半導体チップ４は、銀ペ−スト等の導電性
接着剤１３を用いて、メタルブロック３の表面に固定さ
れる。なお、使用する半導体チップ４はベアチップであ
ることが多い。このため、半田付けする際に使用するフ
ラックスが半導体チップ４に付着して誤動作等の原因と
なるため、半導体チップ４の固定には導電性接着剤１３
が一般的に用いられる。半導体チップ４の入出力端子
（図示せず）と金メッキ層１０は、線径が約２０μｍと
極めて細い金線のワイヤ−１４により接続される。な
お、半導体チップ４を流れる電流量が大きいため、半導
体チップ４の入出力端子と金メッキ層１０の間は、複数
本のワイヤ−１４により接続される。接続にはワイヤ−
ボンディングの手段が用いられる。The semiconductor chip 4 is fixed to the surface of the metal block 3 by using a conductive adhesive 13 such as silver paste. The semiconductor chip 4 used is often a bare chip. Therefore, since the flux used for soldering adheres to the semiconductor chip 4 and causes malfunctions, the conductive adhesive 13 is used to fix the semiconductor chip 4.
Is generally used. The input / output terminal (not shown) of the semiconductor chip 4 and the gold plating layer 10 are connected by a wire 14 which is an extremely thin gold wire having a wire diameter of about 20 μm. Since the amount of current flowing through the semiconductor chip 4 is large, the input / output terminals of the semiconductor chip 4 and the gold plating layer 10 are connected by a plurality of wires -14. Wire for connection
Bonding means are used.
【０００８】蓋５は、回路基板１よりわずか大きい形状
の四角板１５と、コ字状の側壁１６とから一体に形成さ
れる。コ字状の側壁１６は、四角板１５の３つの端縁に
垂設するように設けられる。側壁１６の厚みは、回路基
板１に実装する回路素子１１の厚みより大きく設定され
る。コ字状の側壁１６の底部と放熱板２の折り曲げた両
端とを突き合わせるようにして、蓋５は回路基板１に被
せられる。この後、蓋５は放熱板２に半田付けされる。
回路基板１に接続されたリ−ド線またはリ−ド端子等
（図示せず）は、側壁１６が設けられていない蓋５の側
面を通して引き出される。なお、蓋５は、放熱板２と同
様、表面にニッケルメッキ層および錫メッキ層が積層形
成された真鍮で形成される。The lid 5 is integrally formed from a square plate 15 having a shape slightly larger than the circuit board 1 and a U-shaped side wall 16. The U-shaped side wall 16 is provided so as to vertically extend to the three end edges of the square plate 15. The thickness of the side wall 16 is set to be larger than the thickness of the circuit element 11 mounted on the circuit board 1. The lid 5 is placed on the circuit board 1 so that the bottom portion of the U-shaped side wall 16 and the bent ends of the heat dissipation plate 2 are butted against each other. After that, the lid 5 is soldered to the heat dissipation plate 2.
Lead wires or lead terminals (not shown) connected to the circuit board 1 are drawn out through the side surface of the lid 5 where the side wall 16 is not provided. The lid 5 is made of brass having a nickel-plated layer and a tin-plated layer laminated on the surface, like the heat sink 2.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、混成集
積回路を製造する場合、回路基板１に回路素子１１を実
装する工程や、回路素子１１を実装した後の回路基板１
およびメタルブロック３を放熱板２に半田付けする工程
において、半田付けする際に使用したフラックスが金メ
ッキ層１０に付着するという問題があった。この結果、
金メッキ層１０に付着したフラックスを充分に洗浄して
取り除かないと、半導体チップ４の入出力端子と金メッ
キ層１０は極めて細いワイヤ−１４によって接続される
ため、ワイヤ−１４と金メッキ層１０の接続強度が小さ
くなり、充分な接続強度を確保することができなかっ
た。このため、混成集積回路に振動等が加わると、ワイ
ヤ−１４が金メッキ層１０から外れてしまうという品質
上の問題があった。さらに、金メッキ層１０を充分に洗
浄する工程や、金メッキ層１０の洗浄状態をチェックす
る工程が必要不可欠となり、製造工程が著しく繁雑化し
ていた。However, when manufacturing a hybrid integrated circuit, the step of mounting the circuit element 11 on the circuit board 1 or the circuit board 1 after mounting the circuit element 11 is performed.
Also, in the step of soldering the metal block 3 to the heat sink 2, there is a problem that the flux used for soldering adheres to the gold plating layer 10. As a result,
Unless the flux attached to the gold plating layer 10 is sufficiently washed and removed, the input / output terminals of the semiconductor chip 4 and the gold plating layer 10 are connected by a very thin wire-14, so the connection strength between the wire-14 and the gold plating layer 10 is high. Was small, and sufficient connection strength could not be secured. Therefore, when vibration or the like is applied to the hybrid integrated circuit, there is a problem in quality that the wire -14 comes off from the gold plating layer 10. Furthermore, the step of thoroughly cleaning the gold plating layer 10 and the step of checking the cleaning state of the gold plating layer 10 are indispensable, and the manufacturing process is significantly complicated.
【００１０】また、混成集積回路を小形化するためには
回路基板１を小さくする必要がある。これに伴い、必然
的に貫通孔８の開口の形状が小さくなる。開口の形状が
大きい場合には、貫通孔８によって露出した放熱板２の
表面部分に半田１２が多少はみ出したとしても、はみ出
した半田１２を避けて貫通孔８の内部にメタルブロック
３を収容することができるため、メタルブロック３の底
面がはみ出した半田１２と重なるということはなかっ
た。しかしながら、開口の形状が小さくなると、はみ出
した半田１２の上にメタルブロック３の底面が重なり、
メタルブロック３が傾いたり、メタルブロック３と放熱
板２との間に間隙ができるという問題があった。このた
め、メタルブロック３と放熱板２を確実に固定できず、
放熱性が悪化したり、ワイヤ−ボンディングが行ないに
くくなっていた。Further, in order to downsize the hybrid integrated circuit, it is necessary to make the circuit board 1 small. Along with this, the shape of the opening of the through hole 8 inevitably becomes smaller. When the shape of the opening is large, even if the solder 12 slightly protrudes from the surface portion of the heat dissipation plate 2 exposed by the through hole 8, the metal block 3 is housed inside the through hole 8 while avoiding the protruding solder 12. Therefore, the bottom surface of the metal block 3 did not overlap with the protruding solder 12. However, when the shape of the opening becomes smaller, the bottom surface of the metal block 3 overlaps the protruding solder 12 and
There is a problem that the metal block 3 is inclined or a gap is formed between the metal block 3 and the heat dissipation plate 2. Therefore, the metal block 3 and the heat sink 2 cannot be securely fixed,
The heat dissipation was deteriorated and it was difficult to perform wire bonding.
【００１１】そこで、本発明は、上記問題を解決した混
成集積回路の提供を目的とする。Therefore, an object of the present invention is to provide a hybrid integrated circuit which solves the above problems.
【００１２】[0012]
【課題を解決するための手段】本発明は、上記目的を達
成するため以下のように構成される。すなわち、第一
に、基板の表裏面には回路パタ−ンおよび金属層がそれ
ぞれ形成されるとともに貫通孔が設けられた回路基板
と、該回路基板の裏面の金属層に半田付けされた放熱板
と、前記貫通孔に収容されて該放熱板に固定されたメタ
ルブロックと、該メタルブロックの表面に導電接着剤で
固定された半導体チップを備えた混成集積回路におい
て、前記回路パタ−ンに導電接着剤を用いて電気的に接
続されたボンディングパッドを有し、前記メタルブロッ
クは前記放熱板に導電接着剤で固定されるとともに、前
記半導体チップの入出力端子は前記ボンディングパッド
にワイヤ−接続されたものであり、第二に、第一の発明
において、回路基板の裏面の貫通孔の周縁部には半田が
付着しない領域を設けたものであり、第三に、第一の発
明において、回路基板の裏面の貫通孔の周縁部には半田
レジスト膜を設けたものである。The present invention is configured as described below to achieve the above object. That is, first, a circuit board in which circuit patterns and metal layers are respectively formed on the front and back surfaces of the board and through holes are provided, and a heat dissipation plate soldered to the metal layers on the back surface of the circuit board. And a metal block housed in the through hole and fixed to the heat dissipation plate and a semiconductor chip fixed to the surface of the metal block with a conductive adhesive, the conductive pattern is electrically connected to the circuit pattern. It has a bonding pad electrically connected using an adhesive, the metal block is fixed to the heat dissipation plate with a conductive adhesive, and the input / output terminals of the semiconductor chip are wire-connected to the bonding pad. Secondly, in the first aspect of the invention, the peripheral portion of the through hole on the back surface of the circuit board is provided with a region where solder does not adhere, and thirdly, in the first aspect of the invention. Te, the peripheral portion of the back surface of the circuit board through-hole is provided with a solder resist film.
【００１３】[0013]
【作用】回路基板の裏面と放熱板の表面の間のみが半田
付けされ、メタルブロックの底面と放熱板の表面は導電
接着剤を用いて固定される。このため、使用する半田の
量が減り、回路基板の表面に形成された回路パタ−ンへ
のフラックスの付着が少なくなる。また、回路パタ−ン
と電気的に接続される電極パッド上にボンディングパッ
ドを設けるとともに、このボンディングパッドは導電接
着剤を用いて電極パッドによって固定される。このた
め、ボンディングパッドの表面にはフラックスが付着す
ることがなくなり、常に清浄な状態に保たれる。半導体
チップの入出力端子は、この清浄なボンディングパッド
の表面と、極めて細いワイヤ−で接続される。この結
果、ワイヤ−とボンディングパッドの間の接続強度が高
くなる。Operation: Only the back surface of the circuit board and the front surface of the heat dissipation plate are soldered, and the bottom surface of the metal block and the front surface of the heat dissipation plate are fixed using a conductive adhesive. Therefore, the amount of solder used is reduced, and the adhesion of flux to the circuit pattern formed on the surface of the circuit board is reduced. A bonding pad is provided on the electrode pad electrically connected to the circuit pattern, and the bonding pad is fixed by the electrode pad using a conductive adhesive. Therefore, the flux does not adhere to the surface of the bonding pad, and the bonding pad is always kept in a clean state. The input / output terminals of the semiconductor chip are connected to the surface of this clean bonding pad by an extremely thin wire. As a result, the connection strength between the wire and the bonding pad is increased.
【００１４】回路基板の裏面の貫通孔の周縁部には半田
が付着しない領域を設けたので、貫通孔によって露出し
た放熱板の表面部分には半田がはみ出さない。このた
め、メタルブロックの底面がはみ出した半田と重なり、
傾くということがなくなり、また、メタルブロックの底
面と放熱板の間に間隙が生じないので放熱状態が良くな
る。Since the area where the solder does not adhere is provided in the peripheral portion of the through hole on the back surface of the circuit board, the solder does not protrude to the surface portion of the heat dissipation plate exposed by the through hole. Therefore, the bottom surface of the metal block overlaps with the protruding solder,
There is no inclination, and there is no gap between the bottom surface of the metal block and the heat dissipation plate, which improves the heat dissipation state.
【００１５】[0015]
（実施例１）図１を用いて、第一の実施例を説明する。
従来例と同じ構成部分は、同じ番号を用いて説明は簡略
化する。なお、蓋５については、従来例と同じであるの
で説明は省略する。(Embodiment 1) A first embodiment will be described with reference to FIG.
The same components as those of the conventional example will be denoted by the same reference numerals and the description will be simplified. Since the lid 5 is the same as the conventional example, the description thereof is omitted.
【００１６】本発明の混成集積回路は、回路基板１と、
ボンディングパッド１７と、放熱板２と、メタルブロッ
ク３と、半導体チップ４とから構成され、従来の混成集
積回路の構成と異なる点は、ボンディングパッド１７を
設けたことである。The hybrid integrated circuit of the present invention comprises a circuit board 1,
The bonding pad 17, the heat dissipation plate 2, the metal block 3, and the semiconductor chip 4 are provided, and the difference from the configuration of the conventional hybrid integrated circuit is that the bonding pad 17 is provided.
【００１７】ボンディングパッド１７は、真鍮の表面に
金メッキ層（図示せず）を形成した、縦２．５ｍｍ、横
０．５ｍｍ、高さ０．２ｍｍ程度の小形の四角板であ
る。ボンディングパッド１７は、電極パッド９の表面に
銀ペ−スト等の導電性接着剤１３を用いて固定される。
なお、電極パッド９は、回路基板１の所定位置に設けら
れた貫通孔８を介して対向する開口縁近傍の回路基板１
の表面に、回路パタ−ン６と電気的に接続して形成され
る。なお、真鍮の表面と金メッキ層の間には、両者の接
続強度を高めるためにニッケルメッキ層を介在させても
良い。The bonding pad 17 is a small square plate having a length of 2.5 mm, a width of 0.5 mm, and a height of 0.2 mm, in which a gold plating layer (not shown) is formed on the surface of brass. The bonding pad 17 is fixed to the surface of the electrode pad 9 by using a conductive adhesive 13 such as silver paste.
The electrode pads 9 are arranged in the circuit board 1 in the vicinity of the opening edges facing each other through the through holes 8 provided at predetermined positions of the circuit board 1.
Is electrically connected to the circuit pattern 6 on the surface. A nickel plating layer may be interposed between the brass surface and the gold plating layer in order to enhance the connection strength between the two.
【００１８】放熱板２の表面には、回路基板１の裏面の
金属層７が半田１２を用いて固定される。The metal layer 7 on the back surface of the circuit board 1 is fixed to the front surface of the heat dissipation plate 2 using solder 12.
【００１９】メタルブロック３を貫通孔８の内部に収容
すると、メタルブロック３と回路基板１の表面はほぼ同
一平面となる。なお、メタルブロック３の底面は、導電
性接着剤１３を用いて放熱板２の表面に固定される。こ
の結果、従来のように半田を使用しないので、メタルブ
ロック３を固定する際にはフラックスが電極パッド９等
に付着することがなくなる。When the metal block 3 is housed inside the through hole 8, the surfaces of the metal block 3 and the circuit board 1 are substantially flush with each other. The bottom surface of the metal block 3 is fixed to the surface of the heat dissipation plate 2 using a conductive adhesive 13. As a result, since solder is not used as in the conventional case, the flux does not adhere to the electrode pads 9 and the like when fixing the metal block 3.
【００２０】半導体チップ４は、導電性接着剤１３を用
いて、メタルブロック３の表面に固定される。半導体チ
ップ４の入出力端子（図示せず）と、ボンディングパッ
ド１７の表面は、ワイヤ−１４を用いて接続される。The semiconductor chip 4 is fixed to the surface of the metal block 3 with the conductive adhesive 13. An input / output terminal (not shown) of the semiconductor chip 4 and the surface of the bonding pad 17 are connected using a wire-14.
【００２１】次に、混成集積回路の製造の概略を説明す
る。Next, an outline of manufacturing the hybrid integrated circuit will be described.
【００２２】まず回路パタ−ン６の所定位置に、回路素
子１１が実装される。回路素子１１が実装された後、回
路基板１の裏面の金属層７は、放熱板２の表面に半田付
けされる。さらに、電極パッド９とボンディングパッド
１７、および放熱板２とメタルブロック３はそれぞれ導
電性接着剤１３を用いて固定される。なお、電極パッド
９とボンディングパッド１７、および放熱板２とメタル
ブロック３の間の重ね合わされる面積が充分に大きいた
め、表面に多少のフラックスが残留していたとしても両
者の間の接続強度は充分に確保することができる。この
ため、電極パッド９および貫通孔８によって露出した放
熱板２の表面部分に付着した、半田付けする際に使用し
たフラックスを取り除くための洗浄を行っても良いし、
付着したフラックスが少ない場合には、洗浄を省くこと
ができる。さらに、導電性接着剤１３を用いて固定さた
ボンディングパッド１７の表面は、半田フラックスが付
着することがなく、常に清浄に保たれる。このため、ワ
イヤ−１４とボンディングパッド１７の間は充分な接続
極度を確保することができる。First, the circuit element 11 is mounted at a predetermined position of the circuit pattern 6. After the circuit element 11 is mounted, the metal layer 7 on the back surface of the circuit board 1 is soldered to the front surface of the heat dissipation plate 2. Further, the electrode pad 9 and the bonding pad 17, and the heat dissipation plate 2 and the metal block 3 are fixed with a conductive adhesive 13, respectively. Since the overlapping area between the electrode pad 9 and the bonding pad 17, and between the heat dissipation plate 2 and the metal block 3 is sufficiently large, even if some flux remains on the surface, the connection strength between the two is high. You can secure enough. Therefore, cleaning may be performed to remove the flux used for soldering, which is attached to the surface portion of the heat dissipation plate 2 exposed by the electrode pad 9 and the through hole 8.
If the attached flux is small, cleaning can be omitted. Further, the surface of the bonding pad 17 fixed with the conductive adhesive 13 is always kept clean without the solder flux adhering thereto. Therefore, it is possible to secure a sufficient degree of connection between the wire 14 and the bonding pad 17.
【００２３】（実施例２）図２および図３を用いて、本
発明の第二の実施例を説明する。第一の実施例と同じ構
成部分は同じ番号を用い、説明は省略する。(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
【００２４】回路基板１の金属層７の貫通孔８の周縁部
には、一定幅に半田レジスト膜１８が設けられる。A solder resist film 18 having a constant width is provided on the peripheral portion of the through hole 8 of the metal layer 7 of the circuit board 1.
【００２５】半田レジスト膜１８を設けたことにより、
回路基板１の金属層７と放熱板２を半田付けする際に、
貫通孔８の周縁部には半田１２は付着せず、結果として
貫通孔８によって露出した放熱板２の表面部分には半田
１２がはみ出さない。このため、メタルブロック３を貫
通孔８に収容しても、メタルブロック３の底面ははみ出
した半田１２と重なることがないため、メタルブロック
３は傾かない。この結果、メタルブロック３の底面は放
熱板２と接する状態で確実に固定される。By providing the solder resist film 18,
When soldering the metal layer 7 of the circuit board 1 and the heat sink 2,
The solder 12 does not adhere to the peripheral portion of the through hole 8, and as a result, the solder 12 does not protrude to the surface portion of the heat dissipation plate 2 exposed by the through hole 8. Therefore, even if the metal block 3 is housed in the through hole 8, the bottom surface of the metal block 3 does not overlap the protruding solder 12, and therefore the metal block 3 does not tilt. As a result, the bottom surface of the metal block 3 is securely fixed in contact with the heat dissipation plate 2.
【００２６】なお、半田１２が付着しない領域を形成す
る方法として、半田レジスト膜１８の代わりに、貫通孔
８の周縁部の回路基板１の金属層７を一定幅エッチング
除去しても良い。この場合にも、貫通孔８の周縁部には
半田１２が付着しないので、貫通孔８によって露出した
放熱板２の表面部分に半田１２ははみ出さない。As a method of forming a region to which the solder 12 does not adhere, the metal layer 7 of the circuit board 1 at the peripheral portion of the through hole 8 may be removed by etching to a certain width, instead of the solder resist film 18. Also in this case, since the solder 12 does not adhere to the peripheral portion of the through hole 8, the solder 12 does not protrude to the surface portion of the heat dissipation plate 2 exposed by the through hole 8.
【００２７】[0027]
【発明の効果】本発明は、上述のような構成であるから
次のような効果を有する。すなわち、混成集積回路を製
造する際には回路基板と放熱板のみを半田付けで固定す
るので、従来の混成集積回路のように放熱板と回路基板
およびメタルブロックを半田付けする場合に比べて半田
付けする面積が減少し、電極パッド等に付着するフラッ
クス量が減少する。この結果、フラックスの洗浄を簡単
に済ませることができる。なお、付着したフラックスが
少ない場合には、洗浄を省くこともできる。また、半導
体チップの入出力端子と回路パタ−ンを接続するために
ボンディングパッドを設けるとともに、ボンディングパ
ッドは導電性接着剤を用いて固定されるので表面は常に
清浄に保たれる。このため、ワイヤ−とボンディングパ
ッドの接続強度を充分に確保することができる。この結
果、混成集積回路の製造工程が簡略化されるとともに、
混成集積回路の信頼性が向上し、さらに生産時の歩留ま
りが向上する。The present invention having the above-mentioned structure has the following effects. In other words, when manufacturing a hybrid integrated circuit, only the circuit board and heat sink are fixed by soldering, so compared to the conventional hybrid integrated circuit where the heat sink, circuit board and metal block are soldered The area to be attached is reduced, and the amount of flux attached to the electrode pad or the like is reduced. As a result, cleaning of the flux can be easily completed. If the attached flux is small, the cleaning can be omitted. Further, a bonding pad is provided for connecting the input / output terminal of the semiconductor chip and the circuit pattern, and the bonding pad is fixed using a conductive adhesive, so that the surface is always kept clean. Therefore, the connection strength between the wire and the bonding pad can be sufficiently secured. As a result, the manufacturing process of the hybrid integrated circuit is simplified and
The reliability of the hybrid integrated circuit is improved, and the production yield is improved.
【図１】本発明の第一の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明の第二の実施例に係り、図２（ａ）は回
路基板の裏面の一部であり、図２（ｂ）は図２（ａ）の
Ａ−Ａ´における回路基板の断面図である。FIG. 2 relates to a second embodiment of the present invention, FIG. 2 (a) is a part of the back surface of the circuit board, and FIG. 2 (b) is a circuit board taken along the line AA ′ of FIG. 2 (a). FIG.
【図３】本発明の第二の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the present invention.
【図４】従来の混成集積回路の分解斜視図である。FIG. 4 is an exploded perspective view of a conventional hybrid integrated circuit.
【図５】図４に示す従来の混成集積回路のＡ−Ａ´にお
ける断面図の一部である。5 is a part of a cross-sectional view taken along line AA ′ of the conventional hybrid integrated circuit shown in FIG.
１ 回路基板 ２ 放熱板 ３ メタルブロック ４ 半導体チップ ６ 回路パタ−ン ７ 金属層 ８ 貫通孔 ９ 電極パッド １０ 金メッキ層 １１ 回路素子 １２ 半田 １３ 導電性接着剤 １４ ワイヤ− １８ 半田レジスト膜 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Heat sink 3 Metal block 4 Semiconductor chip 6 Circuit pattern 7 Metal layer 8 Through hole 9 Electrode pad 10 Gold plating layer 11 Circuit element 12 Solder 13 Conductive adhesive 14 Wire-18 Solder resist film
Claims (3)
裏面には金属層が形成されるとともに貫通孔が設けられ
た回路基板と、該回路基板の裏面の金属層に半田付けさ
れた放熱板と、前記貫通孔に収容されて該放熱板に固定
されたメタルブロックと、該メタルブロックの表面に導
電接着剤で固定された半導体チップを備えた混成集積回
路において、前記回路パタ−ンに導電接着剤を用いて電
気的に接続されたボンディングパッドを有し、前記メタ
ルブロックは前記放熱板に導電接着剤で固定されるとと
もに、前記半導体チップの入出力端子は前記ボンディン
グパッドにワイヤ−接続されたことを特徴とする混成集
積回路。1. A circuit board on which a circuit pattern is formed on the front surface of the board and a metal layer is formed on the back surface and through holes are provided, and the circuit board is soldered to the metal layer on the back surface of the circuit board. In the hybrid integrated circuit including a heat dissipation plate, a metal block housed in the through hole and fixed to the heat dissipation plate, and a semiconductor chip fixed to the surface of the metal block with a conductive adhesive, the circuit pattern is provided. Has a bonding pad electrically connected thereto by using a conductive adhesive, the metal block is fixed to the heat dissipation plate by a conductive adhesive, and the input / output terminals of the semiconductor chip are connected to the bonding pad by a wire. A hybrid integrated circuit characterized by being connected.
田が付着しない領域を設けたことを特徴とする請求項１
記載の混成集積回路。2. A region to which solder does not adhere is provided in a peripheral portion of the through hole on the back surface of the circuit board.
A hybrid integrated circuit as described.
田レジスト膜を設けたことを特徴とする請求項１記載の
混成集積回路。3. The hybrid integrated circuit according to claim 1, wherein a solder resist film is provided on a peripheral portion of the through hole on the back surface of the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7161097A JPH0917918A (en) | 1995-06-27 | 1995-06-27 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7161097A JPH0917918A (en) | 1995-06-27 | 1995-06-27 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0917918A true JPH0917918A (en) | 1997-01-17 |
Family
ID=15728553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7161097A Pending JPH0917918A (en) | 1995-06-27 | 1995-06-27 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0917918A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399894B1 (en) | 1998-12-22 | 2002-06-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Wire bond compensation |
| JP2013123011A (en) * | 2011-12-12 | 2013-06-20 | Denso Corp | Electronic apparatus |
| JP2014505373A (en) * | 2011-11-09 | 2014-02-27 | 東莞勤上光電股▲ふん▼有限公司 | Manufacturing method of heat dissipation structure of high power LED |
-
1995
- 1995-06-27 JP JP7161097A patent/JPH0917918A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399894B1 (en) | 1998-12-22 | 2002-06-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Wire bond compensation |
| JP2014505373A (en) * | 2011-11-09 | 2014-02-27 | 東莞勤上光電股▲ふん▼有限公司 | Manufacturing method of heat dissipation structure of high power LED |
| JP2013123011A (en) * | 2011-12-12 | 2013-06-20 | Denso Corp | Electronic apparatus |
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