JP2806343B2 - Multi-chip module and its chip carrier - Google Patents

Multi-chip module and its chip carrier

Info

Publication number
JP2806343B2
JP2806343B2 JP1404796A JP1404796A JP2806343B2 JP 2806343 B2 JP2806343 B2 JP 2806343B2 JP 1404796 A JP1404796 A JP 1404796A JP 1404796 A JP1404796 A JP 1404796A JP 2806343 B2 JP2806343 B2 JP 2806343B2
Authority
JP
Japan
Prior art keywords
chip carrier
chip
circuit board
ground electrode
cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1404796A
Other languages
Japanese (ja)
Other versions
JPH09213876A (en
Inventor
安昭 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1404796A priority Critical patent/JP2806343B2/en
Publication of JPH09213876A publication Critical patent/JPH09213876A/en
Application granted granted Critical
Publication of JP2806343B2 publication Critical patent/JP2806343B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明はマルチチップモジ
ュールおよびそのチップキャリアに関し、特に回路基板
上にチップキャリア方式の回路を搭載したマルチチップ
モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multichip module and a chip carrier thereof, and more particularly, to a multichip module having a circuit of a chip carrier type mounted on a circuit board.

【0002】[0002]

【従来の技術】携帯電話機の小型化を伴ない、その内部
に使用される高周波(RF)信号増幅器としてのマルチ
チップモジュールにも小型・薄型化が要求されている。
従来のマルチチップモジュールの一例の構造を図5の分
解斜視図および図6の断面図により説明する。
2. Description of the Related Art With the miniaturization of portable telephones, a multi-chip module as a high frequency (RF) signal amplifier used therein is also required to be small and thin.
The structure of an example of a conventional multichip module will be described with reference to an exploded perspective view of FIG. 5 and a sectional view of FIG.

【0003】このマルチチップモジュールは平板又は両
端が、図5に示すように、曲げ加工の施こされた金属製
のヒートシンク3の上に、セラミック又は樹脂製の回路
基板2がハンダ等のソルダーにより固定されている。こ
の回路基板2の裏面にはヒートシンク3と電気的に接続
するために、銅等によりメタライズされている。この回
路基板2は半導体の搭載されたチップキャリア1を挿入
するため、穴(キャビティ)が穿けてあり、チップキャ
リア1の電極の1つとなっている底部の金属部分がヒー
トシンク3に回路基板2と共にハンダ等のソルダーにて
接続される。
In this multi-chip module, as shown in FIG. 5, a ceramic or resin circuit board 2 is placed on a metal heat sink 3 on which a flat plate or both ends are bent as shown in FIG. Fixed. The back surface of the circuit board 2 is metallized with copper or the like to be electrically connected to the heat sink 3. The circuit board 2 has a hole (cavity) formed therein for inserting the chip carrier 1 on which a semiconductor is mounted, and the bottom metal portion serving as one of the electrodes of the chip carrier 1 is attached to the heat sink 3 together with the circuit board 2. Connected with solder such as solder.

【0004】チップキャリア1の他のリード電極8はこ
の回路基板2への挿入時に回路基板2上に厚膜印刷又は
エッチングにて形成された回路パターン11と接続され
て回路を構成する。また、回路基板2上には回路パター
ン11とともに回路を構成するチップ状の抵抗,コンデ
ンサ,インダクタ等のチップ部品10が回路パターン1
1上に配置され、ハンダにて固定される。回路基板2上
の回路パターン11を酸化等から保護するために、誘電
体をコーティングするか、耐酸化性の良い金などのメッ
キ(例えば、Cu−Ni−Auの3層とし、その厚みは
各々18μm,3〜5μm,0.03μm程度)とす
る。
The other lead electrode 8 of the chip carrier 1 is connected to a circuit pattern 11 formed by printing or etching a thick film on the circuit board 2 when the chip carrier 1 is inserted into the circuit board 2 to form a circuit. On the circuit board 2, chip components 10 such as chip resistors, capacitors, inductors, etc., which constitute a circuit together with the circuit pattern 11, are formed.
1 and fixed with solder. In order to protect the circuit pattern 11 on the circuit board 2 from oxidation or the like, it is coated with a dielectric or plated with gold or the like having good oxidation resistance (for example, three layers of Cu-Ni-Au, each having a thickness of 18 μm, 3 to 5 μm, about 0.03 μm).

【0005】また、回路基板2には外部とのインターフ
ェース(電源供給及び入出力信号ライン)として、端部
にリード12が取り付けられている。このリード12は
回路基板2の端部に設けられた回路パターン10の位置
で回路基板2を挟み込むようなクリップ形状をしてお
り、その一部は回路基板2の端部より2mm程度引出さ
れ、外部のラインと接続される。
A lead 12 is attached to the end of the circuit board 2 as an interface with the outside (power supply and input / output signal lines). The lead 12 has a clip shape that sandwiches the circuit board 2 at the position of the circuit pattern 10 provided at the end of the circuit board 2, and a part of the lead 12 is pulled out from the end of the circuit board 2 by about 2 mm. Connected to an external line.

【0006】ヒートシンク3上に構成された回路部品
は、金属製のカバー4をヒートシンク3に取り付ける事
により保護され、またこのカバー4は内部のRF回路か
らの信号輻射等を防ぐ。
The circuit components formed on the heat sink 3 are protected by attaching a metal cover 4 to the heat sink 3, and the cover 4 prevents signal radiation from an internal RF circuit.

【0007】カバー4は、図6(c)に示すように、そ
れ自身の嵌合部14Aとヒートシンク3に設けられた嵌
合部14Bで咬み合わされ、金属の弾性を利用して機械
的に嵌合部を締付ている。この金属部の嵌合による接触
でカバー4とヒートシンク3の電気的な接続をとってい
る。
As shown in FIG. 6C, the cover 4 is engaged with its own fitting portion 14A and a fitting portion 14B provided on the heat sink 3, and is mechanically fitted by utilizing the elasticity of metal. The joint is tightened. The cover 4 and the heat sink 3 are electrically connected to each other by the contact due to the fitting of the metal portion.

【0008】マルチチップモジュールに搭載されている
チップキャリア1の構造は、図6(b)に示される。金
属製のベース6の上面外周部を中央部より低くし、この
部分にセラミック製または絶縁体製の厚さ0.6mm程
度の薄板13をのせる。この薄板13の裏面には、金属
製のベース6と接続するようにメタライズが施こされ、
両者はソルダーで接着される。薄板13の上面にはチッ
プキャリア1のリード電極8が取り付けられるが、裏面
と同様に薄板13の上面はメタライズされ、その部分で
リード電極8が接着される。またベース6の上面には半
導体、例えばGaAsFETがマウントされ、半導体上
面の電極とチップキャリア1のリード電極8がボンディ
ングワイヤにより接続される。チップキャリア1の内の
半導体及びボンディングワイヤを保護する為にチッピキ
ャリア1の上部より樹脂をポッティングしてある。
FIG. 6B shows the structure of the chip carrier 1 mounted on the multi-chip module. The outer peripheral portion of the upper surface of the metal base 6 is made lower than the central portion, and a thin plate 13 made of ceramic or insulator and having a thickness of about 0.6 mm is placed on this portion. The rear surface of the thin plate 13 is metallized so as to be connected to the metal base 6.
Both are bonded with solder. The lead electrode 8 of the chip carrier 1 is attached to the upper surface of the thin plate 13, but the upper surface of the thin plate 13 is metallized similarly to the back surface, and the lead electrode 8 is bonded at that portion. A semiconductor, for example, a GaAs FET is mounted on the upper surface of the base 6, and the electrode on the upper surface of the semiconductor and the lead electrode 8 of the chip carrier 1 are connected by a bonding wire. Resin is potted from above the chip carrier 1 to protect the semiconductor and the bonding wires in the chip carrier 1.

【0009】[0009]

【発明が解決しようとする課題】この従来のマルチチッ
プモジュールでは、カバー4の電位をヒートシンク3と
同電位にするため、カバー4の固定を行なう各嵌合部1
4A,14Bのかみ合いによる接触を電気的な接続とし
て利用しているが、その電気的接続が不完全となり、マ
ルチチップモジュールの電気的特性が不安定となるとい
う問題点があった。また、マルチチップモジュールの薄
型化のために、マルチチップモジュール内の回路部品1
0がカバー4のわずかな変形によりカバーと接触する危
険があった。
In this conventional multi-chip module, in order to make the potential of the cover 4 the same as that of the heat sink 3, each fitting portion 1 for fixing the cover 4 is used.
Although the contact due to the meshing of 4A and 14B is used as an electrical connection, the electrical connection is incomplete and there is a problem that the electrical characteristics of the multi-chip module become unstable. In order to reduce the thickness of the multi-chip module, the circuit components 1
0 was in danger of contacting the cover due to slight deformation of the cover 4.

【0010】本発明の目的は、これらの問題を解決し、
カバーとの接触を確実にし、カバーの変形による部品等
との接触を防止したマルチチップモジュールを提供する
ことにある。
An object of the present invention is to solve these problems,
An object of the present invention is to provide a multi-chip module that ensures contact with a cover and prevents contact with components and the like due to deformation of the cover.

【0011】[0011]

【課題を解決するための手段】本発明の構成は、高周波
素子を搭載したチップキャリアと高周波部品とを実装し
これらを接続する配線を形成した回路基板と、この回路
基板を搭載する金属製放熱板と、この金属製放熱板と嵌
合する嵌合部を有し前記回路基板を覆う導電部材からな
るキャップ状のカバーとを備えたマルチチップモジュー
ルにおいて、前記高周波素子を搭載したチップキャリア
は、その搭載面上がその前方に延在した接地電極からな
り、この接地電極が前記カバーと接触して接続されるよ
うにしたことを特徴とする。
According to the present invention, there is provided a circuit board on which a chip carrier on which a high-frequency element is mounted and a high-frequency component are mounted and wiring for connecting the components is formed, and a metal radiator on which the circuit board is mounted is provided. In a multi-chip module including a plate and a cap-shaped cover made of a conductive member that has a fitting portion fitted with the metal heat sink and covers the circuit board, the chip carrier on which the high-frequency element is mounted is: The mounting surface is formed of a ground electrode extending forward, and the ground electrode is configured to be in contact with and connected to the cover.

【0012】また本発明のチップキャリアの構成は、高
周波素子を搭載し接地電極を構成する金属ベースと、こ
の金属ベースの前記高周波素子の搭載部を囲む絶縁基板
と、この絶縁基板上で前記高周波素子から外部に引き出
されたリードとを有するチップキャリアにおいて、前記
金属ベースは、前記リード部分を除く前記絶縁基板の外
周にわたり前記高周波素子の搭載面上に延在された接地
電極を有することを特徴とする。
The chip carrier of the present invention comprises a metal base on which a high-frequency element is mounted and forms a ground electrode; an insulating substrate surrounding the mounting portion of the high-frequency element on the metal base; In a chip carrier having a lead drawn out of a device, the metal base has a ground electrode extending on a mounting surface of the high-frequency device over an outer periphery of the insulating substrate excluding the lead portion. And

【0013】[0013]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。図1は本発明の一実施の形態のマルチチッ
プモジュールの分解斜視図である。このマルチチップモ
ジュールは、ヒートシンク(放熱板)3の上に誘電体製
の回路基板2がのせられ、回路基板2は裏面に金属膜が
付けられており、ハンダにてヒートシンク3と回路基板
2が嵌合されている。この回路基板2は、チップキャリ
ア1を実装する貫通孔5が穿けられており、この貫通孔
5にチップキャリア1が挿入され、接地電極である底部
のペース6の下面がヒートシンク3とハンダにて接続さ
れる。また回路基板2の上面は回路パターン11が形成
されており、回路を構成するチップ部品(抵抗,コンデ
ンサ等)10が搭載されハンダで固定される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is an exploded perspective view of a multichip module according to an embodiment of the present invention. In this multi-chip module, a circuit board 2 made of a dielectric material is placed on a heat sink (radiator plate) 3, and a metal film is attached to the back surface of the circuit board 2. The heat sink 3 and the circuit board 2 are soldered. Mated. The circuit board 2 is provided with a through hole 5 for mounting the chip carrier 1. The chip carrier 1 is inserted into the through hole 5, and the lower surface of the bottom pace 6, which is a ground electrode, is connected to the heat sink 3 and solder. Connected. A circuit pattern 11 is formed on the upper surface of the circuit board 2, and chip components (resistors, capacitors, etc.) 10 constituting the circuit are mounted and fixed with solder.

【0014】これら各部品10を実装した後、カバー4
で覆われ、図6(c)と同様にヒートシンク3の前後部
にある嵌合部14A,14Bにはまる事でカバー4の固
定及び電気的接続を行なう。また、図2(b)に示すよ
うにチップキャリア1の上部はカバー4を取付けた時
に、カバー4の上部内面と接触する高さとなっており、
図2(a)に示すように、チップキャリア1の上部はそ
の下部の接地電極となるベース6と電気的に接続されて
いるので、組み立てられたときにカバー4の押圧で接地
電極15とカバー4とが接触し電気的接続がとられる。
この時、チップキャリア1はカバー4を支える構造とな
っている。
After mounting these parts 10, the cover 4
6C, the cover 4 is fixed and electrically connected by fitting into the fitting portions 14A and 14B at the front and rear portions of the heat sink 3 as in FIG. Further, as shown in FIG. 2B, the upper portion of the chip carrier 1 has a height that comes into contact with the inner surface of the upper portion of the cover 4 when the cover 4 is attached.
As shown in FIG. 2A, the upper portion of the chip carrier 1 is electrically connected to the base 6 serving as the ground electrode at the lower portion thereof. 4 and the electrical connection is established.
At this time, the chip carrier 1 has a structure for supporting the cover 4.

【0015】図3は本発明の他の実施形態を示す分解斜
視図である。この実施形態において、チップキャリア1
の形状を、図2(a)のようにチップキャリア1のベー
ス6と電気的に接続されている接地電極15が、マルチ
チップモジュール内の空間を回路上で複数に分割する構
造を持ち、チップキャリア1の接地電極15が図1と同
様にカバー4と電気的・構造的に接続される。また、本
実施形態においては、カバー4の上部への接続だけでな
く、背面及び前面でのカバー4への接続が同時に行なわ
れる。
FIG. 3 is an exploded perspective view showing another embodiment of the present invention. In this embodiment, the chip carrier 1
2A, the ground electrode 15 electrically connected to the base 6 of the chip carrier 1 has a structure in which the space in the multi-chip module is divided into a plurality of parts on a circuit. The ground electrode 15 of the carrier 1 is electrically and structurally connected to the cover 4 as in FIG. In the present embodiment, not only the connection to the upper portion of the cover 4 but also the connection to the cover 4 on the rear surface and the front surface are performed at the same time.

【0016】次に、本発明に用いられるチップキャリア
1について図2(a),図4により説明する。マルチチ
ップモジュールを組立たときに、ヒートシンク3の上面
とカバー4の上部内面との高さと一致するように設計さ
れた接地電極15となる金属ベース6は図2に示すよう
な断面構造となっている。また、その内側には、図4に
示すように半導体素子を取囲むように誘電体の薄板13
がロウ付等により付けられる。この薄板13上には、引
出し用のリード電極8が取付けられている。接地電極1
5はリード電極8を引出す位置については高さ方向に削
られており、リード電極8は接地電極15の隙間から引
出される。
Next, the chip carrier 1 used in the present invention will be described with reference to FIGS. When the multi-chip module is assembled, the metal base 6 serving as the ground electrode 15 designed to match the height between the upper surface of the heat sink 3 and the upper inner surface of the cover 4 has a sectional structure as shown in FIG. I have. On the inside, as shown in FIG. 4, a thin dielectric plate 13 surrounds the semiconductor element.
Is attached by brazing or the like. On this thin plate 13, a lead electrode 8 for extraction is attached. Ground electrode 1
5 is cut in the height direction at the position where the lead electrode 8 is pulled out, and the lead electrode 8 is drawn out from the gap between the ground electrode 15.

【0017】接地電極15の形状としては、リード電極
8が引き出される辺について、又は全外周に沿ってのい
ずれかの形がとられるが、高さについては、前述のよう
にマルチチップモジュールの組立時に接地電極15の上
面がカバー4の上部内側に接触する高さに設定される。
The shape of the ground electrode 15 can be either the side from which the lead electrode 8 is drawn out or along the entire outer periphery, but the height is as described above. Sometimes, the height is set to a level at which the upper surface of the ground electrode 15 contacts the upper inside of the cover 4.

【0018】[0018]

【発明の効果】以上説明したように本発明は、マルチチ
ップモジュール内部のチップキャリアにおいて、チップ
キャリアの接地電極がカバー及びヒートシンクと同時に
電気的に接続されることによりカバーの電位が安定した
接地電位となり、マルチチップモジュールの性能が安定
化される。また、その構造上カバーがチップキャリアに
より支えられている形となるので、カバーの変形が防止
されると共に、カバーが変形することによる内部回路の
短絡を防止できるという効果を有する。さらに、チップ
キャリアの上部接地電極を更に大型化と、マルチチップ
モジュール内の空間を複数に分割することにより、マル
チチップモジュール内の回路のアイソレーションが向上
され回路の安定性の向上が図られるという効果もある。
As described above, according to the present invention, in the chip carrier in the multi-chip module, the ground potential of the chip carrier is electrically connected simultaneously with the cover and the heat sink so that the potential of the cover is stabilized. And the performance of the multichip module is stabilized. Further, since the cover is structurally supported by the chip carrier, the cover is prevented from being deformed, and the short circuit of the internal circuit due to the deformation of the cover can be prevented. Furthermore, by further increasing the size of the upper ground electrode of the chip carrier and dividing the space in the multi-chip module into a plurality of parts, the isolation of the circuit in the multi-chip module is improved, and the stability of the circuit is improved. There is also an effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の構成を示す分解斜視図で
ある。
FIG. 1 is an exploded perspective view showing a configuration of an embodiment of the present invention.

【図2】図1のチップキャリアおよびマルチチップモジ
ュールの断面図である。
FIG. 2 is a cross-sectional view of the chip carrier and the multi-chip module of FIG.

【図3】本発明の他の実施形態の分解斜視図である。FIG. 3 is an exploded perspective view of another embodiment of the present invention.

【図4】図3のチップキャリアの上面図である。FIG. 4 is a top view of the chip carrier of FIG. 3;

【図5】従来のマルチチップモジュールの構成を示す分
解斜視図である。
FIG. 5 is an exploded perspective view showing a configuration of a conventional multichip module.

【図6】図5のマルチチップモジュール部分、チップキ
ャリアおよびケース部分の各断面図である。
6 is a cross-sectional view of a multi-chip module portion, a chip carrier, and a case portion of FIG.

【符号の説明】[Explanation of symbols]

1 チップキャリア 2 回路基板 3 ヒートシンク 4 カバー 5 (基板)貫通孔 6 ベース 7 ハンダメッキ 8 リード電極 9 樹脂 10 チップ部品 11 回路パターン 12 リード 13 絶縁板製薄板 14A,14B 嵌合部 15 接地電極 REFERENCE SIGNS LIST 1 chip carrier 2 circuit board 3 heat sink 4 cover 5 (substrate) through hole 6 base 7 solder plating 8 lead electrode 9 resin 10 chip component 11 circuit pattern 12 lead 13 insulating plate thin plate 14A, 14B fitting portion 15 ground electrode

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 高周波素子を搭載したチップキャリアと
高周波部品とを実装しこれらを接続する配線を形成した
回路基板と、この回路基板を搭載する金属製放熱板と、
この金属製放熱板と嵌合する嵌合部を有し前記回路基板
を覆う導電部材からなるキャップ状のカバーとを備えた
マルチチップモジュールにおいて、前記高周波素子を搭
載したチップキャリアは、その搭載面上がその前方に延
在した接地電極からなり、この接地電極が前記カバーと
接触して接続されるようにしたことを特徴とするマルチ
チップモジュール。
A circuit board on which a chip carrier on which a high-frequency element is mounted and a high-frequency component are mounted and wiring for connecting the chip carrier is formed; a metal heat sink on which the circuit board is mounted;
In the multi-chip module including the metal heat dissipation plate and a cap-shaped cover made of a conductive member that covers the circuit board and has a fitting portion, the chip carrier on which the high-frequency element is mounted has a mounting surface A multi-chip module, comprising a ground electrode extending forward thereof, the ground electrode being in contact with and connected to the cover.
【請求項2】 チップキャリアは、回路基板に穿設され
た貫通孔内で、金属製放熱板上に接して配設されたもの
である請求項1記載のマルチチップモジュール。
2. The multi-chip module according to claim 1, wherein the chip carrier is disposed in contact with a metal heat sink in a through hole formed in the circuit board.
【請求項3】 チップキャリアの接地電極により、この
チップキャリアを実装した回路基板とキャップ状カバー
との間が分離されるようにした請求項1または2記載の
マルチチップモジュール。
3. The multi-chip module according to claim 1, wherein a ground electrode of the chip carrier separates a circuit board on which the chip carrier is mounted from the cap-shaped cover.
【請求項4】 高周波素子を搭載し接地電極を構成する
金属ベースと、この金属ベースの前記高周波素子の搭載
部を囲む絶縁基板と、この絶縁基板上で前記高周波素子
から外部に引き出されたリードとを有するチップキャリ
アにおいて、前記金属ベースは、前記リード部分を除く
前記絶縁基板の外周にわたり前記高周波素子の搭載面上
に延在された接地電極を有することを特徴とするチップ
キャリア。
4. A metal base on which a high-frequency element is mounted to form a ground electrode, an insulating substrate surrounding the mounting portion of the high-frequency element of the metal base, and a lead drawn out of the high-frequency element on the insulating substrate. Wherein the metal base has a ground electrode extending on the mounting surface of the high-frequency element over the outer periphery of the insulating substrate excluding the lead portion.
JP1404796A 1996-01-30 1996-01-30 Multi-chip module and its chip carrier Expired - Fee Related JP2806343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1404796A JP2806343B2 (en) 1996-01-30 1996-01-30 Multi-chip module and its chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1404796A JP2806343B2 (en) 1996-01-30 1996-01-30 Multi-chip module and its chip carrier

Publications (2)

Publication Number Publication Date
JPH09213876A JPH09213876A (en) 1997-08-15
JP2806343B2 true JP2806343B2 (en) 1998-09-30

Family

ID=11850193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1404796A Expired - Fee Related JP2806343B2 (en) 1996-01-30 1996-01-30 Multi-chip module and its chip carrier

Country Status (1)

Country Link
JP (1) JP2806343B2 (en)

Also Published As

Publication number Publication date
JPH09213876A (en) 1997-08-15

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