JPH09116249A - Semiconductor device and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent short circuit between adjacent bumps which is to be caused by the spreading of conducting paste, and increase the density of a semiconductor device and a display device, by forming protruding electrodes having recessed parts on the upper surfaces, on connecting pads, and mounting a semiconductor element on a wiring board via the protruding electrodes. SOLUTION: In a semiconductor element 1, many bumps 2 are formed on the surface. On a wiring pattern 4 formed on an insulating board 3, recessed parts 5 are formed on the surface connecting with the bumps 2 and a board 3 and connected via conducting paste 6 with which the recessed parts 5 are filled. As the more preferable mode of the recessed parts 5, they are formed as trenches having apertures of one position on the edges of side surfaces 21 which do not face adjacent bumps. When protruding electrodes having trench- shaped recessed parts having apertures of one position are formed, the electrodes are so arranged that they alternately face the inside and the outside of a semiconductor device, and the conducting paste can be effectively prevented from flowing out to the space between adjacent bumps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a display device in which a semiconductor element is mounted on a substrate with a connecting surface facing downward via a bump.

[0002]

2. Description of the Related Art In recent years, as a method of mounting a semiconductor device and a display device in a thinner and higher density, a semiconductor element is fixedly mounted on a wiring board, and a so-called wire is used for electrical connection. Instead of bonding mounting, face-down mounting technology has been developed in which bump electrodes are formed on a semiconductor element and directly connected to a substrate for mounting. Face-down mounting is flip-chip technology using solder bumps applied to supercomputers and COG (Ch
A variety of connection materials, mounting methods, etc. have been proposed depending on the application, such as ip on glass).

As one of the COG techniques, as shown in FIG. 12, bumps made of gold or copper are formed on a semiconductor element, and a conductive paste containing silver as a main component is further formed on the bumps to form a semiconductor element. A technique has been proposed in which the wiring is mounted on the substrate and the conductive paste is cured to make a connection. However, in this method, when the semiconductor element is mounted on the substrate, the conductive paste spreads and a short circuit occurs between the adjacent bumps, so that it is necessary to widen the pitch between the bumps, which hinders high-density mounting. Was there.

Therefore, as a method of making the connection pitch finer, a method of preventing the spread of the conductive paste by forming bumps in a convex shape and transferring the conductive paste to the bumps as shown in FIG. 13 has been proposed. ing. However, although this method allows finer pitch connection than the method shown in FIG. 12, the conductive paste still spreads and a short circuit may occur between adjacent bumps.

[0005]

The present invention has been made in consideration of the above problems, and a semiconductor device and a display device using a so-called conductive paste COG mounting technique for connecting bumps and wirings through a conductive paste. In order to prevent a short circuit between adjacent bumps due to spreading of the conductive paste, it is an object of the present invention to provide a semiconductor device and a display device with higher density.

[0006]

According to the present invention, firstly, a wiring board and a protruding electrode having a concave portion on the upper surface are formed on a connection pad and mounted on the wiring board via the protruding electrode. Provided is a semiconductor device including a semiconductor element.

Secondly, according to the present invention, a wiring board and a protruding electrode having a groove having at least one opening at an edge thereof are formed on a connection pad, and the protruding electrode is mounted on the wiring board via the protruding electrode. In the semiconductor device including the semiconductor element, the plurality of projecting electrodes are arranged such that the openings face the inside or the outside of the semiconductor device.

Thirdly, the present invention provides a wiring board and a semiconductor element having a plurality of protruding electrodes provided with grooves having openings at the edges thereof and mounted on the wiring board via the protruding electrodes. In the provided semiconductor device, the plurality of protruding electrodes may be
A semiconductor device is provided, wherein the openings are arranged so as to alternately face the inside or the outside of the semiconductor device.

A fourth aspect of the present invention is a semiconductor element in which a substrate on which a display element is provided and a protruding electrode having a concave portion on the upper surface are formed on a connection pad, and which is mounted on the substrate via the protruding electrode. There is provided a display device comprising:

Fifthly, according to the present invention, a substrate provided with a display element and a protruding electrode having a groove having at least one opening at an edge thereof are formed on a connection pad, and the substrate is provided through the protruding electrode. There is provided a display device including a semiconductor element mounted on the display device.

In a sixth aspect of the present invention, a substrate provided with a display element and a plurality of projecting electrodes having a groove having an opening at an edge thereof are formed, and the substrate is mounted on the substrate via the projecting electrodes. In a semiconductor device including a semiconductor element, the plurality of projecting electrodes are arranged such that the openings are alternately arranged inside or outside the semiconductor device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described in detail with reference to FIG. As shown in FIG. 1, the semiconductor element 1 has a large number of bumps 2 formed on its surface. On the wiring pattern 4 formed on the insulating substrate 3,
A recess 5 is formed on the surface connecting to the bump 2 and the substrate 3 and is connected via a conductive paste 6 filled in the recess 5.

As the insulating substrate 3 having the wiring pattern 4, in addition to a glass substrate / resin substrate, a circuit board having a wiring pattern formed on one or both sides of a substrate made of ceramic such as alumina / aluminum nitride is used. I can give you. The material of the bump 2 is not particularly limited as long as it is a conductive substance,
For example, Cu, Ni, Au, etc. may be mentioned.

The method of forming the bumps 2 includes, for example, screen printing / plating, sputtering and the like. As a method of forming the concave portion 5, for example, (1) a method of plating on a substrate in which the concave portion is formed in advance, (2) a method of performing the plating in two steps and using different resist masks, (3)
By repeating the screen printing a plurality of times using two kinds of screen masks and (4) adjusting the resist mask and plating conditions such as flow rate and additive concentration,
There is a method of reducing the plating deposition rate at the center of the bump.

An embodiment of the shape of the recess is shown in FIGS. As shown in the figure, the concave portion 5 may have a pond shape as shown in FIG. 2, but a more preferable embodiment is that shown in FIG.
As shown in FIG. 4, the concave portion 5 is formed in a groove shape having an opening at one edge on the side surface 21 that does not face the adjacent bumps, or one at each edge on the opposite side surface 21 as shown in FIG. When the conductive paste 6 filled in the concave portion 5 of the bump 2 flows out to the periphery of the bump 2 at the time of connection by forming the groove in the shape of a groove having the opening and arranging the openings so as to face the inside or outside of the semiconductor device. However, it is possible to prevent the concave portion 5 from becoming an escape path for the conductive paste 6 and not flowing out toward the adjacent bump. Also, in particular, FIG.
In the case of providing a protruding electrode having a groove-shaped concave portion having an opening at one place as shown in, the conductive paste between adjacent bumps can be formed by arranging them so as to alternately face the inside or the outside of the semiconductor device. Outflow can be effectively prevented.

Further, the shape of the recess 5 of the bump 2 may be a cross shape as shown in FIG. 5, or, as shown in FIG. 6, for example, the shape of the bump 2 of FIG. A rectangular parallelepiped bump of a book may be formed, and the groove may be constituted by the side walls of the two bumps facing each other and the upper surface of the connection pad, and it does not matter if the bump material does not exist on the bottom surface of the recess.

ITO is used as the material of the wiring pattern 4.
-A conductor such as molybdenum, gold or nickel can be used, and the forming method includes sputtering, screen printing, vapor deposition, plating and the like.

Next, one embodiment of the display device according to the present invention will be described in detail with reference to FIG. The semiconductor element 1 is
A large number of bumps 2 are formed on the surface thereof, and a wiring pattern 4 formed around the display portion 7 on the substrate 3 of the display device.
The upper part is connected via the bump 2. Bump 2
Has a recess 5 formed on the surface connected to the substrate 3,
The recess 5 is filled with a conductive paste 6.

The method of forming the bump, the preferable shape, and the material of the wiring pattern are the same as those of the semiconductor device described above. According to the present invention, for example, a pond-shaped or groove-shaped concave portion is provided on the connection surface between the bump and the wiring pattern, and the concave portion is filled with the conductive paste when the semiconductor element is connected. Also, it becomes difficult for the conductive paste to flow out,
A short circuit between adjacent bumps can be prevented.

Hereinafter, a specific method of forming the semiconductor device according to the first embodiment of the present invention will be described in detail with reference to FIG. The semiconductor device according to the present invention is shown in FIG.
As shown in FIG. 3, the semiconductor element 1 is connected to the gold / nickel / titanium / tungsten wiring pattern 4 formed on the alumina substrate 3 via the Au bumps 2 and the conductive paste 6. The Au bump 2 has a groove 5 formed on the surface connected to the wiring pattern 4,
The groove 5 is filled with a conductive paste 6. The groove 5 is formed in a direction parallel to the side surface facing the adjacent Au bump, that is, so as to penetrate the side surface 21 not facing the adjacent bump. By arranging the grooves in such a direction, even if the conductive pastes of the adjacent bumps flow out, it is possible to prevent the conductive pastes from contacting each other and causing a short circuit.

Here, a manufacturing process of the semiconductor device shown in FIG. 1 will be described. Aluminum electrodes are formed on the semiconductor element 1. A barrier metal is deposited on this aluminum electrode. As the barrier metal, for example, use a laminated structure of titanium, chromium, which is an adhesion layer with aluminum, nickel, titanium-tungsten, which is a diffusion prevention layer, and gold, palladium, copper, etc. for forming bumps by plating. You can Here, a barrier metal having a laminated structure of palladium / nickel / titanium / (aluminum electrode) was formed by sputtering.

Next, a plating resist is applied by spin coating to a thickness of 10 μm, exposed and developed, and a barrier metal is used as a plating electrode on the aluminum electrode.
Gold bumps of 00 μm □ were formed with a pitch of 120 μm and a pitch of 10 μm. Further, a plating resist is applied to a thickness of 10 μm, and the width of the gold bump formed by exposure and development is 100
2 x 30 x 100 μm patterning at μm
This was performed, and gold bumps having a height of 10 μm were formed here.
The obtained gold bump had a shape shown in FIG. 4, and the height of the gold bump was 20 μm, the groove portion was 40 × 100 μm, and the peak portion was 30 × 100 μm. Remove the plating resist, etch the barrier metal using the gold bumps as a mask,
Finished the gold bump process.

Further, a conductive paste was printed on the obtained gold bumps as follows. As the conductive paste, for example, one containing silver as a main component such as silver, silver-palladium, or silver-platinum can be used. Here, the silver-palladium paste was used to print on one surface of an arbitrary substrate. A transfer substrate formed so as to correspond to the array of bumps was stamped thereon, and the silver-palladium paste was transferred to the transfer substrate. Transfer substrate height is 20μm, 30x
The protrusions of 50 μm are formed at a pitch of 120 μm,
By the transfer, the silver-palladium paste was transferred to the protruding portion of 30 × 50 μm.

After that, the semiconductor element on which the gold bump having the groove was formed and the transfer substrate were aligned, and the silver-palladium paste was transferred to the groove portion. Next, the semiconductor element to which the silver-palladium paste is transferred and the wiring board are aligned, the semiconductor element is mounted on the board, and the silver-
Palladium was cured at 150 ° C. for 30 minutes to connect the semiconductor element and the substrate.

The silver-palladium paste spread a little along the grooves of the concave bumps during mounting, but the peaks of the concave bumps formed walls and did not spread in the lateral direction. Therefore, the silver-palladium paste flowing out from one bump did not come into contact with the adjacent bump or the silver-palladium paste flowing out from the bump.

When the connection of the semiconductor element 1 is inspected and the semiconductor element 1 needs to be replaced, it can be peeled from the alumina substrate 3 by applying a shearing force to the semiconductor element 1 with a simple jig. After confirming normal operation by inspection, resin can be filled in the gap between the semiconductor element and the substrate and cured. In the present embodiment, the gold bumps are formed in two steps to form the bumps having grooves. However, as shown in FIG. 6, the bumps are formed in only one step and the aluminum electrode and the barrier metal are formed. You may form the bump which has a recessed part directly on it.

Further, as shown in FIG. 7, a glass substrate for a display device may be used instead of the alumina substrate. In the case of a display device, as shown in FIG. 7, the semiconductor element 3 has a structure in which the semiconductor element 3 is connected via the Au bump 2 on the wiring pattern 4 formed around the display portion 7 on the glass substrate 3. There is. The Au bump 2 has a groove 5 formed on the surface connected to the wiring pattern 4, and the groove 5 is filled with an Ag paste 6. The groove 5 is formed so as to penetrate in a direction parallel to the side surface facing the adjacent Au bump, that is, the side surface 21 not facing the adjacent bump. The formation of the Au bump 2 and the Ag paste is performed in the same process as the above. ITO was used for the wiring of the glass substrate.

Next, a second embodiment of the semiconductor device according to the present invention will be described. In the second embodiment of the semiconductor device of the present invention, bumps formed on a semiconductor element are formed on the semiconductor element. A groove having a width of 30 μm and a depth of 1 μm is formed in the center of the bonding pad existing by the PEP process and the Al etching process, and a barrier metal layer is sputtered thereon by 1 μm.
A semiconductor device was assembled in the same manner as in Example 1 except that Au was formed to a thickness of 20 μm by plating, and a groove having a width of 30 μm and a depth of 1 μm was formed in the center. The obtained Au bump has the same shape as that of FIG. 4 although its dimensions are different from those of the first embodiment.

The temporary connection of the obtained semiconductor device before the inspection is
Fill the groove with Ag paste, and in the air at 100 ℃, 1
The Ag paste was temporarily cured by a heat treatment for 0 minutes. Since the semiconductor element was replaced by the inspection of the semiconductor element, when the semiconductor element 1 was peeled from the alumina substrate with a simple jig, the Ag paste remained on the wiring pattern of the alumina substrate, but no damage was observed. There wasn't.

After another semiconductor element was temporarily connected in the same manner, a good semiconductor element was confirmed by inspection. Therefore, as the main connection, the semiconductor element side was heated to 380 ° C. and the alumina substrate was heated to 60 ° C. While applying a load of 50 g around the bumps, pressure welding was performed for 5 seconds, and all the Au bumps were simultaneously bonded to the wiring pattern by solid phase diffusion bonding. At this time, the Ag paste filled in the grooves of the bumps flowed out to the periphery of the bumps due to the high temperature and high pressure condition of the main connection, but flowed out in the direction in which the grooves were formed and spread between the adjacent bumps. Since it was not, a short circuit with an adjacent bump did not occur. In this joining, there was no electrical connection failure.

The third semiconductor device according to the present invention will be described below.
An embodiment will be described. In the third embodiment of the semiconductor device of the present invention, bumps formed on the semiconductor element are
On the bonding pad formed on the semiconductor element, Au screen printing was repeated twice with a thickness of 10 μm, the first mask was masked into a square pattern of 80 μm square, and the second mask was covered with a center width of 40 μm of 80 μm.
Similar to Example 1, except that a square pattern of m-square was formed, it had a pond-shaped concave portion having a width of 40 μm and a depth of 10 μm.
Bumps of 0 μm square and 20 μm high were formed.

For the temporary connection before the semiconductor device inspection, Ag is placed in the groove.
The paste was filled and heat-treated at 100 ° C. for 10 minutes in the air to thermally cure the Ag paste. Since the semiconductor element was replaced by the inspection of the semiconductor element, when the semiconductor element 1 was peeled from the alumina substrate with a simple jig, a small amount of Ag paste remained on the wiring pattern on the alumina substrate, No damage was observed.

Since another semiconductor element was temporarily connected in the same manner and a good semiconductor element was confirmed by inspection, the semiconductor element side was heated to 380.degree. C. and the alumina substrate was heated to 60.degree. The main bonding was performed by press-contacting for 5 seconds while applying a load of 50 g per bump, and solid-phase diffusion bonding all the Au bumps to the wiring pattern at once. At this time, A filled in the groove of the bump
Under the high temperature and high pressure condition of this connection, the g paste hardly flowed out to the periphery of the bump, and the adjacent bump was not short-circuited. In this main bonding, no electrical connection failure occurred.

Further, the fourth semiconductor device of the present invention is described below.
An embodiment will be described. In the semiconductor element used in this semiconductor device, the resist mask was formed so as to overhang at the edge of the opening prior to forming the bump by plating. FIG. 8 is a schematic diagram showing the shape of a resist mask used in the fourth embodiment of the semiconductor device of the present invention.
Shown in As shown in FIG. 8, the resist mask 8 formed on the semiconductor element 1 overhangs at the end of the opening. By forming the resist mask 8 in such a shape, the plating flow velocity of the semiconductor element 1 in the plating solution can be maximized in the central portion of the bump 2.

FIG. 9 is a graph showing the flow velocity distribution of the plating solution in the bump pattern. This flow velocity distribution shows a flow velocity distribution when x is the direction along the cross section of the end portion of the resist mask shown in FIG. As shown in FIG. 9, the flow velocity is
It becomes maximum at the center of the opening.

FIG. 10 is a graph showing the relationship between the plating solution flow rate and the plating deposition rate. Solid line a in FIG.
As shown in FIG. 10, when the additive is not included, the plating deposition rate monotonically increases with respect to the plating solution flow rate. However, by sufficiently adding the additive, as shown by the solid line b in FIG. The plating deposition rate can be controlled to decrease monotonically with respect to the plating solution flow rate. FIG. 11 shows a schematic cross-sectional view of bumps used in the fourth embodiment of the semiconductor device of the present invention. A with sufficient addition of additives
By performing u-plating, as shown in FIG. 11, a bump with a height of 20 μm and a square of 80 μm having a sectional shape in which the central portion is recessed by 10 μm from the end portion was obtained.

The temporary connection before the semiconductor inspection was performed by filling the groove with Ag paste and temporarily curing the Ag paste by heat treatment at 100 ° C. for 10 minutes in the air. Since the semiconductor element was replaced by the inspection of the semiconductor element, when the semiconductor element 1 was peeled from the alumina substrate with a simple jig, a small amount of Ag was found on the wiring pattern on the alumina substrate.
Although the paste remained, no damage was found.

After another semiconductor element was temporarily connected in the same manner, a good semiconductor element was confirmed by inspection. Therefore, as the main connection, the semiconductor element side was heated to 380 ° C. and the alumina substrate was heated to 60 ° C. The main bonding was performed by applying a pressure of 50 g per bump and pressing for 5 seconds to solid-phase diffusion bond all the Au bumps to the wiring pattern at once.

At this time, the Ag paste filled in the groove of the bump was melted under the high-temperature and high-pressure conditions of the main connection, but it hardly flowed out to the periphery of the bump. Therefore, a short circuit between adjacent bumps did not occur. In this main joining, there was no electrical connection failure. Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0040]

As described in detail above, according to the present invention, since the concave portion is formed on the bump electrode, it is possible to prevent the conductive paste from spreading between the adjacent bumps. Therefore, according to the present invention, it is possible to obtain a semiconductor device and a display device which have a high density and are easily repaired.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to the present invention.

FIG. 2 is a diagram for explaining an example of bump shapes on a semiconductor element according to the present invention.

FIG. 3 is a diagram for explaining an example of a bump shape on a semiconductor element according to the present invention.

FIG. 4 is a diagram for explaining an example of bump shapes on a semiconductor element according to the present invention.

FIG. 5 is a diagram for explaining an example of bump shapes on a semiconductor element according to the present invention.

FIG. 6 is a diagram for explaining an example of a bump shape on a semiconductor element according to the present invention.

FIG. 7 is a schematic diagram showing an embodiment of a display device according to the present invention.

FIG. 8 is a schematic diagram showing the shape of a resist mask used in a fourth embodiment of the semiconductor device of the present invention.

FIG. 9 is a graph showing a plating solution flow velocity distribution of bumps used in the fourth embodiment of the semiconductor device of the present invention.

FIG. 10 is a graph showing the relationship between the plating solution flow rate and the plating deposition rate.

FIG. 11 is a schematic sectional view of a bump used in a fourth embodiment of the semiconductor device of the present invention.

FIG. 12 is a schematic view showing a connection portion of a conventional semiconductor device.

FIG. 13 is a schematic view showing a connection portion of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 2 ... Bump 3 ... Substrate 4 ... Wiring pattern 5 ... Recessed portion 6 ... Conductive paste 7 ... Display portion 8 ... Resist mask 21 ... Side surface of bump not facing adjacent bump

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seisaburo Shimizu 33 Shinisogo-cho, Isogo-ku, Yokohama, Kanagawa Pref., Institute of Industrial Science, Toshiba Corporation (72) Masayuki Saito Shinisogo-cho, Isogo-ku, Yokohama, Kanagawa No. 33 Incorporated company Toshiba Production Engineering Laboratory

Claims (6)

[Claims] 1. A semiconductor device comprising: a wiring board; and a semiconductor element having a projection electrode having a concave portion on the upper surface formed on a connection pad and mounted on the wiring board via the projection electrode. apparatus. 2. A wiring board, and a semiconductor element formed on a connection pad with a protruding electrode having a groove having at least one opening at an edge thereof and mounted on the wiring board via the protruding electrode. The semiconductor device according to claim 1, wherein the plurality of protruding electrodes are arranged such that the openings face the inside or the outside of the semiconductor device. 3. A semiconductor device comprising: a wiring board; and a semiconductor element having a plurality of protruding electrodes provided with grooves each having an opening at an edge thereof and mounted on the wiring board via the protruding electrodes. The semiconductor device according to claim 1, wherein the plurality of protruding electrodes are arranged such that the openings are alternately oriented inside or outside the semiconductor device. 4. A substrate provided with a display element, and a semiconductor element having a projection electrode having a recess on the upper surface formed on a connection pad and mounted on the substrate via the projection electrode. Characteristic display device. 5. A semiconductor on which a substrate provided with a display element and a protruding electrode having a groove having at least one opening at an edge thereof are formed on a connection pad and mounted on the substrate via the protruding electrode. A display device comprising: an element. 6. A substrate provided with a display element, and a semiconductor element having a plurality of projecting electrodes having grooves each having an opening at an edge formed therein and mounted on the substrate via the projecting electrodes. In the semiconductor device, the plurality of protruding electrodes are arranged such that the openings are alternately oriented to the inside or the outside of the semiconductor device.