JP6168586B2 - Bonding method and semiconductor module manufacturing method - Google Patents

Bonding method and semiconductor module manufacturing method Download PDF

Info

Publication number
JP6168586B2
JP6168586B2 JP2013027968A JP2013027968A JP6168586B2 JP 6168586 B2 JP6168586 B2 JP 6168586B2 JP 2013027968 A JP2013027968 A JP 2013027968A JP 2013027968 A JP2013027968 A JP 2013027968A JP 6168586 B2 JP6168586 B2 JP 6168586B2
Authority
JP
Japan
Prior art keywords
bonding agent
electrode
module substrate
semiconductor chip
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013027968A
Other languages
Japanese (ja)
Other versions
JP2014157926A (en
Inventor
史樹 加藤
史樹 加藤
仲川 博
博 仲川
豊群 郎
豊群 郎
佐藤 弘
弘 佐藤
山口 浩
浩 山口
俊典 小柏
俊典 小柏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Tanaka Kikinzoku Kogyo KK
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK, National Institute of Advanced Industrial Science and Technology AIST filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP2013027968A priority Critical patent/JP6168586B2/en
Publication of JP2014157926A publication Critical patent/JP2014157926A/en
Application granted granted Critical
Publication of JP6168586B2 publication Critical patent/JP6168586B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • H01L2224/29019Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering

Landscapes

  • Die Bonding (AREA)

Description

本発明は、接合方法及び半導体モジュールの製造方法に関する。   The present invention relates to a bonding method and a semiconductor module manufacturing method.

近年、パワーモジュールなどの半導体モジュールで用いられる半導体チップとして、低い順電流抵抗と高速スイッチング性能を持ち、200℃を超える高温でも動作可能なSiCやGaNなどのワイドギャップの半導体チップが注目されている。この半導体チップを用いた半導体モジュールでは、放熱構造を簡略化できるので、その分高密度化、高集積化を図ることができ、例えばパワーモジュールに採用した場合には、単位面積当たりのパワー密度を飛躍的に向上できる。   In recent years, wide-gap semiconductor chips such as SiC and GaN, which have low forward current resistance and high-speed switching performance and can be operated even at a high temperature exceeding 200 ° C., are attracting attention as semiconductor chips used in semiconductor modules such as power modules. . In the semiconductor module using this semiconductor chip, since the heat dissipation structure can be simplified, it is possible to achieve higher density and higher integration. For example, when used in a power module, the power density per unit area is reduced. It can be improved dramatically.

また、従来、半導体チップをモジュール基板に実装し半導体モジュールを構成するにあたり、半導体チップをモジュール基板上に配置し、半導体チップの基板側の面の電極(例えばドレイン電極)をダイボンドでモジュール基板の電極と接合し、基板と反対側の面の電極(例えばソース・ゲート電極)をワイヤーボンディングでモジュール基板の電極と接続する、いわゆる二次元実装が行われていた(特許文献1参照)が、近年、半導体チップの両面にモジュール基板を配置し、半導体チップの両面の電極を各モジュール基板の電極に接合する、いわゆる三次元実装が提案されている。この三次元実装では、ワイヤーボンディングが不要となるため、二次元実装に比べて回路の高密度化、省スペース化、低インダクタンス化が図られる。   Conventionally, when a semiconductor chip is mounted on a module substrate to form a semiconductor module, the semiconductor chip is disposed on the module substrate, and an electrode (for example, drain electrode) on the substrate side of the semiconductor chip is die-bonded to form an electrode on the module substrate. In recent years, so-called two-dimensional mounting has been performed in which an electrode (for example, a source / gate electrode) on the surface opposite to the substrate is connected to the electrode of the module substrate by wire bonding (see Patent Document 1). So-called three-dimensional mounting has been proposed in which module substrates are arranged on both sides of a semiconductor chip, and electrodes on both sides of the semiconductor chip are joined to the electrodes of each module substrate. This three-dimensional mounting eliminates the need for wire bonding, and therefore can achieve higher circuit density, space saving, and lower inductance than two-dimensional mounting.

特開2011−138808号公報JP 2011-138808 A

ところで、上述の三次元実装では、例えば半導体チップの両面の電極に各モジュール基板の電極を接合する必要があり、また複数の半導体チップを順にモジュール基板に接合する必要があるため、半導体チップの電極の接合を一括して行うことができず、接合を複数回行う必要がある。このため、一旦接合されたはんだが再溶融しないように、接合の回数に応じて、融点の異なる複数種のはんだを用意する必要がある。しかしながら、例えば上述のような200℃を超える高温動作可能な半導体チップを三次元実装する場合には、動作時に溶融しないように融点が200℃を超えるはんだが必要となるが、この種のはんだはまだ種類が少ないため、はんだのみで三次元実装を行うのは現実的に難しい。   By the way, in the above-described three-dimensional mounting, for example, it is necessary to bond the electrodes of each module substrate to the electrodes on both sides of the semiconductor chip, and it is necessary to sequentially bond a plurality of semiconductor chips to the module substrate. This joining cannot be performed at once, and it is necessary to perform joining several times. For this reason, it is necessary to prepare a plurality of types of solder having different melting points according to the number of times of joining so that the solder once joined does not remelt. However, for example, when a semiconductor chip capable of operating at a high temperature exceeding 200 ° C. as described above is three-dimensionally mounted, a solder having a melting point exceeding 200 ° C. is required so as not to melt at the time of operation. Since there are still few types, it is practically difficult to perform 3D mounting using only solder.

そこで、複数回の接合の一部に、はんだに代えて、接合電極の表面と同じ素材の金などの金属粒子を含むペースト状の接合剤を用い、当該接合剤を焼結させて電極同士を接合することを考えている。焼結後には接合剤の融点が上がるため、複数回の接合にも耐え得るようになる。   Therefore, instead of solder, a paste-like bonding agent containing metal particles such as gold of the same material as the surface of the bonding electrode is used instead of solder, and the bonding agent is sintered to bond the electrodes together. I'm thinking of joining. Since the melting point of the bonding agent increases after sintering, it can withstand multiple bonding.

しかしながら、その場合、電極に接合剤を塗布し、電極間に圧力をかけて接合剤を挟み込んで接合する必要があるため、接合剤が電極間から横にはみ出すことが考えられる。半導体チップは、例えばソース電極とゲート電極のように近接した電極もあるため、接合剤が電極からはみ出すと、隣接する電極間などで短絡が生じる恐れがある。   However, in that case, since it is necessary to apply a bonding agent to the electrodes and apply pressure between the electrodes to sandwich the bonding agent, the bonding agent may protrude laterally from between the electrodes. A semiconductor chip includes adjacent electrodes such as a source electrode and a gate electrode, for example. If the bonding agent protrudes from the electrode, there is a possibility that a short circuit may occur between adjacent electrodes.

本発明は、かかる点に鑑みてなされたものであり、半導体チップの両面にモジュール基板が接合される三次元実装の半導体モジュールにおいて、金属粒子を含むペースト状の接合剤を用いて、当該接合剤が電極から横にはみ出さないように電極同士を接合する接合方法とその接合法を用いた半導体モジュールの製造方法を提供することをその目的とする。   The present invention has been made in view of such points, and in a three-dimensionally mounted semiconductor module in which a module substrate is bonded to both surfaces of a semiconductor chip, the bonding agent is used by using a paste-like bonding agent containing metal particles. It is an object of the present invention to provide a joining method for joining electrodes so that they do not protrude laterally from the electrodes, and a method for manufacturing a semiconductor module using the joining method.

上記目的を達成するための本発明は、半導体チップの両面にモジュール基板が接合される半導体モジュールにおいて、少なくとも一方のモジュール基板の電極と半導体チップの電極とを接合する方法であって、前記半導体チップの電極と前記モジュール基板の電極それぞれに、金属粒子を含むペースト状の接合剤を塗布する工程と、前記半導体チップ及び前記モジュール基板のうちの一方の電極の前記接合剤の表面に凹凸を形成する工程と、表面に凹凸がある状態で前記接合剤を硬化する工程と、前記半導体チップ及び前記モジュール基板のうちの前記一方の電極の前記表面に凹凸がある状態で硬化した前記接合剤と、他方の電極の未硬化の前記接合剤を合わせる工程と、合わせられた前記接合剤の金属粒子を焼結させる工程と、を有する、接合方法である。   To achieve the above object, the present invention provides a method for joining at least one module substrate electrode and a semiconductor chip electrode in a semiconductor module in which a module substrate is joined to both surfaces of a semiconductor chip, the semiconductor chip comprising: A step of applying a paste-like bonding agent containing metal particles to each of the electrodes of the module substrate and the electrodes of the module substrate, and forming irregularities on the surface of the bonding agent of one of the semiconductor chip and the module substrate A step of curing the bonding agent with unevenness on the surface, the bonding agent cured with unevenness on the surface of the one electrode of the semiconductor chip and the module substrate, and the other The step of combining the uncured bonding agent of the electrode and the step of sintering the metal particles of the combined bonding agent, It is the case method.

前記接合剤を塗布する工程は、スクリーンマスクを電極上に配置し、当該スクリーンマスクを通じて前記ペースト状の接合剤を電極に塗布するスクリーン印刷を用いて行い、前記接合剤の表面に凹凸を形成する工程は、前記スクリーンマスクを電極から離脱させることにより行ってもよい。   The step of applying the bonding agent is performed using screen printing in which a screen mask is disposed on the electrode and the paste adhesive is applied to the electrode through the screen mask, thereby forming irregularities on the surface of the bonding agent. The step may be performed by removing the screen mask from the electrode.

上記接合方法は、前記表面に凹凸がある状態で前記接合剤を硬化する工程の前に、板状部材を前記接合剤の表面に押しつけ、前記凹凸の凸部の高さを揃える工程を、さらに有していてもよい。   The bonding method further includes a step of pressing the plate-like member against the surface of the bonding agent and aligning the height of the protrusions of the unevenness before the step of curing the bonding agent with the surface being uneven. You may have.

前記板状部材により揃えられる前記凸部の高さは、最終的に電極間に配置される接合剤の目標厚に設定されてもよい。   The height of the convex portion aligned by the plate-like member may be set to a target thickness of the bonding agent that is finally disposed between the electrodes.

前記ペースト状の接合剤は、粒径が0.05以上、0.5μm以下の金微粒子を有する金ペーストであってもよい。 The pasty bonding agent has a particle size of 0.05 or more, may be a gold paste having the following gold particles 0.5 [mu] m.

前記半導体チップの片面に形成されたゲート電極及びソース電極と、前記モジュール基板の電極とを接合するようにしてもよい。   You may make it join the gate electrode and source electrode which were formed in the single side | surface of the said semiconductor chip, and the electrode of the said module substrate.

前記モジュール基板面内に複数の半導体チップを実装し、表面に凹凸がある前記接合剤を前記モジュール基板の電極に形成し、前記接合剤を硬化する際には、前記複数の半導体チップの電極に対応する前記モジュール基板の総ての電極の接合剤を一括して加熱して硬化するようにしてもよい。   A plurality of semiconductor chips are mounted on the module substrate surface, the bonding agent having irregularities on the surface is formed on the electrode of the module substrate, and when the bonding agent is cured, the bonding agent is applied to the electrodes of the plurality of semiconductor chips. You may make it harden by heating collectively the bonding agent of all the electrodes of the said corresponding module board | substrate.

別の観点による本発明は、上記接合方法を用いて半導体モジュールを製造する方法である。   The present invention according to another aspect is a method of manufacturing a semiconductor module using the bonding method.

本発明によれば、半導体チップの電極とモジュール基板の電極とを、金属粒子を含むペースト状の接合剤を用いて、当該接合剤が電極から横にはみ出さないように接合できる。   According to the present invention, an electrode of a semiconductor chip and an electrode of a module substrate can be bonded using a paste-like bonding agent containing metal particles so that the bonding agent does not protrude laterally from the electrode.

半導体モジュールの一例を示す図である。It is a figure which shows an example of a semiconductor module. 半導体チップの電極とモジュール基板の電極の構造の一例を示す説明図である。It is explanatory drawing which shows an example of the structure of the electrode of a semiconductor chip, and the electrode of a module substrate. モジュール基板上にスクリーンマスクを配置し、電極上に接合剤を塗布する工程を示す説明図である。It is explanatory drawing which shows the process of arrange | positioning a screen mask on a module board | substrate, and apply | coating a bonding agent on an electrode. モジュール基板の電極の接合剤の表面に凹凸を形成する工程を示す説明図である。It is explanatory drawing which shows the process of forming an unevenness | corrugation in the surface of the bonding agent of the electrode of a module substrate. 接合剤の表面の凹凸の凸部の高さを揃える工程を示す説明図である。It is explanatory drawing which shows the process of aligning the height of the convex part of the unevenness | corrugation of the surface of a bonding agent. 表面に凹凸がある状態で硬化された接合剤を示す説明図である。It is explanatory drawing which shows the bonding | curing agent hardened | cured in the state with an unevenness | corrugation on the surface. 半導体チップ上にスクリーンマスクを配置し、電極上に接合剤を塗布する工程を示す説明図である。It is explanatory drawing which shows the process of arrange | positioning a screen mask on a semiconductor chip, and apply | coating a bonding agent on an electrode. 半導体チップの電極上に塗布された接合剤を示す説明図である。It is explanatory drawing which shows the bonding agent apply | coated on the electrode of a semiconductor chip. 半導体チップの電極とモジュール基板の電極を対向させる工程を示す説明図である。It is explanatory drawing which shows the process of making the electrode of a semiconductor chip and the electrode of a module substrate oppose. 半導体チップの電極の接合剤とモジュール基板の電極の接合剤を合わせる工程を示す説明図である。It is explanatory drawing which shows the process of match | combining the bonding agent of the electrode of a semiconductor chip, and the bonding agent of the electrode of a module substrate. 半導体チップとモジュール基板の電極間の接合剤を焼結する工程を示す説明図である。It is explanatory drawing which shows the process of sintering the bonding agent between the electrode of a semiconductor chip and a module substrate. 一実施例としての電極への金ペーストのスクリーン印刷後の回路基板を示す図面に代わる写真である。It is the photograph replaced with drawing which shows the circuit board after the screen printing of the gold paste to the electrode as one Example. 金ペーストの凹凸の状態を示すレーザ顕微鏡3D高さマッピング像である。It is a laser microscope 3D height mapping image which shows the uneven | corrugated state of a gold paste. 突起高さ均一化後の凹凸の状態を示すレーザ顕微鏡3D高さマッピング像である。It is a laser microscope 3D height mapping image which shows the state of the unevenness | corrugation after processus | protrusion height equalization.

以下、図面を参照して本発明の好ましい実施の形態について説明する。図1は、本実施の形態にかかる接合方法が適用される半導体モジュール1の構成の概略を示す模式図である。   Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram showing an outline of a configuration of a semiconductor module 1 to which the bonding method according to the present embodiment is applied.

半導体モジュール1は、パワーモジュールなどのいわゆる三次元実装構造を有するものであり、複数の半導体チップ10と、これらの半導体チップ10の各電極面に接合されたモジュール基板11、12を有している。また、半導体チップ10は、例えば200℃を超える高温でも動作可能なSiCやGaNのチップ本体からなるワイドギャップの半導体チップである。   The semiconductor module 1 has a so-called three-dimensional mounting structure such as a power module, and includes a plurality of semiconductor chips 10 and module substrates 11 and 12 bonded to respective electrode surfaces of these semiconductor chips 10. . The semiconductor chip 10 is a wide-gap semiconductor chip composed of a SiC or GaN chip body that can operate at a high temperature exceeding 200 ° C., for example.

各半導体チップ10は、例えば一方の面に複数の電極、例えばゲート電極20とソース電極21を有し、他方の面にドレイン電極22を有している。   Each semiconductor chip 10 has, for example, a plurality of electrodes such as a gate electrode 20 and a source electrode 21 on one surface and a drain electrode 22 on the other surface.

半導体チップ10のゲート電極20とソース電極21は、モジュール基板11の電極30に後述の接合剤Aにより接合されている。半導体チップ10のドレイン電極22は、モジュール基板12の電極31に例えばはんだBにより接合されている。   The gate electrode 20 and the source electrode 21 of the semiconductor chip 10 are bonded to the electrode 30 of the module substrate 11 by a bonding agent A described later. The drain electrode 22 of the semiconductor chip 10 is joined to the electrode 31 of the module substrate 12 by, for example, solder B.

ゲート電極20とソース電極21は、例えば図2に示すようにSiCのチップ本体の表面に形成されたNi、Ti、Ag、Pt、Pd、Al(図2では、NiとAl)などの金属の薄膜と、その表面に形成されたAuの薄膜により構成されている。Au薄膜は例えば厚み0.01μm〜10μm程度である。   The gate electrode 20 and the source electrode 21 are made of metal such as Ni, Ti, Ag, Pt, Pd, and Al (Ni and Al in FIG. 2) formed on the surface of the SiC chip body as shown in FIG. It consists of a thin film and a thin Au film formed on the surface. The Au thin film has a thickness of about 0.01 μm to 10 μm, for example.

モジュール基板11の電極30は、例えばSiN基板の表面に形成されたCuの膜と、その表面に形成されたNi-P、Ni-Bの単層膜や、Ni-P又はNi-Bとその上に積層されるバリアメタル(WN,Ta、TaN,Ti,TiN,Pd)からなる二層膜などの薄膜と、その表面に形成されたAuの薄膜により構成されている。このAu薄膜も例えば0.01μm〜10μmの範囲から任意に設定される厚みを採り得る。   The electrode 30 of the module substrate 11 includes, for example, a Cu film formed on the surface of a SiN substrate, a single-layer film of Ni-P and Ni-B formed on the surface, Ni-P or Ni-B and its It is composed of a thin film such as a two-layer film made of barrier metal (WN, Ta, TaN, Ti, TiN, Pd) and an Au thin film formed on the surface thereof. This Au thin film can also take the thickness arbitrarily set, for example from the range of 0.01 micrometer-10 micrometers.

接合剤Aは、接合対象の電極20、21、30の表面と同じ材質の、粒径0.05μm〜0.5μmのサブミクロンの金微粒子を含む金ペーストを焼結させたものである。接合剤Aの厚みは、例えば約1μm〜100μmの範囲から任意に選択された所定の目標厚に設定されている。接合剤Aの材料の金ペーストは、金含有量が90wt%以上と高く、自己レベリングが生じない、または自己レベリングが生じ難い高い粘性を有している。金ペーストには、例えば田中貴金属工業製のAuRoFUSE(登録商標)が用いられる。   The bonding agent A is obtained by sintering a gold paste containing submicron gold fine particles having a particle diameter of 0.05 μm to 0.5 μm and made of the same material as the surfaces of the electrodes 20, 21, 30 to be bonded. The thickness of the bonding agent A is set to a predetermined target thickness arbitrarily selected from a range of about 1 μm to 100 μm, for example. The gold paste of the material of the bonding agent A has a high viscosity such that the gold content is as high as 90 wt% or more and self-leveling does not occur or self-leveling hardly occurs. For example, AuRoFUSE (registered trademark) manufactured by Tanaka Kikinzoku Kogyo is used as the gold paste.

本実施の形態にかかる接合方法は、上記半導体モジュール1における例えば半導体チップ10のゲート電極20及びソース電極21とモジュール基板11の電極30との接合に適用される。以下、当該部分の接合方法について説明する。   The bonding method according to the present embodiment is applied to, for example, bonding of the gate electrode 20 and the source electrode 21 of the semiconductor chip 10 and the electrode 30 of the module substrate 11 in the semiconductor module 1. Hereinafter, the joining method of the said part is demonstrated.

先ず、スクリーン印刷機において、図3に示すようにメッシュ状のスクリーンマスク50によりモジュール基板11の表面が覆われる。そして、スキージ51によりペースト状の接合剤Aがスクリーンマスク50を通じて電極30上に流し込まれ、ペースト状の接合剤Aが電極30上に印刷塗布される。なお、このとき、半導体チップ10が実装されるモジュール基板11上の総ての電極30に対し一括して接合剤Aが塗布される。   First, in the screen printing machine, the surface of the module substrate 11 is covered with a mesh screen mask 50 as shown in FIG. Then, the paste-like bonding agent A is poured onto the electrode 30 through the screen mask 50 by the squeegee 51, and the paste-like bonding agent A is printed and applied onto the electrode 30. At this time, the bonding agent A is collectively applied to all the electrodes 30 on the module substrate 11 on which the semiconductor chip 10 is mounted.

次に、図4に示すようにスクリーンマスク50がモジュール基板11の表面から上方に離脱する。このとき、スクリーンマスク50のメッシュ線とともに接合剤Aの一部が上方に引っ張られ、接合剤Aの表面にスクリーンマスク50のメッシュに起因する凹凸が形成される。接合剤Aの表面におけるメッシュ線の交差部分に対応する部分には、凸部60が形成され、メッシュ線の孔部分に対応する部分は、凹部61となる。なお、このとき、接合剤Aの粘度が高いため、スクリーンマスク50により接合剤Aの一部がよく引っ張られ十分な凹凸が形成される。また凸部60の高さは、接合剤Aの最終的な目標厚Dより大きくなる。   Next, the screen mask 50 is detached upward from the surface of the module substrate 11 as shown in FIG. At this time, a part of the bonding agent A is pulled upward together with the mesh lines of the screen mask 50, and irregularities due to the mesh of the screen mask 50 are formed on the surface of the bonding agent A. A convex portion 60 is formed at a portion corresponding to the intersecting portion of the mesh line on the surface of the bonding agent A, and a portion corresponding to the hole portion of the mesh line is a concave portion 61. At this time, since the viscosity of the bonding agent A is high, a part of the bonding agent A is pulled well by the screen mask 50 to form sufficient unevenness. Moreover, the height of the convex part 60 becomes larger than the final target thickness D of the bonding agent A.

次に、図5に示すように板状部材70が接合剤A表面の凹凸の凸部60に押し付けられる。この板状部材70は、例えば方形のガラス製、フッ素樹脂製、あるいはポリエチレン製などであり、スクリーンマスク50よりも接合剤Aに対する濡れ性が低いものが用いられる。押し付けた際の板状部材70の高さ(板状部材70と電極30とのギャップ)は、電極表面からの凸部60の高さが接合剤Aの最終的な目標厚Dになるように設定される。こうして、凸部60の高さが揃えられる。   Next, as shown in FIG. 5, the plate-like member 70 is pressed against the uneven protrusion 60 on the surface of the bonding agent A. The plate-like member 70 is made of, for example, square glass, fluororesin, or polyethylene, and has a lower wettability with respect to the bonding agent A than the screen mask 50. The height of the plate-like member 70 when pressed (the gap between the plate-like member 70 and the electrode 30) is such that the height of the convex portion 60 from the electrode surface becomes the final target thickness D of the bonding agent A. Is set. Thus, the heights of the convex portions 60 are aligned.

次に、板状部材70が凸部60に押し付けられた状態で、接合剤Aが所定時間、所定温度(例えば2分程度、200℃程度)で加熱され仮焼結される。これにより、図6に示すように接合剤Aが表面に凹凸がある状態で硬化する。なお、この加熱工程では、モジュール基板11の全体が加熱され、モジュール基板11の電極30の総ての接合剤Aが一括で加熱され、硬化する。また、この加熱により、モジュール基板11の電極30の表面のAuの薄膜と接合剤Aも接合する。   Next, in a state where the plate-like member 70 is pressed against the convex portion 60, the bonding agent A is heated and pre-sintered at a predetermined temperature (for example, about 2 minutes, about 200 ° C.) for a predetermined time. Thereby, as shown in FIG. 6, the bonding agent A is cured in a state where the surface is uneven. In this heating step, the entire module substrate 11 is heated, and all the bonding agents A of the electrodes 30 of the module substrate 11 are heated at once and cured. Moreover, the thin film of Au on the surface of the electrode 30 of the module substrate 11 and the bonding agent A are also bonded by this heating.

ここで、一実施例として、実際に接合剤Aとして金ペーストを用い、これをSiN−AMC(Active Material brazed Copper)回路基板のゲート電極及びソース電極にスクリーン印刷した。その結果を図12に示す。スクリーンマスクのメッシュ痕がペースト表面に残り、周期的な凹凸が現れていることが分かる。使用したスクリーンマスクは、乳剤厚が10μm、メッシュ線径が30μm、紗厚60μm、メッシュ間隔100μmのものである。印刷時にはこのメッシュの開口部分をペーストが通過し、メッシュの下に回り込むことによって、マスクパターン開口部全面にペーストが印刷塗布される。この時点でペーストはメッシュに接触しているので、マスクを引き離す版離れ工程の際に、ペーストが表面張力でメッシュに引き摺られ、メッシュ痕が形成される。塗布直後の回路上の金ペーストを、非接触三次元測定装置を用いて計測すると、厚みは平均30μmで、薄い部分で25μmであった。凹凸の間隔は100μmであった。凹凸の間隔とメッシュの間隔が同じであることから、この凹凸がメッシュ起因であると判断できる。この凹凸はメッシュに引き摺られて形成されたものであるため、突起の頂点高さ、つまり凸部の高さにばらつきが生じている。計測された突起の最大高さは85μm、突起の最小高さは60μmで、25μmの高さばらつきがあった。印刷された金ペーストを、凸部の高さを揃えずにそのまま仮焼結した際の表面形状について、レーザ顕微鏡の3D高さマッピング像を図13に示す。仮焼結後もメッシュのピッチにあわせた凹凸およびメッシュ交差部の突起が確認できる。図の視野範囲内で最も高い突起は36.8μm(電極表面から58.8μm)、最も低い突起は28.1μm(電極表面から50.1μm)で、その差は8.7μmであった。続いて、このペーストの凹凸にガラスをペーストに押しつけ、突起の高さを揃えてから仮焼結を行った。金ペースト塗布直後の突起の高さが60〜85μmの範囲であったため、基板とガラスのギャップを60μmに設定して、突起の頂点部を押しつぶし、200℃、2分の仮焼結を行った。図14にこの突起抑制プロセスにより凸部が均されたメッシュ痕のレーザ顕微鏡による3D高さマッピング像を示す。高さ22.8μm(電極表面から44.8μm)に突起部が平らに均されていることがわかる。各頂点の高さバラツキは±0.1μm程度であった。このプロセスは、両面実装モジュールにおけるチップ接合時の実装高さばらつき、あるいは傾きの原因となる金ペースとの高さばらつきを抑制することにも繋がる。尚、以上のデータが一実施例に過ぎないことは言うまでもない。   Here, as an example, a gold paste was actually used as the bonding agent A, and this was screen-printed on the gate electrode and the source electrode of an SiN-AMC (Active Material brazed Copper) circuit board. The result is shown in FIG. It can be seen that the mesh marks of the screen mask remain on the paste surface and periodic irregularities appear. The screen mask used has an emulsion thickness of 10 μm, a mesh wire diameter of 30 μm, a cocoon thickness of 60 μm, and a mesh interval of 100 μm. During printing, the paste passes through the opening of the mesh and wraps under the mesh, whereby the paste is printed and applied to the entire mask pattern opening. Since the paste is in contact with the mesh at this point, the paste is dragged to the mesh by the surface tension during the plate separation process for separating the mask, and a mesh mark is formed. When the gold paste on the circuit immediately after coating was measured using a non-contact three-dimensional measuring apparatus, the thickness was 30 μm on average and 25 μm at the thin part. The interval between the irregularities was 100 μm. Since the unevenness interval and the mesh interval are the same, it can be determined that the unevenness is caused by the mesh. Since the unevenness is formed by being dragged by the mesh, there is a variation in the apex height of the protrusion, that is, the height of the convex portion. The maximum height of the measured protrusion was 85 μm, the minimum height of the protrusion was 60 μm, and there was a height variation of 25 μm. FIG. 13 shows a 3D height mapping image of a laser microscope with respect to the surface shape when the printed gold paste is temporarily sintered without aligning the heights of the protrusions. Even after the preliminary sintering, it is possible to confirm the irregularities and the protrusions at the mesh intersections that match the pitch of the mesh. The highest protrusion in the field of view of the figure was 36.8 μm (58.8 μm from the electrode surface), the lowest protrusion was 28.1 μm (50.1 μm from the electrode surface), and the difference was 8.7 μm. Subsequently, glass was pressed against the paste irregularities, and the height of the protrusions was made uniform, and then preliminary sintering was performed. Since the height of the protrusion immediately after application of the gold paste was in the range of 60 to 85 μm, the gap between the substrate and the glass was set to 60 μm, the apex portion of the protrusion was crushed, and preliminary sintering was performed at 200 ° C. for 2 minutes. . FIG. 14 shows a 3D height mapping image by a laser microscope of a mesh mark whose convex portions are leveled by this protrusion suppression process. It can be seen that the protrusions are leveled to a height of 22.8 μm (44.8 μm from the electrode surface). The height variation of each vertex was about ± 0.1 μm. This process also leads to suppression of mounting height variation at the time of chip bonding in the double-sided mounting module or height variation from the gold pace that causes inclination. It goes without saying that the above data is only one example.

一方、スクリーン印刷機において、図7に示すようにメッシュ状のスクリーンマスク50により半導体チップ10の電極20、21表面が覆われる(なお、図7には、一つの電極のみを示す)。そして、スキージ51によりペースト状の接合剤Aがスクリーンマスク50を通じて電極20、21上に流し込まれ、接合剤Aが電極20、21上に印刷塗布される。このときの接合剤Aの塗布量は、モジュール基板11側で硬化した接合剤Aの凹部61の総容積と同等に設定される。その後、半導体チップ10上からスクリーンマスク50が離脱する。こうして、図8に示すように半導体チップ10の電極20(21)上に、硬化していないペースト状の接合剤Aが塗布された状態となる。   On the other hand, in the screen printing machine, the surfaces of the electrodes 20 and 21 of the semiconductor chip 10 are covered with a mesh screen mask 50 as shown in FIG. 7 (note that only one electrode is shown in FIG. 7). Then, the paste-like bonding agent A is poured onto the electrodes 20 and 21 through the screen mask 50 by the squeegee 51, and the bonding agent A is printed and applied onto the electrodes 20 and 21. The application amount of the bonding agent A at this time is set to be equal to the total volume of the concave portions 61 of the bonding agent A cured on the module substrate 11 side. Thereafter, the screen mask 50 is detached from the semiconductor chip 10. In this way, as shown in FIG. 8, the uncured paste-like bonding agent A is applied on the electrode 20 (21) of the semiconductor chip 10.

次に、加熱装置において、図9に示すように、モジュール基板11が下部ヘッド80に保持され、半導体チップ10が上部ヘッド81に保持され、モジュール基板11の電極30と半導体チップ10の電極20、21とが、対向するように位置合わせされる。その後、図10に示すようにモジュール基板11の電極30上で硬化した接合剤Aに、半導体チップ10のペースト状の接合剤Aが押し付けられる。このとき、モジュール基板11側の接合剤Aが硬化しているので、半導体チップ10側のペースト状の接合剤Aが凹部61に入り込む。そして、半導体チップ10側のペースト状の接合剤Aの量が、凹部61の総容積と同等であるので、半導体チップ10側の接合剤Aが凹部61を埋め、接合剤A全体が1μm〜100μm程度の所定の目標厚Dになる。   Next, in the heating apparatus, as shown in FIG. 9, the module substrate 11 is held by the lower head 80, the semiconductor chip 10 is held by the upper head 81, the electrode 30 of the module substrate 11, the electrode 20 of the semiconductor chip 10, 21 are aligned so as to face each other. Thereafter, as shown in FIG. 10, the paste-like bonding agent A of the semiconductor chip 10 is pressed against the bonding agent A cured on the electrode 30 of the module substrate 11. At this time, since the bonding agent A on the module substrate 11 side is cured, the paste-like bonding agent A on the semiconductor chip 10 side enters the recess 61. Since the amount of the paste-like bonding agent A on the semiconductor chip 10 side is equivalent to the total volume of the recess 61, the bonding agent A on the semiconductor chip 10 side fills the recess 61, and the entire bonding agent A is 1 μm to 100 μm. A predetermined target thickness D is obtained.

その後、接合剤Aが、所定時間(例えば2分)、第1の温度である所定温度(例えば200℃程度)で加熱され仮焼結され、その後、所定時間(例えば10分)、第2の温度である所定温度(例えば250℃)で焼結され、図11に示すように半導体チップ10側の接合剤Aとモジュール基板11側の接合剤Aが金属接合される。また、これらの加熱により、半導体チップ10の電極20、21表面のAuの薄膜と接合剤Aも接合する。こうして、半導体チップ10の電極20,21とモジュール基板11の電極30が接合される。その後、半導体チップ10及びモジュール基板11を自然冷却する。   Thereafter, the bonding agent A is heated and pre-sintered at a predetermined temperature (for example, about 200 ° C.) that is a first temperature for a predetermined time (for example, 2 minutes), and then for a predetermined time (for example, 10 minutes) for the second time. Sintering is performed at a predetermined temperature (for example, 250 ° C.), and the bonding agent A on the semiconductor chip 10 side and the bonding agent A on the module substrate 11 side are metal bonded as shown in FIG. Moreover, the thin film of Au on the surfaces of the electrodes 20 and 21 of the semiconductor chip 10 and the bonding agent A are also bonded by these heating. Thus, the electrodes 20 and 21 of the semiconductor chip 10 and the electrode 30 of the module substrate 11 are joined. Thereafter, the semiconductor chip 10 and the module substrate 11 are naturally cooled.

なお、半導体チップ10のドレイン電極22とモジュール基板12の電極31との接合は、例えばはんだBを用いてダイボンドすることで行われる。   The drain electrode 22 of the semiconductor chip 10 and the electrode 31 of the module substrate 12 are joined by die bonding using, for example, solder B.

本実施の形態によれば、半導体チップ10の電極20、21とモジュール基板11の電極30に金微粒子を含むペースト状の接合剤Aをそれぞれ塗布し、モジュール基板11側の電極30の接合剤Aを表面に凹凸を形成して硬化し、そのモジュール基板11側の接合剤Aと、半導体チップ10側のペースト状の未硬化の接合剤Aとを合わせているので、モジュール基板11側の硬化した接合剤Aが鋳型のような役目を果たし、当該接合剤Aの凹凸の凹部に半導体チップ10の未硬化の接合剤Aが入り込む。この結果、はんだに代えて、金属粒子を含むペースト状の接合剤Aを用いても、接合剤Aが電極の横にはみ出さないように電極同士を接合することができる。このように接合剤Aを用いることができるので、融点の異なる複数種のはんだが必要なく、複数回の接合工程のある三次元実装を適切に行うことができる。さらに、高温動作可能な半導体チップの三次元実装も実現できる。   According to the present embodiment, the paste-like bonding agent A containing gold fine particles is applied to the electrodes 20 and 21 of the semiconductor chip 10 and the electrode 30 of the module substrate 11, respectively, and the bonding agent A of the electrode 30 on the module substrate 11 side is applied. The surface of the module substrate 11 is hardened, and the bonding agent A on the module substrate 11 side is combined with the paste-like uncured bonding agent A on the semiconductor chip 10 side. The bonding agent A serves as a mold, and the uncured bonding agent A of the semiconductor chip 10 enters the concave and convex portions of the bonding agent A. As a result, the electrodes can be bonded to each other so that the bonding agent A does not protrude to the side of the electrodes even if a paste-like bonding agent A containing metal particles is used instead of the solder. Since the bonding agent A can be used in this way, a plurality of types of solder having different melting points are not required, and three-dimensional mounting with a plurality of bonding steps can be appropriately performed. Furthermore, three-dimensional mounting of a semiconductor chip that can be operated at high temperature can be realized.

また、モジュール基板11の電極30に接合剤Aを塗布する工程をスクリーン印刷を用いて行い、スクリーンマスク50を電極30から離脱させることにより、接合剤Aの表面に凹凸を簡単かつ適切に形成できる。特に、スクリーン印刷によれば、規則的で安定した凹凸を形成できるので、半導体チップ10側に塗布する接合剤Aの量を定めやすく、接合剤Aのはみ出しをより確実に抑制できる。   Further, the step of applying the bonding agent A to the electrode 30 of the module substrate 11 is performed using screen printing, and the screen mask 50 is separated from the electrode 30, whereby irregularities can be easily and appropriately formed on the surface of the bonding agent A. . In particular, according to screen printing, regular and stable irregularities can be formed. Therefore, it is easy to determine the amount of the bonding agent A applied to the semiconductor chip 10 side, and the protrusion of the bonding agent A can be more reliably suppressed.

本実施の形態において、接合剤Aを硬化する工程の前に、板状部材70を接合剤Aの表面に押しつけ、表面の凸部60の高さを揃えるので、凹部61の容積がより一定になり、半導体チップ10側の塗布剤Aの量を定めやすくなる。よって、接合剤Aのはみ出しをより確実に抑制できる。また、モジュール基板11側の接合剤Aと半導体チップ10側の接合剤Aを合わせたときの接合剤A全体の厚みも安定させることができる。   In the present embodiment, before the step of curing the bonding agent A, the plate-like member 70 is pressed against the surface of the bonding agent A, and the height of the convex portions 60 on the surface is made uniform, so that the volume of the concave portions 61 is made more constant. Thus, the amount of the coating agent A on the semiconductor chip 10 side can be easily determined. Therefore, the protrusion of the bonding agent A can be more reliably suppressed. In addition, the thickness of the entire bonding agent A when the bonding agent A on the module substrate 11 side and the bonding agent A on the semiconductor chip 10 side are combined can be stabilized.

板状部材70により揃えられる凸部60の高さは、最終的に電極間に配置される接合剤Aの目標厚Dに設定されているので、後工程で半導体チップ10側の接合剤Aをモジュール基板11側の接合剤Aに押し付け、半導体チップ10側の接合剤Aをモジュール基板11側の接合剤Aの凹部61に入れることにより、最終的な接合剤Aの厚みを目標厚Dに調整しやすくなる。   Since the height of the convex portion 60 aligned by the plate-like member 70 is set to the target thickness D of the bonding agent A that is finally disposed between the electrodes, the bonding agent A on the semiconductor chip 10 side is used in a later step. The final thickness of the bonding agent A is adjusted to the target thickness D by pressing the bonding agent A on the module substrate 11 side and putting the bonding agent A on the semiconductor chip 10 side into the recess 61 of the bonding agent A on the module substrate 11 side. It becomes easy to do.

本実施の形態では、上記接合方法を用いて、半導体チップ10の片面のゲート電極20及びソース電極21と、モジュール基板11の電極30とを接合している。よって、数十〜数百μm程度の狭小な間隔のゲート電極20、ソース電極21であっても、短絡することなくそれぞれをモジュール基板11と接合できる。   In the present embodiment, the gate electrode 20 and the source electrode 21 on one side of the semiconductor chip 10 and the electrode 30 of the module substrate 11 are bonded using the above bonding method. Therefore, even the gate electrode 20 and the source electrode 21 with a narrow interval of about several tens to several hundreds of μm can be joined to the module substrate 11 without being short-circuited.

ところで、サブミクロンの金微粒子を含む金ペーストの接合剤Aと、モジュール基板11の一般的な電極のCu/Ni-P/Auメッキ表面との接合では、当該電極を大気中で200℃程度で加熱したような熱履歴があると、接合が十分に行われない。そのため、一のモジュール基板11の面内に複数の半導体チップ10を実装する場合に、各半導体チップ10に対しその都度モジュール基板11を高温に加熱してフリップチップで接合すると、一つ目の半導体チップ10は接合できるが、二つ目以降の半導体チップ10は、モジュール基板11側に熱履歴があるため、接合が困難になる。モジュール基板の電極表面のAuの膜厚を数μmに厚くすることでこの問題を回避できることが実験で明らかになった。しかしながら、この方法では、モジュール基板の電極表面全体に厚い金メッキを塗る必要が生じ、コスト的な問題が生じる。   By the way, in joining the bonding agent A of a gold paste containing submicron gold fine particles and the Cu / Ni-P / Au plating surface of a general electrode of the module substrate 11, the electrode is kept at about 200 ° C. in the atmosphere. If there is a heat history such as heating, bonding is not sufficiently performed. Therefore, when a plurality of semiconductor chips 10 are mounted on the surface of one module substrate 11, each module chip 11 is heated to a high temperature and bonded to each semiconductor chip 10 by a flip chip each time. The chip 10 can be bonded, but the second and subsequent semiconductor chips 10 have a thermal history on the module substrate 11 side, so that bonding becomes difficult. Experiments have shown that this problem can be avoided by increasing the thickness of the Au film on the module substrate electrode to several μm. However, in this method, it is necessary to apply a thick gold plating to the entire electrode surface of the module substrate, which causes a cost problem.

本実施の形態によれば、複数の半導体チップ10の電極20、21に対応するモジュール基板11の電極30の総ての接合剤Aを一括して加熱して硬化するので、熱履歴のあるモジュール基板11の電極30に金ペーストの接合剤Aを接合することがなく、総ての接合剤Aとモジュール基板11との接合を適切に行うことができる。また、電極表面に厚い金メッキを形成する必要がないため、コスト的な問題も解消できる。さらに、金ペーストが塗布される部分は接合部分だけなので、電極表面全体に厚い金メッキを形成する場合に比べてこの点でもコストを低減できる。   According to the present embodiment, since all the bonding agents A of the electrodes 30 of the module substrate 11 corresponding to the electrodes 20 and 21 of the plurality of semiconductor chips 10 are collectively heated and cured, a module having a thermal history The bonding agent A of the gold paste is not bonded to the electrode 30 of the substrate 11, and all the bonding agents A and the module substrate 11 can be appropriately bonded. Further, since it is not necessary to form a thick gold plating on the electrode surface, the cost problem can be solved. Furthermore, since the portion to which the gold paste is applied is only the joint portion, the cost can be reduced in this respect as compared with the case where thick gold plating is formed on the entire electrode surface.

以上、添付図面を参照しながら本発明の好適な実施の形態について説明したが、本発明はかかる例に限定されない。当業者であれば、特許請求の範囲に記載された思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。   The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood.

例えば以上の実施の形態では、スクリーン印刷のメッシュ状のスクリーンマスク50により接合剤Aの表面に凹凸を形成していたが、他の方法、例えばステンシルマスクなどの開口部を使い、スキージなどを使って接着剤Aを塗布し、マスクを表面から離脱させることにより凹凸を形成してもよい。あるいは、凹凸の無い接合材Aを形成した後に、バンプなどの柱状構造を別に形成し、スペーサー(凹凸)としても良い。   For example, in the above embodiment, the surface of the bonding agent A is formed with irregularities by the screen-printed mesh screen mask 50. However, other methods, for example, using a stencil mask or the like and using a squeegee or the like. Then, the unevenness may be formed by applying the adhesive A and releasing the mask from the surface. Alternatively, after forming the bonding material A having no unevenness, a columnar structure such as a bump may be formed separately to form a spacer (unevenness).

また、接合剤Aは、サブミクロンの金微粒子を含む金ペーストであったが、銀などの他の金属粒子を含むペーストであってもよい。このときの金属粒子には、電極表面と同じ材質を選択する。また、モジュール基板11側の電極の接合剤Aに凹凸を形成しそれを硬化していたが、半導体チップ10側の電極の接合剤Aに凹凸を形成し硬化させ、当該半導体チップ10側の接合剤Aにモジュール基板11側の未硬化の接合剤Aを合わせてもよい。   The bonding agent A is a gold paste containing submicron gold fine particles, but may be a paste containing other metal particles such as silver. The same material as the electrode surface is selected for the metal particles at this time. Further, the unevenness was formed on the bonding agent A of the electrode on the module substrate 11 side and cured, but the unevenness was formed on the bonding agent A of the electrode on the semiconductor chip 10 side and cured to bond the bonding on the semiconductor chip 10 side. The uncured bonding agent A on the module substrate 11 side may be combined with the agent A.

また、本発明は、本実施の形態の半導体チップ10やモジュール基板11の構成以外の構成を有する半導体モジュールにも適用できる。また、半導体チップの両面にモジュール基板が接合される半導体モジュールにおいて、本実施の形態にかかる接合方法を、一方のモジュール基板の電極と半導体チップの電極との接合だけでなく、両方の接合に適用してもよい。また、本実施の形態にかかる接合方法は、片面に複数の電極を有する半導体チップとモジュール基板を接合するものであったが、片面に一つの電極を有する半導体チップとモジュール基板を接合する際に適用してもよい。   The present invention can also be applied to a semiconductor module having a configuration other than the configuration of the semiconductor chip 10 and the module substrate 11 of the present embodiment. In addition, in the semiconductor module in which the module substrate is bonded to both surfaces of the semiconductor chip, the bonding method according to the present embodiment is applied not only to the bonding of the electrode of one module substrate and the electrode of the semiconductor chip but also to the bonding of both. May be. Further, the bonding method according to the present embodiment is a method of bonding a semiconductor chip having a plurality of electrodes on one side and a module substrate. However, when bonding a semiconductor chip having one electrode on one side and a module substrate. You may apply.

上記実施の形態では、板状部材70を接合剤Aの表面に押しつけ、表面の凸部60の高さを揃えていたが、この工程はなくてもよく、接合剤Aの表面に凹凸をつけた後、直ちに接合剤Aを硬化させてもよい。   In the above embodiment, the plate-like member 70 is pressed against the surface of the bonding agent A, and the height of the convex portions 60 on the surface is made uniform. However, this step is not necessary, and the surface of the bonding agent A is made uneven. After that, the bonding agent A may be cured immediately.

1 半導体モジュール
10 半導体チップ
11 モジュール基板
20 ゲート電極
21 ソース電極
22 ドレイン電極
30 電極
50 スクリーンマスク
60 凸部
61 凹部
70 板状部材
A 接合剤
DESCRIPTION OF SYMBOLS 1 Semiconductor module 10 Semiconductor chip 11 Module board | substrate 20 Gate electrode 21 Source electrode 22 Drain electrode 30 Electrode 50 Screen mask 60 Convex part 61 Concave part 70 Plate-shaped member A Bonding agent

Claims (8)

半導体チップの両面にモジュール基板が接合される半導体モジュールにおいて、少なくとも一方のモジュール基板の電極と半導体チップの電極とを接合する方法であって、
前記半導体チップの電極と前記モジュール基板の電極それぞれに、金属粒子を含むペースト状の接合剤を塗布する工程と、
前記半導体チップ及び前記モジュール基板のうちの一方の電極の前記接合剤の表面に凹凸を形成する工程と、
表面に凹凸がある状態で前記接合剤を硬化する工程と、
前記半導体チップ及び前記モジュール基板のうちの前記一方の電極の前記表面に凹凸がある状態で硬化した前記接合剤と、他方の電極の未硬化の前記接合剤を合わせる工程と、
合わせられた前記接合剤の金属粒子を焼結させる工程と、を有する、接合方法。
In a semiconductor module in which a module substrate is bonded to both surfaces of a semiconductor chip, a method of bonding an electrode of at least one module substrate and an electrode of a semiconductor chip,
Applying a paste-like bonding agent containing metal particles to each of the electrode of the semiconductor chip and the electrode of the module substrate;
Forming irregularities on the surface of the bonding agent of one of the semiconductor chip and the module substrate; and
Curing the bonding agent in a state where the surface has irregularities;
The step of combining the bonding agent cured in a state where the surface of the one electrode of the semiconductor chip and the module substrate is uneven and the uncured bonding agent of the other electrode;
Sintering the combined metal particles of the bonding agent.
前記接合剤を塗布する工程は、スクリーンマスクを電極上に配置し、当該スクリーンマスクを通じて前記ペースト状の接合剤を電極に塗布するスクリーン印刷を用いて行い、
前記接合剤の表面に凹凸を形成する工程は、前記スクリーンマスクを電極から離脱させることにより行う、請求項1に記載の接合方法。
The step of applying the bonding agent is performed using screen printing in which a screen mask is arranged on the electrode, and the paste adhesive is applied to the electrode through the screen mask.
The bonding method according to claim 1, wherein the step of forming irregularities on the surface of the bonding agent is performed by separating the screen mask from the electrode.
前記表面に凹凸がある状態で前記接合剤を硬化する工程の前に、板状部材を前記接合剤の表面に押しつけ、前記凹凸の凸部の高さを揃える工程を、さらに有する、請求項1又は2に記載の接合方法。   The method further comprises the step of pressing a plate-like member against the surface of the bonding agent and aligning the heights of the protrusions of the unevenness before the step of curing the bonding agent with the surface having unevenness. Or the joining method of 2. 前記板状部材により揃えられる前記凸部の高さは、最終的に電極間に配置される接合剤の目標厚に設定される、請求項3に記載の接合方法。   The bonding method according to claim 3, wherein the height of the convex portion aligned by the plate-like member is set to a target thickness of a bonding agent that is finally disposed between the electrodes. 前記ペースト状の接合剤は、粒径が0.05μm以上、0.5μm以下の金微粒子を有する金ペーストである、請求項1〜4のいずれかに記載の接合方法。 The bonding method according to claim 1, wherein the paste-like bonding agent is a gold paste having gold fine particles having a particle size of 0.05 μm or more and 0.5 μm or less . 前記半導体チップの片面に形成されたゲート電極及びソース電極と、前記モジュール基板の電極とを接合する、請求項1〜5のいずれかに記載の接合方法。   The bonding method according to claim 1, wherein a gate electrode and a source electrode formed on one surface of the semiconductor chip are bonded to an electrode of the module substrate. 前記モジュール基板面内に複数の半導体チップを実装し、
表面に凹凸がある前記接合剤を前記モジュール基板の電極に形成し、
前記接合剤を硬化する際には、前記複数の半導体チップの電極に対応する前記モジュール基板の総ての電極の接合剤を一括して加熱して硬化する、請求項1〜6のいずれかに記載の接合方法。
A plurality of semiconductor chips are mounted in the module substrate surface,
Forming the bonding agent having irregularities on the surface thereof on the electrode of the module substrate;
When curing the bonding agent, the bonding agent for all the electrodes of the module substrate corresponding to the electrodes of the plurality of semiconductor chips is collectively heated and cured. The joining method described.
請求項1〜7のいずれかに記載の接合方法を用いて半導体モジュールを製造する方法。   The method to manufacture a semiconductor module using the joining method in any one of Claims 1-7.
JP2013027968A 2013-02-15 2013-02-15 Bonding method and semiconductor module manufacturing method Active JP6168586B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013027968A JP6168586B2 (en) 2013-02-15 2013-02-15 Bonding method and semiconductor module manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013027968A JP6168586B2 (en) 2013-02-15 2013-02-15 Bonding method and semiconductor module manufacturing method

Publications (2)

Publication Number Publication Date
JP2014157926A JP2014157926A (en) 2014-08-28
JP6168586B2 true JP6168586B2 (en) 2017-07-26

Family

ID=51578633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013027968A Active JP6168586B2 (en) 2013-02-15 2013-02-15 Bonding method and semiconductor module manufacturing method

Country Status (1)

Country Link
JP (1) JP6168586B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6936595B2 (en) * 2017-03-15 2021-09-15 株式会社 日立パワーデバイス Semiconductor device
JP7214966B2 (en) * 2018-03-16 2023-01-31 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JP7238621B2 (en) * 2019-06-20 2023-03-14 株式会社デンソー Semiconductor device, method for manufacturing sintered sheet, method for manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4400441B2 (en) * 2004-12-14 2010-01-20 三菱電機株式会社 Semiconductor device
JP5120917B2 (en) * 2006-11-30 2013-01-16 独立行政法人産業技術総合研究所 Semiconductor device and manufacturing method thereof
JP5449958B2 (en) * 2009-09-30 2014-03-19 株式会社日立製作所 Semiconductor device, connection structure and manufacturing method thereof
JP5971543B2 (en) * 2011-12-28 2016-08-17 国立研究開発法人産業技術総合研究所 Semiconductor module and semiconductor chip mounting method

Also Published As

Publication number Publication date
JP2014157926A (en) 2014-08-28

Similar Documents

Publication Publication Date Title
US8569109B2 (en) Method for attaching a metal surface to a carrier, a method for attaching a chip to a chip carrier, a chip-packaging module and a packaging module
JP6770853B2 (en) Lead frames and electronic component equipment and their manufacturing methods
US10847691B2 (en) LED flip chip structures with extended contact pads formed by sintering silver
JP6004441B2 (en) Substrate bonding method, bump forming method, and semiconductor device
TWI255466B (en) Polymer-matrix conductive film and method for fabricating the same
US20170294322A1 (en) Wiring board, electronic device, and electronic module
JP5272922B2 (en) Semiconductor device and manufacturing method thereof
JP5920077B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6168586B2 (en) Bonding method and semiconductor module manufacturing method
US9589864B2 (en) Substrate with embedded sintered heat spreader and process for making the same
JP2010153742A (en) Substrate with through electrode, light emitting device, and method of manufacturing substrate with through electrode
JP5397744B2 (en) Multilayer ceramic substrate, electronic component using the same, and method of manufacturing multilayer ceramic substrate
CN108346640B (en) Semiconductor structure and manufacturing method thereof
JP2017005007A (en) Semiconductor device and semiconductor device manufacturing method
JP5100715B2 (en) Semiconductor device and manufacturing method of semiconductor device
WO2014125536A1 (en) Semiconductor module and semiconductor chip mounting method
CN105990155A (en) Chip package substrate, chip package structure and manufacturing method thereof
CN110504234A (en) A kind of superchip welding structure and welding method
JP2004079710A (en) Semiconductor device and its manufacturing method, circuit board as well as electronic apparatus
JP2007220740A (en) Semiconductor device and manufacturing method thereof
JP6762871B2 (en) How to reduce the difference in solder pad morphology by flattening
US20220148944A1 (en) Electronic device and method for manufacturing electronic device
US12021043B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2013191678A (en) Multilayer wiring board
JPH09116249A (en) Semiconductor device and display device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151125

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160119

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20161006

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161013

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161206

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170531

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170622

R150 Certificate of patent or registration of utility model

Ref document number: 6168586

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250