JP5397744B2 - Multilayer ceramic substrate, electronic component using the same, and method of manufacturing multilayer ceramic substrate - Google Patents

Description

  The present invention relates to a multilayer ceramic substrate and an electronic component using the same. The present invention also relates to a method for manufacturing a multilayer ceramic substrate.

Today, multilayered ceramic substrates are widely used as devices that require high functionality and small size such as cellular phones are increasing. In a general multilayer ceramic substrate, a plurality of ceramic substrate layers are laminated, and a wiring layer having internal wiring is formed between the ceramic substrate layers. These wiring layers are connected by wiring called via wiring.
On the surface of the multilayer ceramic substrate, semiconductor package components (IC chips, etc.) made of active elements and chip components (chip capacitors, etc.) made of passive elements are respectively mounted on the surface. Implementation is required.

  Patent Document 1 shows an example of the structure of such a multilayer ceramic substrate. In the multilayer ceramic substrate disclosed in Patent Document 1, a ceramic laminate formed by laminating a plurality of ceramic layers, a recess formed on one main surface of the ceramic laminate, and a connection exposed inside the recess. And a terminal electrode mainly composed of a conductive resin that is filled in the recess and is electrically connected to the connection electrode.

  Further, Patent Document 2 discloses a self-position correction function (self-alignment function) in which a surface lead-out portion of a via hole conductor is formed to be recessed by 20 μm or less from the surface of a multilayer ceramic substrate and a bump curved surface is fitted to the edge of the recess. ) Is disclosed.

  On the other hand, Patent Document 3 discloses a multilayer ceramic substrate in which substrates having tapered via holes in which one opening area is larger than the other opening area are stacked. Here, an example is shown in which the via hole of the outermost ceramic substrate layer is formed in a tapered hole shape that narrows toward the outermost surface side.

JP 2007-305740 A JP 2001-189550 A JP 2003-258160 A

  However, the gist of the multilayer ceramic substrate disclosed in Patent Document 1 is to improve the impact resistance of the connection terminal electrode with the mother substrate. Therefore, a conductive resin is required for the connecting portion, and the depth of the resin is preferably 100 μm or more. However, the finer the electrode size, the more difficult it is to fill the resin and the easier it is to manufacture. In addition, it is not realistic to stably apply metal plating to the surface of the conductive resin. Furthermore, Patent Document 1 discloses that an Ag—Pd alloy or an Ag—Pt alloy has a low specific resistance and is suitable for high frequency applications. The effect on mechanical strength is not considered.

  Also in Patent Document 2, the mechanical strength when the bump and the via hole conductor are connected is not considered. Further, in order to achieve self-alignment, it is necessary to make the recess depth relatively deep. Thus, when forming a recessed part comparatively deeply, when printing paste of solder paste, a bubble-like nest tends to remain in a recessed part, and electrical and mechanical connection reliability may be impaired. At this time, since the via conductor is formed using the conductive paste having a large shrinkage rate even when the metal plating is provided, the plating solution may be left on the inner wall of the via hole and corrosion may occur.

  In the multilayer ceramic substrate disclosed in Patent Document 3, attention is paid to the electrical connection performance and thermal conductivity of via holes, and tapered via holes are used for thermal vias. However, no consideration is given to the influence on the mechanical strength of the surface layer terminal electrode when connecting the surface mount components.

By the way, electrodes of LGA (LAND GRID ARRAY) and BGA (BALL GRID ARRAY) are formed as a complicated wiring pattern on the outermost surface of the multilayer ceramic substrate. The distance between these electrodes is becoming as narrow as several hundred to 150 μm, and in the case of a semiconductor package component, the distance is further narrowed by flip chip mounting. For this reason, BGA using solder balls of several hundred μm formed on bumps has become mainstream. In this case, the number of solder balls ranges from several tens to several hundreds, sometimes 1000 or more. The number varies depending on the application and function of the semiconductor element, but a connection shear strength of about 50 gf or more per electrode is required. This numerical value is at a high level as a connection with a solder ball of several hundred μm.
On the other hand, in the case of a chip component, the number of electrodes may be originally small, and the LGA using pad electrodes is also selectively used in order to give priority to securing connection strength. However, it is still desirable to have a higher density and higher strength electrode.
From the above, a ceramic substrate having a terminal electrode structure that can narrow the electrode interval and has high connection strength is desired.

  The present invention has been made in view of the above circumstances, and it is possible to increase the mounting density. At this time, even if the terminal electrode is reduced, the bonding strength with the surface-mounted component can be improved due to structural features. It is another object of the present invention to provide a multilayer ceramic substrate having a low possibility of corrosion due to the absence of a plating chemical solution and an electronic component using the same. It is another object of the present invention to provide a manufacturing method suitable for the multilayer ceramic substrate.

  The present invention for solving the problems of the above-described conventional example is a multilayer ceramic substrate in which a plurality of ceramic substrate layers are laminated, and has a tapered shape that narrows toward the outermost surface of the uppermost and lowermost ceramic substrate layers. A via hole is provided to connect a surface layer terminal electrode composed of a surface layer via electrode provided in the via hole and a metal plating layer deposited on an end face thereof, and the surface layer terminal electrode and a wiring on an internal ceramic substrate layer. A surface via electrode of the ceramic substrate layer on the outermost surface on at least one side of the front and back surfaces, the surface being inside a via hole provided in the ceramic substrate layer on the outermost surface, and the ceramic on the outermost surface The surface of the metal plating layer deposited on the end surface of the surface layer via electrode at a position recessed from the surface of the substrate layer is substantially flush with the surface of the ceramic substrate layer on the outermost surface or the outermost surface. A multilayer ceramic substrate characterized in that in the a position recessed from the ceramic substrate layer. Here, the substantially same plane means that, for example, a protrusion of less than the thickness of the metal plating layer is allowed at most up to about 3 μm.

  The boundary surface of the metal plating layer that contacts the inner wall of the via hole coincides with no gap. For example, when the cross section is seen with a scanning electron microscope (magnification: 3000 times), there is no void or gap between the metal plating layer and the inner wall of the via hole, and the plating layer is uneven on the inner wall. Refers to an embodiment in which is closely attached.

  In the multilayer ceramic substrate, the via hole provided in the ceramic substrate layer other than the uppermost ceramic substrate layer on the front and back surfaces may be formed in a tapered shape that extends toward the outermost surface on one side.

  In the multilayer ceramic substrate, the diameter of the tapered via hole that narrows toward each outermost surface provided on at least one outermost ceramic substrate layer on the front and back surfaces is other than the outermost ceramic substrate layer on the front and back surfaces. It can be formed smaller than the diameter of the via hole provided in the ceramic substrate layer.

  Similarly, the length of the tapered via hole narrowed toward the outermost surface of at least one of the front and back outermost ceramic substrate layers is a ceramic substrate other than the outermost ceramic substrate layer of the front and back surfaces. It can be formed shorter than the length of the via hole provided in the layer.

  The present invention is an electronic component characterized in that a surface-mounted component is mounted on the metal plating layer using a solder ball, using any of the multilayer ceramic substrates described above.

  The present invention also includes a step of integrally generating a ceramic green sheet on a carrier film to form a ceramic green sheet with a carrier film, and applying a laser beam to each ceramic green sheet with a carrier film to form a tapered via. A step of forming a hole, a printing step of printing and forming internal wiring and via wiring at a predetermined position of the ceramic green sheet with a carrier film using a conductive material, and a ceramic green sheet with a carrier film of the first layer The carrier film is peeled, a ceramic green sheet with a second layer of the carrier film is laminated on the peeled ceramic green sheet, and then pressure-bonded. Thereafter, the carrier film is peeled off, and thereafter, lamination, pressure bonding, and peeling are performed in the same manner. Repeat until the green multilayer ceramic laminate A multilayer ceramic comprising: a step of forming; a sintering step of firing the unsintered multilayer ceramic laminate; and a step of depositing a metal plating layer on a surface via electrode of the sintered multilayer ceramic laminate A method of manufacturing a substrate, wherein the step of forming a tapered via hole by irradiating each ceramic green sheet with a carrier film to form a tapered via hole is difficult to be absorbed by the carrier film from above the carrier film. When the first via hole is processed by irradiating the first laser beam having a shorter length, the second laser beam having a wavelength longer than that of the first laser beam is irradiated from above the ceramic green sheet. A method of manufacturing a multilayer ceramic substrate, wherein the second via hole is processed.

  In the method for manufacturing a multilayer ceramic substrate, in the step of forming a tapered via hole by irradiating each ceramic green sheet with a carrier film with a laser beam, the processing of the first via hole is The ceramic green sheet with a carrier film of the first layer corresponding to at least one outermost surface is subjected to laser light in the ultraviolet region, and the processing of the second via hole is performed with the ceramic green with carrier film of the second layer and subsequent layers. It can be performed using laser light in the infrared region on the sheet.

According to the present invention, the distance between the electrodes can be narrowed, the density can be increased, and a small-sized multilayer ceramic substrate having a terminal electrode structure with high connection strength can be obtained.
In addition, the present invention is suitable for a method for manufacturing a small multilayer ceramic substrate having a narrow electrode interval and a high density, and particularly suppresses a problem that the conductor material is pulled out from the via hole in the process of peeling the carrier film from the ceramic green sheet. be able to.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a chart showing a manufacturing process of a multilayer ceramic substrate according to the present embodiment.

[Manufacture of multilayer ceramic substrates]
In the step of forming the multilayer ceramic substrate of the present embodiment, first, a plurality of ceramic green sheets are generated. For this purpose, a slurry comprising a mixture of ceramic material powder, glass component powder, organic binder, plasticizer and solvent, which can be fired at a low temperature, is formed on an organic carrier film (for example, PET film) by a doctor blade method to form a film having a predetermined thickness. And dried (S1). The thickness of the slurry after drying varies depending on the purpose, but in this example, it is about 20 to 200 μm.

The ceramic material that can be sintered at a low temperature for the ceramic green sheet is a ceramic material that can be co-fired at 800 to 1000 ° C. with a conductive material such as silver (Ag) (hereinafter referred to as a conductive paste), so-called LTCC. Any ceramic can be used. As an example, when Al, Si, Sr, and Ti, which are main components, are converted into Al ₂ O ₃ , SiO ₂ , SrO, and TiO ₂ , respectively, Al ₂ O ₃ : 10 to 60% by mass, SiO ₂ : 25 to 25% 60% by mass, SrO: 7.5 to 50% by mass, TiO ₂ : 20% by mass or less (including 0), Bi, Na, K, Co as subcomponents with respect to 100 parts by mass of the main component At least one of these groups is 0.1 to 10% by mass in terms of Bi ₂ O ₃ , 0.1 to 5% by mass in terms of Na ₂ O, 0.1 to 5% by mass in terms of K ₂ O, CoO contain 0.1 to 5 wt% in terms of further, Cu, Mn, 0.01 to 5 mass% of at least one kind selected from the group of Ag in terms of CuO, 0.01 to 5 mass% with MnO ₂ in terms of , Containing 0.01 to 5% by mass of Ag and other inevitable impurities Compounds once was calcined at 700 ° C. to 850 ° C., it can be mentioned dielectric ceramic composition comprising finely divided particles having an average particle diameter of 0.6~2μm by pulverizing it.

  The generation of the ceramic green sheet that can be fired at a low temperature is not limited to the doctor blade method described here, and may be generated by, for example, a rolling (extrusion) method, a printing method, an ink jet coating method, a transfer method, or the like. . At this time, the ceramic green sheet forms a ceramic green sheet with a carrier film integrally formed on a thin carrier film such as a PET film. And it cuts as it is, without peeling from a carrier film, and a some ceramic green sheet is obtained (S2). Although it is easy to handle with a green sheet, it is also a reasonable manufacturing method to use it for subsequent printing or the like while repeating winding / unwinding in a roll shape without cutting.

  And a via hole is formed in each ceramic green sheet with a carrier film using a laser according to the target circuit (S3). As shown in FIG. 4, the via hole 11 has a wide opening diameter on the laser incident side, and can be formed in a tapered shape that gradually narrows toward the emission side, that is, the side from which the laser beam exits after passing through the via hole. Here, for the ceramic green sheet 1a of the first layer on the upper surface, as shown in FIG. 4 (a), the processing device is such that the carrier film 5 is on the laser incident side and the ceramic green sheet 1a on the opposite side is on the laser emitting side. The via hole 11 is processed on the support table. On the other hand, the ceramic green sheet 1b other than the first layer on the upper surface, the second layer 1b, the third layer 1c,... Are on the laser incident side as shown in FIG. The carrier film 5 is mounted on the support table of the processing apparatus so that the carrier film 5 is on the laser emission side, and via hole processing is performed.

  In this embodiment, in the via hole processing for the ceramic green sheet 1a of the first layer on the upper surface, the laser beam energy is hardly absorbed by the carrier film 5, and laser light having a wavelength that is easily absorbed by the ceramic green sheet 1a. Used. In the case of a PET film, since there is an absorption band at a wavelength of 10.6 μm, the hole 34 processed in the carrier film 5 is small as shown in FIG. 5A by selecting a wavelength that avoids this wavelength band. However, a sufficiently large hole 11 can be processed for the ceramic green sheet 1a. Then, in the printing process described later, only the via hole 11 is filled with the conductor paste 2 without being insufficient. Rather, if the carrier film 5 is also filled with the conductor paste, the conductor paste 2 filled in the via hole 11 is pulled out together with the carrier film 5 as shown in FIG. May occur. However, if the wavelength of the laser beam is selected as described above, the conductor paste 2 filled in the via hole is difficult to be pulled out as shown in FIG. 5C, thereby preventing conduction failure due to unconnected via wiring. It becomes possible. As an example of the laser wavelength to be selected, ultraviolet light having a wavelength of 0.35 μm or YAG laser having a wavelength of 1.06 μm is used for processing the via hole in the first layer ceramic green sheet 1a on the upper surface, and the first layer on the upper surface is excluded. In other ceramic green sheets 1b, 1c,... Via holes, infrared rays having a wavelength of 10.6 μm can be cited.

Thereafter, the conductive paste 2 containing silver (Ag) as a main component is disposed in each via hole 11 via a printing screen, the conductive paste 2 is press-fitted into the via hole 11 with a squeegee, and the excess conductive paste 2 is peeled off. Thus, a via conductor is produced (S4). At this time, in all the ceramic green sheets 1a, 1b, ..., the ceramic green sheet is mounted on the support base of the printing apparatus so that the ceramic green sheet is on the printing screen side and the carrier film 5 is on the support base side. Perform the process.
Further, a conductive pattern corresponding to a target circuit is formed on the surface of each ceramic green sheet 1b including the first layer ceramic green sheet 1a on the upper surface by using a conductive paste such as silver (Ag). Is formed to a thickness of 5 to 35 μm (S5). Internal wirings such as inductors, transmission lines, capacitors, and ground electrodes are formed by these conductor patterns, and are connected to each other by via wiring by the via conductor to constitute a target circuit wiring.
In the case of the ceramic green sheet 1a of the first layer on the upper surface, it is necessary to print so that a minute conductor pattern is close to a narrow space and a large number of small mounting components and semiconductor components can be mounted. At this time, if the via hole is filled and printed with a conductor paste mainly composed of Ag and the step of forming the surface conductor pattern is repeated a plurality of times, it is difficult to achieve high density because misalignment is likely to occur. . Therefore, the filling printing of the via holes may be performed at once, which also serves as the printing of the surface conductor pattern.

  Next, a plurality of ceramic green sheets on which via conductors and / or conductor patterns are formed are pressure-bonded by pressing (S6), and the step of peeling the carrier film (S7) is repeated by the number of ceramic substrate layers, and is unfired. A sintered multilayer ceramic laminate (hereinafter simply referred to as an “unsintered multilayer ceramic body”) is produced.

As an example, the ceramic green sheet 1a with the carrier film of the first layer that is located on the outermost surface side of the unsintered multilayer ceramic body is inverted so that the carrier film 5 side is on the fixing film 6 And press and press with a mold at a predetermined pressure, temperature and time. For example, the pressure is 1 to 5 MPa (10 to 50 kgf / cm ² ), the temperature is 30 to 60 ° C., and the time is 3 to 15 seconds. The die 7 on and under thermocompression bonding may be a simple flat plate shape with a built-in heater. As shown in FIG. 5C, the opening side narrowed in a tapered shape is set on the fixing film 6 for the via hole 11. As a result, a tapered via hole narrowing toward the outermost surface of the outermost ceramic substrate layer is formed. When the press bonding by the press is finished, the carrier film 5 is peeled from the ceramic green sheet 1a. At this time, the ceramic green sheet 1a is fixed to the fixing film 6 and is not peeled off together with the carrier film. Further, as described above, if the laser wavelength for forming the via hole is appropriately selected and the small via hole 34 is formed so that the continuous through via hole 11 is not formed in the carrier film 5, the carrier film is peeled off. At this time, the conductor paste 2 filled in the via hole 11 of the ceramic green sheet 1a is difficult to be pulled out together, and as a result, it is possible to prevent the occurrence of poor conduction due to the unconnected via wiring.

  Next, the second ceramic green sheet 1b is laminated. On the ceramic green sheet 1b, a conductor pattern P constituting the internal circuit wiring is printed. The ceramic green sheet 1b is set so that the main surface is in contact with the first layer ceramic green sheet 1a, and is pressed and pressure-bonded in the same manner as in the case of the first layer ceramic green sheet. At this time, the via hole 11 is laminated so that the wider taper opening side coincides with the wider taper opening side of the first ceramic green sheet 1a. Thereafter, when the press temperature is set to a temperature at which the adhesive in the printing paste is softened and fixed, the printing portion is joined to the counterpart ceramic green sheet 1a by the applied pressure. Therefore, the ceramic green sheets are bonded together via the printed conductor paste. In addition, where there is no electrode and the ceramic layers are in direct contact with each other, they are softened, fixed and bonded in the same way as when the electrodes are interposed. Although the pressure bonding temperature at this time depends on the type of the pressure-sensitive adhesive, it may be a low temperature of about 40 to 90 ° C., and the bonding strength can be adjusted by changing the pressure. After the pressure bonding, the carrier film 5 of the ceramic green sheet 1b is peeled off. After the third layer ceramic green sheet 1c, the ceramic green sheet corresponding to the outermost layer on the back (bottom) surface side is laminated in the same process as the second layer ceramic green sheet. As a result, a tapered via hole that narrows toward the outermost surface side of the outermost ceramic substrate layer on the bottom surface side is formed. In addition, in order to integrate a laminated body strongly, after crimping | stacking the whole, you may perform a crimping | compression-bonding process further.

  Furthermore, you may perform in the atmosphere which pressure-reduced some or all of the series of processes of crimping | bonding, peeling, and lamination | stacking. If it does in this way, it will be easy to remove the bubble between ceramic green sheets, the dimensional accuracy at the time of lamination | stacking can be maintained, and delamination can be reduced.

  In the present embodiment, a conductive paste mainly composed of Ag is used for the bottom surface of the unsintered multilayer ceramic body thus obtained (opposite surface facing the surface of the outermost ceramic substrate layer). According to the circuit, the bottom surface electrode is printed and formed (S8).

  Further, an overcoat material may be appropriately formed around the conductor pattern on the substrate surface and the bottom surface. As a material of this overcoat material, it is desirable that the sintering shrinkage characteristic and the thermal expansion characteristic are similar to the raw material of the unsintered multilayer ceramic body. For example, what added the additive component for providing the function which improves the visibility of a coating part to the slurry of the same material as a ceramic green sheet is mentioned. By covering the periphery of the surface conductor pattern with an overcoat to form an electrode coating region, mechanical protection of the surface conductor pattern and solder provided on the conductor pattern in a later step flow out and contact the conductive portion Can prevent short circuit. Note that the conductor pattern and the overcoat material on the substrate surface do not necessarily have to be provided in a state of an unsintered multilayer ceramic body, and may be formed on the sintered multilayer ceramic substrate.

In the present embodiment, the unsintered multilayer ceramic body thus obtained is thermocompression-bonded at 10 to 40 MPa (100 to 400 kgf / cm ² ) and 85 ° C. with a CIP device, and the unsintered multilayer multilayer body in which the layers are integrated. A ceramic body.

  Next, cut grooves are formed on the surface of the unsintered multilayer ceramic body with a jig such as a knife cutter, and split grooves are formed (S9). The dividing grooves are formed in different shapes depending on the size of the collective substrate and the size of the product substrate. The dividing groove is formed with a sufficient dimensional margin so as not to adversely affect the conductor pattern constituting the circuit, and is formed at a distance of about 100 to 250 μm from the end of the conductor in plan view. This dividing groove is, for example, a V-shaped groove, and the depth is, for example, when the dividing groove is placed on both the upper and lower surfaces, so that the sum of the groove depths on both sides is 30% or less of the thickness of the unsintered multilayer ceramic body. To do. This depth varies depending on the thickness of the unsintered multilayer ceramic body, but is generally about 0.01 to 0.2 mm. This is because if the depth is too deep, the mold of the cutter is poor and deformation is likely to occur, and it becomes a starting point of cracks in the sintering process. The dividing grooves are not necessarily formed on both surfaces, and may be either the top surface or the bottom surface.

  Further, the dividing method is not necessarily limited to the method of dividing along the V-shaped groove, but a method of dicing or scribing may be used after the subsequent firing step without forming the groove.

  Next, the unsintered multilayer ceramic body is integrally fired in a firing furnace at a sintering temperature of 800 to 1000 ° C. (S10). At this stage, in the cross section of the via hole, as illustrated in FIG. 2A, the surface (F) of the surface via electrode which is a part of the external terminal electrode and the surface of the outermost ceramic substrate layer (S) Are substantially on the same plane.

[Surface via electrode etching]
In the present embodiment, the surface layer via electrode (here, Ag here) is immersed in an etching solution having a function of dissolving, and a part of the surface layer via electrode is removed (S11). That is, at this stage, in the cross section of the via hole, as illustrated in FIG. 2B, the surface (F) of the surface via electrode is inside the via hole and is on the outermost surface of the ceramic substrate layer (S). On the other hand, etching is performed up to a concave position. In the following description, after the plating layer is formed on the surface layer via electrode, the surface here is referred to as an end face for distinction. Here, as the etching solution, a mixed solution containing any one of nitric acid, aqua regia, or hydrogen peroxide can be used. When the conductor material to be used is copper or an alloy mainly containing copper, ammonium persulfate can be used as an etching solution. Thereby, the surface of the surface layer via electrode is recessed with respect to the surface of the outermost ceramic substrate layer, and a preferable surface property can be obtained. Thereby, Ni plating, Au plating, etc. can be formed on the electrode with high quality in a later step. That is, by using the etching solution, Ag stuck to the unevenness of the inner wall of the via hole can be dissolved and removed, which can contribute to improving the biting strength (anchor effect). Further, by performing this etching process, the surface of the via hole is sufficiently wetted to remove minute bubbles, so that defects due to minute precipitation defects in the subsequent plating process can be prevented.

  When dissolving the surface via electrode, the type, concentration, and temperature of the etching solution are adjusted in order to obtain a sufficient etching effect without causing damage to the electrode and reducing the adhesion strength between the electrode and the ceramic. Keep it. This adjustment is set experimentally and empirically. For example, nitric acid is 1 to 20% by volume, aqua regia is 1 to 25% by volume, and an etching solution containing hydrogen peroxide is 1 to 30%. Those containing 1% by volume or 1-30% by volume of hydrochloric acid are desirable. It is necessary to pay sufficient attention to the stirring method in the etching bath. In each etching process, the thickness of the remaining electrode is measured using a measuring method such as fluorescent X-ray, and the etching reaction rate is confirmed by comparing with the thickness before etching, and the process conditions are strictly controlled. Furthermore, when the component of the etching solution includes a component that easily volatilizes or a component that easily decomposes, it is desirable to periodically collect and titrate a sample of the solution and monitor the concentration of each component. Monitoring of the concentration of the etched conductor metal that dissolves in the liquid is also performed periodically in exactly the same way.

  Further, the quantitative control of the depth of the recess by etching is performed by controlling the type, concentration, and temperature of the etching solution. However, for example, if the concentration is extremely reduced, the performance of the etching solution is likely to deteriorate with only a small amount of processing, and frequent adjustments must be made. Therefore, it is necessary not to reduce the concentration too much. The temperature is suitably 50 ° C. or lower because the main component of the etching solution is often volatile. This is because if the temperature is higher than this, the concentration of the etching solution and the compounding ratio of the components are likely to fluctuate. Furthermore, the stirring operation such as the circulation of the etching solution and the vertical movement and rotation of the ceramic substrate is effective for controlling the reaction rate including the uniformization of the etching solution. It is desirable to finely adjust the etching processing time while monitoring each processing batch or lot after combining these adjustment methods.

  For such an etching process, in addition to a method of immersing in an etching solution, a method of applying an etching solution so as to be transferred by a roller-like coating head, or a fountain of etching solution from below on a horizontally held ceramic substrate A method of blowing up into a shape may be used. In these methods, the edge of the substrate to be held may be pressed and sealed with rubber packing or the like so that the etching solution does not wrap around the opposite surface, and the processing on each side may be performed. The surface to be sealed with the packing material may be selected according to the design of the apparatus and the type and properties of the etching solution. Usually, since a minute surface layer terminal electrode is unevenly distributed on the upper surface on which a semiconductor or a small chip component is mounted, the structure of the surface layer terminal electrode of the present invention is effective for such an upper surface layer. However, the lower surface layer (bottom surface) on the opposite side is often provided with about 20 to 30 LGA (LAND GRID ARRAY) electrodes having a large dimension of 1 mm or more, and the electrode size is large and the strength can be increased. In the surface layer (bottom surface), the terminal electrode structure of the present embodiment is not necessarily required. In such a case, the above single-side treatment is often effective. The single-sided treatment is advantageous in terms of the manufacturing process, because it is easy on the environment, such as a small amount of water required for the subsequent rinsing process, and the facility design including drying and overall process management become easy and inexpensive.

[Metal plating layer]
Now, after the etching process, sufficient rinsing is performed (S12), and then plating is performed (S13). In this plating process, electroless plating is generally performed so that even a component having a complicated circuit structure is uniformly formed. As an example, Ni base plating 3 to 10 μm, and subsequently Au plating 0.03 to 0.5 μm are applied. Here, in order to prevent a chemical reaction such as undesired diffusion when the Ni base plating layer is used as a product, a buffer layer may be plated between the Au plating.

  By this plating step, as shown in FIG. 2C, a metal plating layer (M) is deposited on the surface via electrode (F), and the surface (MF) of the metal plating layer and the outermost surface The surface of the ceramic substrate layer (S) is substantially flush with the surface (as described below, the protrusion is less than the thickness of the metal plating layer (up to 3 μm in the above example)). Specifically, since a solder ball or the like is placed on the surface of the metal plating layer, it is preferable not to make a large protrusion or to form a deep recess. This range is empirically located at a position 3 μm or less from the outermost ceramic substrate layer surface S in the convex direction, more preferably about 3 μm deep from the outermost ceramic substrate layer surface S in the concave direction. The depth is preferably up to 10 μm or less. Thus, a surface layer terminal electrode composed of the surface layer via electrode (F) and the metal plating layer (M) deposited on the upper portion (end surface) is formed. At this time, it is important that the metal plating layer is closely adhered along the unevenness without any voids or gaps between the end face of the surface via electrode and the inner wall of the via hole.

[No shrinkage method]
In addition, after formation of process S9 and a division | segmentation groove | channel, the green sheet | seat for restraint which restrains so that a board | substrate may not shrink | contract during baking may be arranged on the surface of a non-sintered multilayer ceramic body, and what is called a shrinkage-free construction method may be used. Here, the constraining green sheet is a ceramic slurry prepared by adding an organic binder, a plasticizer, and a solvent to an inorganic material that does not sinter at the firing temperature of the unsintered multilayer ceramic body, and this is applied to the carrier film by the doctor blade method. The film is formed to a predetermined thickness (for example, 100 to 200 μm).

  The ceramic material used for the constraining green sheet does not sinter at the firing temperature (about 800 to 1000 ° C.) of the glass ceramic material used for the ceramic green sheet and has a function of not shrinking the surface of the unsintered multilayer ceramic body. Anything is acceptable. As the inorganic material, alumina is generally used. In addition, the same organic binder, plasticizer and solvent as those used for the ceramic green sheet can be used.

Prior to the sintering step, the constraining green sheets are aligned with the upper and lower surfaces of the unsintered multilayer ceramic body, and the constraining green sheets are laminated so that the thickness of the constraining green sheets is about 200 μm. Then, thermocompression bonding is performed at 10 to 40 MPa (100 to 400 kgf / cm ² ) and 85 ° C. to obtain a laminate in which the constraining layer made of constraining green sheets and the unsintered multilayer ceramic body are integrated.

  Next, this laminated body is integrally fired at 800 to 1000 ° C., which is a temperature at which the unsintered multilayer ceramic body is sintered, while appropriately performing binder removal of the constraining layer in a firing furnace in step S10.

  When the constraining green sheet is used in this way, most of the inorganic particles after firing can be easily removed, but the inorganic particles remaining on the surface via electrode may not be easily removed. In such a case, it is effective to remove residual inorganic particles by ultrasonic cleaning. Here, it is preferable to perform ultrasonic cleaning in an etchant that also serves as a pretreatment process of etching (processing S11), because the surface of the surface via electrode (Ag) can be etched and inorganic particles can be removed. Further, in the rinsing process (S12), ultrasonic cleaning may be performed to ensure cleaning.

[Via hole and surface terminal electrode configuration]
In the present invention, the via hole of the surface layer terminal electrode is formed in a tapered hole shape narrowing toward the outermost surface. As a result, the distance between the electrodes can be reduced and the density can be increased. In addition, the taper-shaped via hole increases the lateral distance of the ceramic in contact with the metal plating layer, which in turn increases the area where the metal plating layer contacts the inner wall of the via hole, increasing the anchor effect and increasing the strength. Contributes to an increase in. In particular, the inner wall surface of the via hole is actually intricately concave and convex, so the effect is great.

  If the via hole d is up to a depth of about 15 μm, it is possible to grow the plating to a level substantially equal to the surface of the ceramic substrate layer within a practical plating time. At this time, the metal plating layer is deposited so as to fill the via hole without any gap in order from the bottom of the via, and it is possible to prevent the plating solution from being left behind by being entrained in the minute irregularities on the inner wall of the via. For this reason, the adhesion of the metal plating layer to the inner wall of the via is improved, which contributes to an increase in mechanical joint strength due to the anchor effect.

  In the multilayer ceramic substrate created by the method of the present embodiment, as shown schematically in FIG. 2C and FIG. The surface layer via electrode is formed so that its surface F is in a recessed position. Further, a metal plating layer is deposited on the surface via electrode, and the surface MF of the metal plating layer is also substantially flush with or recessed from the outermost ceramic substrate surface S.

  The surface layer via electrode is fired together with the firing of the ceramic substrate in the firing step (S10). At this time, it is considered that the boundary between the metal material of the surface layer via electrode and the ceramic substrate (the inner wall surface of the via hole) is intruded into an intricate uneven shape, exerts an anchor effect and produces mutual adhesion. Also, when the firing temperature is in the range of 850 ° C. to 1000 ° C., silver (Ag) and copper (Cu), which are materials for the surface layer via electrode, do not react at the interface with the ceramic or diffuse to each other to improve adhesion. It contributes to further improving the adhesion.

  In FIGS. 2 and 3, the boundary between the surface layer terminal electrode 4 and the ceramic substrate is schematically shown as a straight line. There are no holes or gaps between the Ni base plating 3 a and the end face F of the surface via electrode 2. Similarly, the Ni base plating 3a is in close contact with the unevenness of the inner wall of the via without any voids or gaps. As described above, the metal plating layers 3a and 3b are deposited along the unevenness, and the boundary surfaces thereof coincide with each other without any gap, and the length of the boundary surface and the unevenness width affect the connection strength.

  The contact length of the boundary surface needs to be 2 μm or more. The longer the length is, the higher the connection strength is. However, since there are manufacturing restrictions such as etching accuracy and labor when removing the above-described surface via electrode, the preferred range is about 3 to 8 μm. The uneven width of the boundary surface is preferably 0.6 μm or more. This unevenness width is the heat shrinkage behavior of the ceramic material used, the heat shrinkage behavior of the conductor material filling the via hole, the accuracy of via hole machining, and in the case of laser via machining, the residue after machining, the inner wall of the via hole and the surrounding heat It depends on many factors such as the shape and size of the affected area. Laser processing conditions are effective as process parameters that are easy to control, and main processing conditions such as energy, pulse width, and number of shots can be changed to affect factors such as a heat-affected region. A preferable range of the uneven width is empirically about 0.9 to 5 μm.

  Further, when the metal plating layer 3 has the Ni underlayer 3a and the Au coating 3b, the nickel (Ni) underlayer 3a having a relatively high strength adheres closely to the inner wall of the via hole so as to trace the unevenness of the inner wall of the via hole. It is thought that this also contributes to strength improvement. That is, the Young's modulus of nickel (Ni) is 200 GPa, which is higher than 83 GPa of silver (Ag) and 130 GPa of copper (Cu), which are the materials of the surface via electrode 2. It has a high characteristic of resisting external force by maintaining the state of being in close contact with the inner wall of the hole, and can sufficiently exert the anchor fixing effect. Here, the thickness of the nickel (Ni) base layer 3a is preferably 3 μm or more, and a more preferable range is 4 to 8 μm.

In the conventional general substrate shown in FIG. 8, the end surface of the surface layer via electrode 2 that is continuously connected to the via wiring by extending the via wiring to the outermost surface side is substantially flush with the surface S of the outermost surface ceramic substrate. Or protrude from the surface S of the outermost ceramic substrate. In the case of such a conventional example, the surface layer terminal electrode is in close contact with the corner portion (R) of the opening on the surface side of the via hole, and stress is applied when an external force is applied from the lateral direction as in the shear strength test. This corner that tends to concentrate tends to be the starting point of destruction.

  On the other hand, as illustrated in FIG. 2C and FIG. 3, the end surface F of the surface layer via electrode 2 that is continuously connected to the via wiring by extending the via wiring to the outermost surface side is the outermost surface ceramic substrate 1. The metal plating layer 3 deposited on the end face F of the surface S is recessed substantially in the same plane as the surface S of the outermost ceramic substrate 1 or in a recessed position. Sometimes, the peripheral edge of the upper end of the surface via electrode 2 is in close contact with the inner wall surface of the via hole, and is not in close contact with the corner portion of the opening on the surface side of the via hole that is easily damaged due to stress concentration. Here, “substantially the same plane” means a state of projecting from the surface S of the outermost ceramic substrate 1 by an amount less than the thickness of the metal plating layer 3 (for example, 3 μm or less). Although the metal plating layer 3 may be deposited on the corner portion of the opening on the surface side of the via hole (the metal plating layer 3 does not necessarily extend to the diameter of the via hole, the surface of the surface via electrode 2 surface When the dent is shallow, the outermost surface side of the metal plating layer 3 may slightly protrude from the surface S of the outermost surface ceramic substrate 1 and spread in an umbrella shape). This protrusion is up to 3 μm. If it is 3 μm or less, the anchor effect is superior and breakage can be avoided even if the boundary surface length in close contact with the inner wall of the via hole is about 2 μm. In addition, although there is an anchor effect due to the engagement between the material constituting the metal plating layer 3 and the ceramic substrate, the chemical reaction and interdiffusion are smaller than the material of the surface via electrode 2, Therefore, stress concentration that leads to breakage is unlikely to occur, and as a result, high strength is considered.

  Further, when the metal plating layer 3 is deposited on the surface of the surface via electrode 2 that is substantially flush with the surface of the outermost ceramic substrate as in the conventional general structure, as shown in FIG. Further, the end of the metal plating layer 3 has a pointed shape and is in contact with the surface S of the ceramic substrate (Q). Therefore, when an external force is applied from the lateral direction as in the shear strength test, the stress tends to concentrate on the end portion of the pointed metal plating layer, which tends to be a starting point of fracture. In general, nickel (Ni) having high strength is used as the metal plating layer as the underlayer, so that the possibility of causing stress concentration to become a starting point of fracture becomes higher.

  In the multilayer ceramic substrate of the present embodiment, as illustrated in FIGS. 2C and 3, the surface of the surface via electrode is recessed from the surface of the outermost ceramic substrate in the depth direction of the via hole. The metal plating layer deposited on the top (end surface) is flush with the surface of the outermost ceramic substrate (projects from the surface by less than the thickness of the metal plating layer (for example, 3 μm or less)) or in a recessed position. In some cases, the end portion of the metal plating layer does not have a pointed shape but is in close contact with the entire peripheral surface of the inner wall of the via hole. For this reason, since it has a structure in which breakage due to stress concentration does not easily occur, the strength becomes high.

[Electronic parts]
When such a multilayer ceramic substrate is used, an electronic component is configured by mounting surface-mounted components on the surface of the metal plating layer 3 using solder balls. This electronic component can be used in an electronic device such as a cellular phone.

  In addition to passive elements such as capacitors, inductors, and resistors, the electronic components to be mounted include semiconductor products, and active elements such as module components including an array in which a plurality of passive components are integrated. In the multilayer ceramic substrate of the present embodiment, the end surfaces of all surface layer via electrodes corresponding to these electronic components may not be in a position recessed from the surface of the outermost ceramic substrate layer. Also, the size of the via hole need not be the same. That is, a via hole having a diameter of 60 μm may be formed in a portion where the semiconductor component is mounted when the upper surface component is mounted, and a via hole having a diameter of 100 μm may be formed in a portion where the chip capacitor and the chip resistor are mounted. Here, the via hole having a diameter of φ60 μm is formed in the portion where the semiconductor component is mounted because the arrangement of the semiconductor connection pads is narrow with a pitch of 150 to 200 μm, so in the case of the first ceramic green sheet This is because it is necessary to reduce the via processing diameter in a portion corresponding to a narrow pitch.

  In one example, specifically, a semiconductor product having an outer dimension of 3 mm square and a thickness of 0.25 mm is flip-chip mounted. Here, the shape of the flip chip connection pad formed on the mounting surface of the semiconductor product facing the multilayer ceramic substrate is a substantially square with a side of 100 μm, and the arrangement interval of the pads varies between 150 μm and 200 μm depending on the location. It is good. The shape of the flip chip connecting surface via electrode provided on the surface of the multilayer ceramic substrate facing the semiconductor is approximately circular with a diameter of 100 μm, and the arrangement interval of the surface via electrodes is made to match that of the semiconductor product to be mounted. Passive components are ceramic chip capacitors and chip resistors, and two types of 1 × 0.5 mm and 0.6 × 0.3 mm are used.

  The multilayer ceramic substrate was produced as follows. The production of the low-temperature sinterable ceramic material and the production of the ceramic green sheet are the same as those described above. Then, via holes are provided in the first ceramic green sheet which is located on the outermost surface side of the unsintered multilayer ceramic body. In the process of forming the via holes, the semiconductor component is mounted when the upper surface component is mounted. Via portions having a diameter of 60 μm are processed in the portions to be processed, and via processing having a diameter of 100 μm is performed in the portions where the chip capacitors and the chip resistors are mounted.

  When these via holes are formed by laser processing, first, via processing with a diameter of φ100 μm is performed, and then optical components such as a collimator inside the laser processing apparatus, and processing conditions such as pulse width and number of shots are changed to φ60 μm. The via processing may be performed. Note that the order in which φ100 μm or φ60 μm is processed first does not matter. In this way, via holes having different diameters are mixed in the first ceramic green sheet.

  Next, using a screen and a squeegee, a silver paste is printed and filled in the via holes. The conductor printing process is performed in multiple steps. First, a via processing with a diameter of 60 μm on which a semiconductor component is mounted has a conductor paste with an Ag content of 80 mass% and a Pd content of 0.1 mass% (a paste with relatively large volume shrinkage during sintering). ) Is used for via filling printing. After this conductor paste was dried, the via paste having a diameter of φ100 μm on which the chip capacitor and the chip resistor were mounted had an Ag content of 90% by mass and a Pd content of 0% by mass (during sintering) In addition, via filling printing is performed using a paste having a relatively small volume shrinkage, and a wiring pattern on the surface is also printed.

  Next, the 2nd ceramic green sheet laminated | stacked adjacent to the 1st ceramic green sheet of a non-sintered multilayer ceramic body is produced. Also in the second ceramic green sheet, the via hole is formed by laser processing as in the first ceramic green sheet. However, since the second ceramic green sheet is used for the second and subsequent ceramic green sheets, the diameter of the via hole processing is not necessarily changed depending on whether the component mounted on the upper surface is a semiconductor component, a chip capacitor or a chip resistor. It is not necessary. That is, via holes having only one type of diameter may be used without mixing via holes having different diameters.

  That is, after the second ceramic green sheet (referred to as the second and subsequent ceramic green sheets; the same applies hereinafter), the pitch can often be gradually increased by rearranging the wiring. Since fine vias are not necessarily required, the via processing diameters can be as large as those of φ100 μm and easy to manufacture. Actually, the number of ceramic green sheets from which such fine vias are not required depends on the design of individual components and the multilayer ceramic substrate.

  For the printing on the second ceramic green sheet, via filling printing is performed using a conductor paste having an Ag content of 90% by mass and a Pd content of 0% by mass. Also, the wiring routing pattern may be printed at the time of this printing. Thereafter, via hole processing and conductor printing are similarly performed on the third and subsequent ceramic green sheets.

Next, as in the above embodiment, the side of the first ceramic green sheet that is to be positioned on the outermost surface side of the unsintered multilayer ceramic body is set on the fixing film, and the mold is Press and press with a predetermined pressure, temperature and time. For example, the pressure is 1 to 5 MPa (10 to 50 kgf / cm ² ), the temperature is 30 to 60 ° C., and the time is 3 to 15 seconds. The upper and lower molds for thermocompression bonding may have a simple flat plate shape with a built-in heater. After the press bonding, the ceramic green sheet carrier film is peeled off. At this time, the green sheet is fixed to the fixing film and is not peeled off together with the carrier film.

  The second ceramic green sheet and the subsequent press-bonding and lamination are performed in the same manner as in the above embodiment to obtain an unsintered multilayer ceramic body.

  Thereafter, the above-mentioned unsintered multilayer ceramic body is appropriately formed with a shallow groove for division or cut into a size that is easy to handle, sintered at 900 ° C. for about 2 hours, Plating is performed in the same manner as in the above embodiment.

When the via portion of the sintered multilayer ceramic body thus formed was observed and measured, the depth d to the surface layer via electrode of the portion on which the semiconductor component was mounted was −1 μm and the filling property was good. The shear strength measured by mounting a solder ball having a diameter of 125 μm was 0.0069 gf / μm ² , and the pull strength measured by mounting a solder ball having a diameter of 500 μm was 0.0496 gf / μm ² . This multilayer ceramic substrate is divided into individual pieces, soldered to a test printed circuit board, and then placed in a constant temperature and humidity chamber to + 4V in a path according to the original electrical design in an environment of 85 degrees and 85% RH. A “high temperature and high humidity energization test” was performed in which a direct current voltage was applied. During the entire test time of 1000 hours, there was no insulation failure and no appearance abnormality. When assembling semiconductor components as electronic components, the surface layer terminal electrodes are almost flush with the surface of the ceramic substrate, so the solder balls do not deviate from the center of the pads, and the self-alignment effect is exhibited, allowing accurate assembly. . In addition, since the solder ball mounting method was used instead of the solder paste printing method for semiconductor mounting, the soldered state after assembly was in a good connection state with almost no void-like nest.

  Another aspect for manufacturing a multilayer ceramic substrate for use in the electronic component according to the present embodiment will be described. In this embodiment, the production of the ceramic material that can be sintered at a low temperature, the generation of the ceramic green sheet, and the formation of the via hole are the same as those described above, and the silver paste is printed and filled into the via hole using a screen and a squeegee. Sometimes, the conductor printing process is divided into a plurality of times, but the process of filling the conductor paste with respect to the portion where the passive component is arranged is different.

  In this embodiment, first, in the conductor paste, both the part processed with vias with a diameter of φ60 μm on which semiconductor components are mounted and the part with vias processed with a diameter of φ100 μm on which passive components such as chip capacitors and chip resistors are mounted. Via filling printing using an Ag content of 80% by mass and a Pd content of 0.1% by mass (with a relatively large volume shrinkage during sintering), and drying this conductor paste, a chip capacitor In the conductive paste, Ag content is 90% by mass and Pd content is 0% by mass in the area where the passive component is mounted, such as the chip resistance and the area where the passive components are mounted (surface sintering is relatively low The second conductor printing is performed using a small one. In this way, a surface layer pad electrode is formed by printing a double conductor on a portion where a passive component such as a chip capacitor or a chip resistor is mounted. The surface layer pad electrode portion does not necessarily have a clear two-layer structure, but includes a portion in which the above-described two types of conductor paste are mixed, and can be said to be a conductor structure having a concentration gradient.

  The manufacturing method after the second ceramic green sheet and the conductive paste used are the same as those described in the previous embodiment. In addition, pressure bonding and lamination, groove formation for division, sintering and plating are performed in the same manner as in the previous embodiment.

  When the via portion of the sintered multilayer ceramic body thus formed was observed and measured, the depth d to the surface layer via electrode of the portion on which the semiconductor component was mounted was −1 μm and the filling property was good. Since the conductor on which the chip capacitor and the chip resistor were mounted was printed twice, it was raised in a convex direction in the positive direction from the surface of the ceramic multilayer substrate.

  This multilayer ceramic substrate is divided into individual pieces, soldered to a test printed circuit board, placed in a constant temperature and humidity chamber, and + 4V direct current is routed to the path according to the original electrical design in an environment of 85 degrees and 85% RH. A “high temperature and high humidity energization test” in which a voltage was applied was performed. During the entire test time of 1000 hours, there was no insulation failure and no appearance abnormality. Also, when assembling as an electronic component by mounting a semiconductor component, the surface layer terminal electrode is substantially flush with the surface of the ceramic substrate, so that the solder ball does not deviate from the center of the pad, and the self-alignment effect is exhibited, so that it can be assembled accurately. did it. Further, since the solder ball mounting method was used instead of the solder paste printing method for semiconductor mounting, the soldered state after assembly was a good connection state with almost no void-like nest.

  FIG. 6 shows an example of a cross section of the multilayer ceramic substrate 10 of the present embodiment on which electronic components are mounted. A large number of component-mounting pad electrodes are formed as conductor patterns on the upper surface of the multilayer ceramic substrate 10 of the present embodiment. Passive components 22 such as resistors and capacitors (chip components in FIG. 4) are formed on these electrodes. An active component 21 made of a semiconductor chip such as an IC is mounted. The multilayer ceramic substrate includes an outermost substrate layer and each substrate layer laminated thereon, and internal wiring such as an inductor, a transmission line, a capacitor, and a ground electrode is formed on each substrate layer by a conductor pattern, and these are connected to vias. The target circuit wiring is configured by connecting to each other by wiring. A pad electrode for connecting the substrate to the mother substrate is appropriately formed on the lowermost substrate, and the mounting density on the upper surface side is usually high.

  In this multilayer ceramic substrate, the active component 21 is surface-mounted by a BGA connection 212 using a solder ball, and the passive component 22 is an LGA connection 222 using a solder paste on the pad electrode surface. At this time, the diameter of the via hole 211 for BGA connection is smaller than the diameter of the via hole 221 for LGA connection with respect to the diameter of the via hole in which the surface layer terminal electrode is formed. As described above, for the BGA connection having a relatively small via hole diameter (the electrode on which the IC chip 21 of FIG. 4 is mounted), the end face of the surface via electrode is inside the via hole provided in the outermost ceramic substrate layer. The surface of the metal plating layer deposited on the end surface of the surface layer via electrode is in a position recessed from the surface of the outermost ceramic substrate layer, and the thickness of the metal plating layer is equal to the surface of the outermost ceramic substrate layer. It is formed so that it protrudes less than or less than the surface of the outermost ceramic substrate layer. On the other hand, in the LGA connection 222 using a round or square pad electrode 223 having a lower density than the BGA connection 212, the height of the surface of the metal plating layer is higher than the height of the surface of the metal plating layer for BGA connection. It is set higher than this. Therefore, the passive component 22 can be easily connected by using the solder paste on the pad electrode surface.

  As described above, the via holes provided in the outermost ceramic substrate layer are mixed in size, but among them, the LGA connection uses a relatively large via hole. In the first place, since the bonding strength between the electrode formed in the relatively large via hole and the electronic component is relatively large, the conventional electrode may be formed. However, in the case of the BGA connection by the relatively small via hole, the surface layer is used. Metal plating in which the end face of the via electrode is inside the via hole provided in the outermost ceramic substrate layer and is recessed from the surface of the outermost ceramic substrate layer, and is deposited on the end face of the surface via electrode By forming the surface of the layer so that it is almost flush with the surface of the outermost ceramic substrate layer or recessed from the surface of the outermost ceramic substrate layer, the connection strength is enhanced and the processing efficiency is increased. Can be improved.

It is a flowchart showing the example of the manufacturing method of the multilayer ceramic substrate which concerns on embodiment of this invention. It is explanatory drawing showing the example of the cross section in the manufacture process of the multilayer ceramic substrate which concerns on embodiment of this invention. It is sectional drawing showing the example of the multilayer ceramic substrate which concerns on embodiment of this invention. It is explanatory drawing showing the example of the via hole processing of the ceramic green sheet in the manufacture process of the multilayer ceramic substrate which concerns on embodiment of this invention. It is explanatory drawing showing the example from the via hole process of ceramic green sheet to peeling of a carrier film in the manufacture process of the multilayer ceramic substrate which concerns on embodiment of this invention. It is explanatory drawing showing an example of the cross section of the multilayer ceramic substrate 10 of this Embodiment carrying the electronic component which concerns on embodiment of this invention. It is explanatory drawing showing the example which the malfunction produced in the via hole processing of the ceramic green sheet in the manufacture process of the multilayer ceramic substrate which concerns on embodiment of this invention. It is sectional drawing showing the example of the conventional multilayer ceramic substrate.

DESCRIPTION OF SYMBOLS 1 Ceramic substrate layer, 2 Surface layer via electrode, 3 Metal plating layer, 4 Surface layer terminal electrode, 5 Carrier film, 6 Fixing film, 7 Lower metal mold, 11, 211, 221 Via hole, 12 Via wiring, 21 Active component ( Element), 22 passive components (element), 212 BGA connection, 222 LGA connection

Claims (5)

A multilayer ceramic substrate in which a plurality of ceramic substrate layers are laminated,
Tapered via holes that narrow toward the outermost surface are provided on the uppermost and lowermost ceramic substrate layers,
A surface layer terminal electrode comprising a surface layer via electrode provided in the via hole and a metal plating layer deposited on the end face thereof;
Via wiring connecting the surface layer terminal electrode and wiring on an internal ceramic substrate layer;
Including
The surface layer via electrode of the outermost surface ceramic substrate layer on at least one of the front and back surfaces has a surface inside the via hole provided in the outermost surface ceramic substrate layer, and is recessed from the surface of the outermost surface ceramic substrate layer. In the position
Surface of the metal plating layer deposited on the end surface of the surface layer via electrode, the to not substantially the same plane as the surface of the outermost ceramic substrate layer, Ri position near recessed from the ceramic substrate layer surface of the outermost surface, wherein The boundary surface in contact with the inner wall of the via hole of the metal plating layer coincides with no gap, and when the boundary surface is viewed in the cross section in the depth direction, the contact length (L) of the boundary surface is 2 μm or more. A multilayer ceramic substrate characterized by the above. Via holes formed in the ceramic substrate layers other than the outermost ceramic substrate layer surface of the front and back, the multilayer ceramic according to claim 1, characterized in that it is formed in a tapered shape spreading towards the outermost surface of the one side substrate. The diameter of the tapered via hole that narrows toward the outermost surface of at least one of the front and back outermost ceramic substrate layers is provided in a ceramic substrate layer other than the outermost ceramic substrate layer of the front and back surfaces. multilayer ceramic substrate according to claim 1 or 2, characterized in that less than the diameter of the via hole. The length of the tapered via hole narrowed toward the outermost surface of at least one of the front and back outermost ceramic substrate layers is provided in a ceramic substrate layer other than the outermost ceramic substrate layer of the front and back surfaces. The multilayer ceramic substrate according to claim 1 or 2 , wherein the length is shorter than the length of the via hole. Using a multilayer ceramic substrate according to any one of claims 1-4, relative to the metal plating layer, electronic component and wherein the mounting the surface mounting component using solder balls.

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