JP2004235347A - Insulating ceramics and multilayer ceramic substrate using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulating ceramics whose specific resistance is 10<SP>11</SP>Ωcm or higher even in the case the thickness is 100 μm or less, and to provide a multilayer ceramic substrate using the same. <P>SOLUTION: A multilayer ceramic substrate 1 comprises an insulating board 2 where a plurality of insulating layers 2a-2f are laminated, and a wiring circuit layer 3 arranged on the surface of the insulating board 2 and among the insulting layers 2a-2f. At least one layer, or the insulating layer 2a, between the insulating layers 2a and 2f comprises a thin layer of 100 μm or less. The maximum diameter of the crystallite constituting the insulating layers 2a and 2f comprising the thin layer is set to be 5 μm or less, a void area rate to be 3% or less, and maximum void bore to be 5 μm or less, so that the specific resistance of the insulating layer is 10<SP>11</SP>Ωcm or higher, resulting in preventing occurrence of failure at plating. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【００３５】
表１の結果より、各絶縁層の結晶子の最大径が５μｍ以下であり、かつその絶縁層のボイド面積率が３％以下で、最大ボイド径が５μｍ以下の絶縁性セラミックスからなる場合、１００μｍ厚み以下、特に５０μｍ以下の薄層を形成した場合でも比抵抗が１０^１１Ω・ｃｍ以上の高い絶縁性を示した。
【００３６】
【発明の効果】
以上詳述したとおり、本発明によれば、結晶子の最大径が５μｍ以下であり、かつその絶縁層のボイド面積率が３％以下で、最大ボイド径が５μｍ以下となる絶縁性セラミックスを厚み１００μｍ以下の薄層を形成した場合においても比抵抗が１０^１１Ω・ｃｍ以上の高い絶縁性を有することから、多層セラミック基板として高い信頼性を付与できる。
【図面の簡単な説明】
【図１】本発明による多層セラミック基板の一例を示す概略断面図である。
【符号の説明】
１ 多層セラミック基板
２ 絶縁基板
２ａ〜２ｆ 絶縁層
３ 配線回路層
４ ビアホール導体
５ 半導体素子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer ceramic substrate suitable for an insulating ceramic, a package for housing a semiconductor element, and the like.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high-density, small-sized semiconductor devices such as ICs and LSIs, and packages for mounting semiconductor devices such as LSIs, and wiring boards applied to hybrid integrated circuit devices on which various electronic components are mounted have been developed. Lightening is required. In response to such demands for higher density, smaller size and lighter weight, the thickness of each insulator constituting the multilayer ceramic wiring board has shifted to a thinner layer as the height has been reduced, particularly from the viewpoint of reducing the height of the board. Specifically, it is necessary to be configured with a thickness of 20 μm to 100 μm (for example, see Patent Documents 1, 2, and 3).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-111218 [Patent Document 2]
JP 10-93238 A [Patent Document 3]
JP-A-7-154073
[Problems to be solved by the invention]
However, when the insulating layer is thin, if the denseness of the insulating layer is insufficient, the specific resistance of the insulating layer becomes less than 10 ¹¹ Ω · cm, and the two wiring conductor layers sandwiching the thin insulating layer. As a result, there is a problem that the short circuit and the mutual interference effect increase. In particular, in the case where the thin insulating layer is disposed on the surface of the wiring board and a plating layer is formed by adhesion, if the insulating layer has insufficient tightness, the plating film adheres to defective portions such as voids. However, the above-mentioned disadvantages become significant.
[0005]
An object of the present invention is to provide an insulating ceramic having a specific resistance of 10 ¹¹ Ω · cm or more even when the thickness is 100 μm or less, and a multilayer ceramic substrate using the same.
[0006]
[Means for Solving the Problems]
The present inventors have conducted intensive studies on the above problems, and as a result, in a thin ceramic layer having a thickness of the insulating layer of 100 μm or less, the maximum diameter of crystallites constituting the insulating layer is 5 μm or less, and When the void area ratio of the insulating layer is 3% or less and the maximum void diameter is 5 μm or less, the specific resistance of the insulating layer can be 10 ¹¹ Ω · cm or more, and the above object can be achieved. Invented the invention.
[0007]
That is, the insulating ceramic of the present invention is formed of a thin layer having a thickness of 100 μm or less, the maximum diameter of the ceramic crystallite constituting the insulating layer is 5 μm or less, and the void area ratio of the insulating layer is 3% or less. , The maximum void diameter is 5 μm or less, and the specific resistance is 10 ¹¹ Ω · cm or more.
[0008]
Further, the multilayer ceramic substrate of the present invention includes an insulating substrate formed by laminating a plurality of insulating layers, and a wiring circuit layer disposed between the insulating substrate surface and the insulating layer. At least one of the insulating layers is formed of a thin layer having a thickness of 100 μm or less, and the maximum diameter of crystallites constituting the insulating layer made of the thin layer is 5 μm or less, the void area ratio is 3% or less, and the maximum void diameter is 5 μm or less. In particular, the specific resistance of the thin insulating layer is 10 ¹¹ Ω · cm or more.
[0009]
Further, it is suitable when a thin insulating layer having a thickness of 100 μm or less is formed on the outermost surface, and further when a plating layer is formed on the surface of a wiring circuit layer provided on the surface. It is suitable.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the multilayer ceramic substrate of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the ceramic substrate of the present invention. According to the cross-sectional view of FIG. 1, the multilayer ceramic substrate 1 includes an insulating substrate 2 composed of a laminate formed by laminating a plurality of ceramic insulating layers 2a to 2f, the insulating substrate 2 between the insulating layers 2a to 2f, and the insulating substrate 2 The wiring circuit layer 3 made of a metal conductor having a thickness of about 5 to 20 μm is formed on the surface. Also, via-hole conductors 4 having a diameter of 80 to 200 μm are formed so as to penetrate through the thickness direction of each of the ceramic insulating layers 2 a to 2 f, thereby connecting the wiring circuit layers 3 to form a predetermined circuit. Is done.
[0011]
The multilayer ceramic substrate 1 of the present invention is formed of a sintered body obtained by firing ceramic powder, glass powder, or a mixture of glass powder and ceramic powder. In particular, in order to realize low-temperature firing, it is desirable to fire a composition containing 50% by mass or more, particularly 55% by mass or more, of glass powder having an average particle size of 1 μm or less.
[0012]
The glass powder used contains at least SiO ₂ and at least one of Al ₂ O ₃ , B ₂ O ₃ , ZnO, PbO, an alkaline earth metal oxide, and an alkali metal oxide. For example, borosilicate such as SiO ₂ —B ₂ O ₃ system, SiO ₂ —B ₂ O ₃ —Al ₂ O ₃ system—MO system (where M represents Ca, Sr, Mg, Ba or Zn) Examples include acid glass, alkali silicate glass, Ba-based glass, Pb-based glass, and Bi-based glass. These glasses are also amorphous glasses by calcination, and lithium silicate, quartz, cristobalite, cordierite, mullite, anorthite, Celsian, diopside, spinel, garde Those which precipitate at least one kind of crystals of knight, willemite, dolomite, petalite and substituted derivatives thereof are used.
[0013]
On the other hand, as the ceramic powder, at least one selected from the group consisting of Al ₂ O ₃ , ZrO ₂ , mullite, forsterite, enstatite, spinel, and magnesia is used, and these are used in combination with the glass powder. The strength and characteristics of the sintered body can be improved. In this case, the ceramic powder is desirably contained at a ratio of 10 to 90% by mass with respect to the glass.
[0014]
On the other hand, the wiring circuit layer 2 and the via hole conductor 4 are formed of at least one selected from the group consisting of W, Mo, Mo, Cu, and Ag. In particular, it is desirable to use Cu or Ag in consideration of the fact that it is formed by simultaneously firing with a ceramic substrate at a low temperature for low resistance.
[0015]
According to the present invention, among the plurality of ceramic insulating layers 2a to 2f constituting the insulating substrate 2 in the above-described multilayer ceramic substrate, the multilayer ceramic substrate has an insulating layer composed of a thin layer having a thickness of 100 μm or less. In the example of FIG. 1, a thin layer having a thickness of 100 μm or less is formed on the outermost surface and the lowermost surface.
[0016]
According to the present invention, as the insulating ceramics constituting the ceramic insulating layers 2a and 2f forming such a thin layer, the maximum diameter of the ceramic crystallite constituting the insulating layer is 5 μm or less, particularly 3 μm or less, and The insulating layer has a void area ratio of 3% or less, particularly 2% or less, and a maximum void diameter of 5 μm or less, particularly 3 μm or less.
[0017]
The reason that each factor was controlled in the above range is that the maximum diameter of the ceramic crystallites constituting the insulating layers 2a and 2b and the maximum void diameter generated tend to be substantially the same. For example, the maximum diameter of the crystallite is 5 μm. , The maximum void diameter is also approximately 5 μm, and if the maximum diameter or the maximum void diameter of the ceramic crystallite is larger than 5 μm, the effective volume of the insulating layer is reduced in the insulator having a thickness of 100 μm or less, and the specific resistance is reduced by 10 μm. ^{It is} less than ¹¹ Ω · cm. Similarly, even when the void area ratio of the insulating layer is larger than 3%, the effective volume of the insulating layer is reduced, and the specific resistance is less than 10 ¹¹ Ω · cm.
[0018]
In addition, the insulating ceramic having such properties can achieve a specific resistance of 10 ¹¹ Ω · cm or more at room temperature even when the thickness is 100 μm or less, particularly 50 μm or less, and even 30 μm or less.
[0019]
Next, a method of manufacturing a wiring board according to the present invention will be described in the case where the above glass-ceramic material is used as a ceramic insulating substrate material. First, a glass-ceramic composition is prepared by mixing the above-mentioned ceramic component with the above-mentioned crystallized glass or amorphous glass, and after adding an organic binder and the like to the mixture, doctor blade method, rolling method, press method A green sheet having a thickness of about 20 to 500 [mu] m is formed by forming the sheet into a sheet shape.
[0020]
Next, a through hole having a diameter of 80 to 200 μm is formed in the green sheet by laser, micro drill, punching, or the like, and the inside thereof is filled with a conductive paste for via holes containing copper or silver as a main component. The conductive paste for via holes is formed by homogeneously mixing an organic binder such as an acrylic resin and an organic solvent such as terpineol and dibutyl phthalate, in addition to the metal component.
[0021]
The organic binder is mixed at a ratio of 0.5 to 15.0 parts by mass with respect to 100 parts by mass of the metal component, and the organic solvent is mixed at a ratio of 5 to 100 parts by mass with respect to 100 parts by mass of the solid component and the organic binder. It is desirable. Note that less than 20% by mass of a ceramic filler, a glass component, or the like may be added to the via conductor paste.
[0022]
Next, a wiring circuit layer is formed on the surface of the green sheet by using a pattern conductive paste by a screen printing method. The patterned conductor paste is formed by homogeneously mixing an organic binder such as an acrylic resin and an organic solvent such as terpineol and dibutyl phthalate, in addition to the metal component. The organic binder is mixed at a ratio of 0.5 to 15.0 parts by mass with respect to 100 parts by mass of the metal component, and the organic solvent is mixed at a ratio of 5 to 100 parts by mass with respect to 100 parts by mass of the solid component and the organic binder. It is desirable to be done. Note that less than 20% by mass of a ceramic filler, a glass component, or the like may be added to the conductor paste for a pattern.
[0023]
Thereafter, a plurality of green sheets obtained in the same manner are laminated and pressed to form a laminate. Green sheets are laminated by applying heat and pressure to the stacked green sheets and thermocompression bonding, or by applying an adhesive consisting of an organic binder, plasticizer, solvent, etc. between the sheets and thermocompression bonding. It is possible.
[0024]
Next, this laminate is subjected to heat treatment in a nitrogen atmosphere at 100 to 850 ° C., particularly 400 to 750 ° C. to decompose and remove organic components and the like in the green sheet and the conductor paste. Co-firing in atmosphere. If the cooling rate of this firing is too fast, cracks occur due to the difference in thermal expansion between the ceramic substrate and the wiring circuit layer. Therefore, the cooling rate is desirably 400 ° C./hr or less. During firing, a load may be applied by placing a weight on the upper surface of the laminate to prevent warpage. An appropriate load is 50 Pa to 1 MPa.
[0025]
In addition, for controlling the crystal particles and voids of the ceramic insulating layer, the average particle size of the glass powder to be used and the average particle size of the ceramic filler powder are finely controlled, and in particular, each is 1.2 μm or less, particularly 1 μm or less. Use powder. Further, it is necessary to control the glass content to 50% by mass or more, particularly 55% by mass or more. In addition, by firing at the lowest possible firing temperature, a substrate having a glass ceramic insulating layer with a fine structure can be manufactured.
[0026]
The maximum diameter of crystallites in each insulating layer of the obtained multilayer ceramic substrate is 5 μm or less, the void area ratio of the insulating layer is 3% or less, and the maximum void diameter is 5 μm or less. It is possible to have a high insulating property with a resistance of 10 ¹¹ Ω · cm or more.
[0027]
【Example】
The ceramic wiring board of the present invention is evaluated based on one example.
First, _SiO 2: 44 _wt%, Al ₂ O 3: 28 wt%, MgO: 11 wt%, ZnO: 7 _{wt%, B 2} O 3: average particle size of 10% by weight of the composition 0.8 4.8 μm glass and Al ₂ O ₃ having an average particle size of 0.8 to 4.6 μm as a ceramic filler component are weighed so that the mass ratio of glass: Al ₂ O ₃ becomes 70:30, and the glass ceramic is weighed. A composition was made. Using a slurry prepared by adding an acrylic resin as a binder, DBP (dibutyl phthalate) as a plasticizer, and toluene and isopropyl alcohol as a solvent, a green sheet having a thickness of 25 to 125 μm was prepared by a doctor blade method. .
[0028]
Next, 1 part by mass of alumina powder and 10 parts by mass of glass powder were weighed with respect to 100 parts by mass of Cu powder, and an acrylic resin as an organic binder and DBP as a solvent were added thereto and kneaded, and a paste sample for via-hole conductor was prepared. Produced. The amount of the organic binder in the via-hole paste sample was 2.0 parts by mass with respect to the Cu powder, and the solvent was added at a ratio of 40 parts by mass with respect to the solid component and the organic binder. This Cu paste was filled into via holes formed at predetermined locations on the green sheet.
[0029]
Further, 1 part by mass of alumina powder and 5 parts by mass of glass powder were weighed with respect to 100 parts by mass of Cu powder, and an acrylic resin as an organic binder and DBP as a solvent were added and kneaded to prepare a Cu paste sample for a pattern. did. The amount of the organic binder was 3.0 parts by mass with respect to the main component, and the solvent was added at a ratio of 50 parts by mass with respect to the solid component and the organic binder. A wiring circuit layer was formed by screen printing on the green sheet filled with the obtained Cu paste and the via ink. The printed thickness of the wiring layer at this time was 10 to 30 μm. Thereafter, the green sheets on which the wiring circuits were formed were laminated in the configuration shown in FIG. 1 and were laminated under pressure at 50 ° C. and 5 MPa to produce a laminate.
[0030]
Next, the laminate is placed on an Al ₂ O ₃ setter and calcined at 750 ° C. in a nitrogen atmosphere to decompose and remove organic components such as an organic binder, and then at 900 ° C. in a nitrogen atmosphere. Baking was performed for one hour to produce a wiring substrate. Thereafter, the substrate was plated with Ni / Au. The plating thickness at this time was 3 μm and 0.5 μm, respectively.
[0031]
As a result of identifying the precipitated crystal phase of the obtained multilayer ceramic substrate by X-ray diffraction measurement, garnite and Al ₂ O ₃ crystals were recognized.
[0032]
The insulating layer of the obtained multilayer ceramic substrate was evaluated. The size of crystallites constituting the ceramic insulating layer was calculated by an intercept method from a scanning electron microscope (SEM) photograph of a mirror-polished insulator cross section. The void area ratio and the maximum void diameter were similarly calculated from the scanning electron microscope (SEM) photograph of the void portion using an image analyzer. Table 1 shows the results.
[0033]
Further, using the obtained multilayer ceramic substrate, the insulation resistance between the surface wiring circuit layer plated with metal and the internal wiring circuit layer was measured. The measurement was performed by applying a voltage of 10 V for 20 seconds between the wiring circuit layers on the back surface through the via conductors and the internal wiring circuit layers from the front wiring circuit layer using an insulated meter. Table 1 shows the results.
[0034]
[Table 1]

[0035]
From the results shown in Table 1, when the maximum diameter of crystallites of each insulating layer is 5 μm or less, the void area ratio of the insulating layer is 3% or less, and when the insulating layer is made of insulating ceramics having a maximum void diameter of 5 μm or less, 100 μm Even when a thin layer having a thickness of not more than 50 μm or less was formed, a high insulating property having a specific resistance of 10 ¹¹ Ω · cm or more was exhibited.
[0036]
【The invention's effect】
As described in detail above, according to the present invention, the insulating ceramic having a maximum crystallite diameter of 5 μm or less, a void area ratio of the insulating layer of 3% or less, and a maximum void diameter of 5 μm or less is used. Even when a thin layer having a thickness of 100 μm or less is formed, the multilayer ceramic substrate has high insulation properties with a specific resistance of 10 ¹¹ Ω · cm or more.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing an example of a multilayer ceramic substrate according to the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 multilayer ceramic substrate 2 insulating substrates 2 a to 2 f insulating layer 3 wiring circuit layer 4 via-hole conductor 5 semiconductor element

Claims (6)

It is made of a thin layer having a thickness of 100 μm or less, the maximum diameter of ceramic crystallites constituting the insulating layer is 5 μm or less, the void area ratio of the insulating layer is 3% or less, and the maximum void diameter is 5 μm or less. An insulating ceramic characterized by the following. 2. The insulating ceramic according to claim 1, wherein the specific resistance is 10 ¹¹ Ω · cm or more. A multilayer ceramic substrate comprising: an insulating substrate formed by laminating a plurality of insulating layers; and a wiring circuit layer provided between the insulating substrate surface and the insulating layers, wherein at least one of the insulating layers is an insulating layer. Has a maximum thickness of 5 μm or less, a void area ratio of 3% or less, and a maximum void diameter of 5 μm or less. Ceramic substrate. Multilayer ceramic substrate according to claim 3, wherein the specific resistance of the insulating layer is 10 ¹¹ Ω · cm or more. The multilayer ceramic substrate according to claim 3 or 4, wherein a thin insulating layer having a thickness of 100 µm or less is formed on the outermost surface. 6. The multilayer ceramic substrate according to claim 1, wherein a plating layer is formed on the surface of the wiring circuit layer provided on the surface.

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