JP2004087989A - Multilayer wiring substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring substrate having proper electrical characteristics, wherein the generation of delaminations and cracks in layers and patterns are restrained, when a wiring layer of high purity such as a copper foil and a glass ceramic green sheet are baked at the same time. <P>SOLUTION: In a multilayer wiring substrate A, an insulation substrate 10 consists of glass ceramic and wiring layers 3, 6 are formed of a metal foil in a surface and/or the inside the insulation substrate 10. In the substrate A, a through-hole 11 is formed in the wiring layer 6, whose wiring area ratio in a layer surface of the wiring layers 3, 6 is 50% or larger, the average pitch of the through-holes 11 to which each is adjacent is 0.1 to 2.0mm and the average maximum diameter of the through-hole 11 is 0.05 to 0.40mm. <P>COPYRIGHT: (C)2004,JPO

Description

【００６９】
表１の結果から明らかなように配線層面内の配線面積比率が５０％以下の試料Ｎｏ．１〜５ではデラミネーション、クラックともに発生せず高い歩留まりで製品が作製できた。一方、配線層面内の配線面積比率が５０％を越える試料Ｎｏ．６〜９ではデラミネーションやクラックが多発し、歩留まりが低下した。
【００７０】
【表２】

【００７１】
表２の結果から明らかなように、貫通孔が無い試料Ｎｏ１０，２６はデラミネーション及びクラックが多発しており、歩留まりは５０％に満たない結果となっており実用的でない。
【００７２】
また、貫通孔ピッチが２．０ｍｍを超える試料Ｎｏ．１８，３４は、貫通孔のない試料Ｎｏ１０，２６と比較すると改善はされているが、試料１００個中のクラック、デラミネーションの発生数が２０を超えているため実用的ではない。
【００７３】
貫通孔ピッチが０．１ｍｍ未満の試料Ｎｏ１１，２７は、導通抵抗が１６ｍΩを超えているため実用的ではない。
【００７４】
貫通孔径の平均を０．０５ｍｍより小さくした試料Ｎｏ．１９，３５では若干数のデラミネーション、クラックが発生していることから、貫通孔径の平均は０．０５ｍｍ以上にすることが必要であった。
【００７５】
また、貫通孔径の平均を０．４０ｍｍより大きくした試料Ｎｏ．２５，４１では基板導通抵抗が１６ｍΩを超えているため、貫通孔径の平均は０．４ｍｍ以下にすることが必要であった。
【００７６】
これに対して本発明の範囲内である試料Ｎｏ１２〜１７，２０〜２４，２８〜３３，３６〜４０，４２〜４４においては、クラック、デラミネーションとも皆無か非常に少なく、電気特性の問題も無いサンプルが得られた。
【００７７】
配線層の厚さが２５，３５μｍの試料Ｎｏ．４３，４４についてみると、特性上全く問題の無い結果が得られたが、配線層の厚さが３５μｍの試料Ｎｏ．４４では貫通孔の内、０．０５ｍｍ以下の貫通孔でエッチング不良が発生したため、配線層の厚みは２５μｍ以下が望ましい。
【００７８】
【発明の効果】
以上詳述したとおり、本発明によれば、ガラスセラミックからなる絶縁基板と、該絶縁基板の表面及び／又は内部に金属箔で配線層を形成した多層配線基板において、該配線層の層面内における配線面積比率が５０％以上の配線層に複数の貫通孔を形成し、それぞれ隣接する該貫通孔のピッチを平均０．１〜２．０ｍｍとし、かつ貫通孔の最大径の平均を０．０５〜０．４０ｍｍすることで、基板内部にクラック、デラミネーション等の発生が抑制され、電気特性に優れた多層配線基板を容易に得ることができる。
【図面の簡単な説明】
【図１】本発明の多層配線基板を説明するための概略断面図である。
【図２】本発明の多層配線基板における貫通孔を形成した配線層を上からみた該略図である。
【図３】本発明における多層配線基板の製造方法を説明するための工程図である。
【符号の説明】
１　　セラミックグリーンシート
２　　ビアホール導体
３　　配線層
５　　樹脂フィルム
６　　配線層
８　　拘束シート
１０　絶縁基板
１１　貫通孔
Ａ　　多層配線基板
Ｂ　　電子部品
ａ，ａ１〜９，ｂ，ｂ１〜６　　貫通孔[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer wiring board suitable for a multilayer wiring board, a package for accommodating a semiconductor element, and the like.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a multilayer ceramic wiring board capable of relatively high-density wiring has been frequently used as a wiring board, for example, as a multilayer wiring board used for a package containing a semiconductor element. This multilayer ceramic wiring board is composed of an insulating substrate such as alumina or glass ceramic, and a wiring conductor formed on the surface thereof and made of a metal such as W, Mo, Cu, or Ag. A cavity is formed in the portion, the semiconductor element is housed in the cavity, and the cavity is hermetically sealed by the lid.
[0003]
2. Description of the Related Art In recent years, high-density, low-priced wiring boards have been developed for semiconductor element storage packages for mounting semiconductor elements such as ICs and LSIs, and for hybrid integrated circuit devices on which various electronic components are mounted. Since resistance, small size and light weight are required, a low dielectric constant is obtained as compared with an alumina ceramic material, and a low resistance metal such as copper can be used as a wiring layer. So-called glass-ceramic wiring boards are receiving more attention.
[0004]
In such a glass ceramic wiring board, as a technique for forming a wiring layer, a technique of printing a metallized paste mainly containing a wiring conductor made of a metal such as Cu or Ag on an insulating substrate by a screen printing method or the like is used. I have. However, when such a method is used, it is difficult to form a wiring having a wiring width of 100 μm or less, and this is a factor which hinders achievement of further higher density, smaller size and lighter weight which will be required in the future. Also, regarding the electric resistance, there is a problem that many voids exist in the wiring layer because the wiring layer is formed by the paste, and it is difficult to reduce the resistance.
[0005]
As a method of solving this problem, a method of forming a wiring layer in a glass ceramic green sheet with an etched metal foil is known (Japanese Patent Application Laid-Open No. 63-99596).
[0006]
By forming the wiring layer with a metal foil, the electric resistance can be reduced to about 60 to 70% as compared with the case where a conventional printing method is used. Further, by etching the metal foil, the wiring width can be reduced to 100 μm or less. It becomes possible.
[0007]
[Problems to be solved by the invention]
However, when a large-area wiring layer such as a ground layer in a multilayer wiring board is formed of metal foil, the decomposition gas of the binder generated during firing is difficult to escape to the outside of the system. And cracks are generated, and the yield is reduced.
[0008]
As a countermeasure, a method of making a structure of a large-area wiring layer such as a ground layer into a mesh shape is generally used.
However, when a large number of through-holes such as a mesh structure exist in the ground layer, the electric resistance of the wiring board increases, and there is a problem that the board performance is affected.
[0009]
An object of the present invention is to provide a high-purity, low-resistance wiring layer formed of a copper foil or the like and a ceramic green sheet at the same time, without causing delamination or cracks between the layers or patterns, and furthermore, the It is to provide a multilayer wiring board having excellent characteristics.
[0010]
[Means for Solving the Problems]
The present inventors have studied the above problem and found that by forming through-holes having an average pitch and a through-hole diameter in a wiring layer having an area ratio of more than 50% in a layer plane, delamination or cracking between layers or patterns can be achieved. It has been found that a multilayer wiring board which does not cause any other problems and has excellent electrical characteristics can be obtained.
[0011]
That is, in the multilayer wiring board of the present invention, in an insulating substrate made of glass ceramic and a multilayer wiring board having a wiring layer formed of metal foil on the surface and / or inside of the insulating substrate, the area ratio of the wiring layer in the layer plane Are formed in the wiring layer exceeding 50%, the pitch of the adjacent through holes is 0.1 to 2.0 mm on average, and the average of the maximum diameter of the through holes is 0.05 to 0.40 mm. It is characterized by having done.
[0012]
In addition, copper foil is desirable as a material of the metal foil so that the metal foil does not cause insulation failure such as migration.If the thickness of the metal foil exceeds 25 μm, etching failure may occur. The thickness of the metal foil is desirably 25 μm or less in order to form a fine circuit because the hole shape becomes tapered or the like.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a description will be given based on a schematic cross-sectional view showing an example of the multilayer wiring board of the present invention.
[0014]
According to the multilayer wiring board A of FIG. 1, the insulating substrate 10 is composed of a laminated body formed by laminating a plurality of glass ceramic insulating layers 10a to 10d having a thickness of 50 to 250 μm. On the surface of the substrate 10, a general wiring layer 3 made of a high-purity metal conductor having a thickness of about 3 to 25 μm and a wiring layer 6 forming a ground layer are formed by adhesion.
[0015]
Further, via-hole conductors 2 having a diameter of 50 to 200 μm are formed so as to penetrate through the thickness direction of each of the glass ceramic insulating layers 10 a to 10 d, thereby connecting the wiring layer 3 and the wiring layer 6 to form a predetermined circuit. The network to achieve is formed. Electronic components B such as semiconductor elements are mounted and mounted on the surface of the wiring layer 3.
[0016]
The wiring layer 3 on the surface is used as a pad for mounting various electronic components B such as an IC chip, or as a conductive film for shielding, and further as a terminal electrode connected to an external circuit. Is bonded to the wiring layer 3 via a solder, a conductive adhesive or the like.
[0017]
Although not shown, a thick-film resistor film such as tantalum silicide or molybdenum silicide, a wiring protection film, or the like may be further formed on the surface of the multilayer wiring board A as necessary.
[0018]
According to the present invention, a through-hole 11 as shown in FIG. 2 is formed in the wiring layer 6 having a wiring area ratio in the layer plane of 50% or more among the wiring layers 3 and 6, and each of the through-holes 11 adjacent to the through-hole 11 is formed. It is important that the pitch be 0.1 to 2.0 mm on average.
[0019]
At this time, if the average pitch of the through holes 11 is less than 0.1 mm, the number of the through holes 11 increases, so that the electric resistance increases and the electric characteristics are adversely affected.
[0020]
On the other hand, when the average pitch exceeds 2.0 mm, decomposed gas of organic components generated at the time of binder removal becomes difficult to escape, so that delamination and cracks occur between layers and patterns.
[0021]
In consideration of these, it is important that the average pitch between the through holes 11 is 0.1 to 2.0 mm, and from the viewpoint of easy formation of the through holes, the average pitch is most preferably 0.3 to 1.0 mm. desirable.
[0022]
If the diameter of the through-hole 11 is too small, it cannot sufficiently serve as a path through which gas passes during debinding, and if the diameter of the through-hole 11 is too large, the resistance of the wiring layer 6 increases. Therefore, it is important that the average of the diameters of the through holes 11 is 0.05 to 0.40 mm, and most preferably 0.08 to 0.20 mm.
[0023]
The diameter of the through-hole 11 is the maximum diameter of each through-hole 11, and corresponds to a diagonal line when the through-hole 11 is square. Therefore, the average diameter of the through holes 11 is obtained by dividing the sum of the diameters of the through holes 11 by the number of the through holes 11.
[0024]
Regarding the relationship between the average pitch and the average diameter of the through-holes, if the average ratio of the average pitch / the average diameter of the through-holes is smaller than 1.2, the conduction resistance increases. It is desirable that this is the case.
[0025]
In the present invention, as shown in FIG. 2, the average value of the through-hole a inside the wiring layer 6 is calculated from the pitch of all the adjacent through-holes (a1 to a9) ((a1 + a2 + a3 +). ~ A9) / 9).
[0026]
As for the through-hole b present at the outermost peripheral portion of the wiring layer 6, in addition to all the adjacent through-holes (b1, b2, b3, b4, b6), the outer side (b5) of the wiring layer 6 is also a through-hole. Therefore, a method of calculating an average value from the shortest distance between the through hole b and the through holes (b1, b2, b3, b4, b5, b6) ((b1 + b2 + ｂb6) / 6) was adopted.
[0027]
Note that the pitch in this case is the distance between the center of the through hole 11 and the center of the adjacent through hole 11. For example, a1 used in the calculation is the distance between the centers of the through hole a and the through hole a1 in FIG. Represents the distance of.
[0028]
Further, as shown in FIG. 2, the shape of the through hole 11 does not need to be circular, but may be polygonal or elliptical as needed.
[0029]
Hereinafter, a method for manufacturing a multilayer wiring board of the present invention will be described with reference to the process chart of FIG. 3 using the multilayer wiring board of the present invention of FIG. 1 as an example.
[0030]
Here, a glass ceramic will be described as an example of the ceramic material forming the insulating substrate. First, a glass powder having an average particle size of 0.5 to 10 μm, particularly 1 to 5 μm, and a ceramic filler powder having an average particle size of 0.5 to 10 μm, particularly 1 to 5 μm are prepared.
[0031]
The glass component used includes at least SiO ₂ and at least one of Al ₂ O ₃ , B ₂ O ₃ , ZnO, PbO, an alkaline earth metal oxide, and an alkali metal oxide. For example, borosilicates such as a SiO ₂ —B ₂ O ₃ system and a SiO ₂ —B ₂ O ₃ —Al ₂ O ₃ —MO system (where M represents Ca, Sr, Mg, Ba or Zn) Examples include glass, alkali silicate glass, Ba-based glass, Pb-based glass, and Bi-based glass.
[0032]
These glasses are also amorphous glasses by calcination treatment.Also, by calcination treatment, alkali metal silicate, quartz, cristobalite, cordierite, mullite, enstatite, anorthite, celsian, spinel, garnite, diopite What precipitates at least one kind of crystal of side, ilmenite, willemite, dolomite, petalite or a substituted derivative thereof is used.
[0033]
Further, as the ceramic filler, at least one selected from the group consisting of SiO ₂ such as quartz and cristobalite, Al ₂ O ₃ , ZrO ₂ , mullite, forsterite, enstatite, spinel, and magnesia is preferably used.
[0034]
The glass powder and the ceramic filler powder are mixed in a proportion of, in particular, 10 to 90% by weight, especially 50 to 80% by weight, of the glass component and 10 to 90% by weight, especially 20 to 50% by weight of the ceramic filler component. After adding an organic binder or the like to the mixture, the mixture is formed into a sheet by a doctor blade method, a rolling method, a pressing method, or the like, to produce a green sheet 1 having a thickness of about 50 to 500 μm.
[0035]
Next, a through hole having a diameter of 50 to 200 μm is formed in the green sheet 1 by laser, micro drill, punching, or the like, and a conductive paste is filled therein to form a via hole conductor 2 (FIG. 3A). .
[0036]
The conductive paste is formed by mixing a metal component such as Cu, Ag, and Au with an organic binder such as an acrylic resin and an organic solvent such as toluene, isopropyl alcohol, and acetone.
[0037]
It is preferable that the organic binder is mixed at a ratio of 0.5 to 15.0 parts by weight with respect to 100 parts by weight of the metal component, and the organic solvent is mixed at a ratio of 5 to 100 parts by weight with respect to 100 parts by weight of the solid component and the organic binder. In addition, a slight glass component, an inorganic powder, or the like may be added to the conductor paste in order to match firing shrinkage with the glass ceramic material.
[0038]
Next, on the surface of the green sheet 1, the wiring layer 3 and the wiring layer 6 in which the area ratio of the wiring occupying in the layer surface exceeds 50% are formed. It is desirable that the width of the wiring layer 3 is 75 μm or less, particularly 50 μm or less, and the pitch of the wiring layer 3 is 150 μm or less.
[0039]
In particular, in order to reduce the wiring width to 100 μm or less, it is desirable to form the wiring with a high-purity metal having a purity of 99.5% or more, particularly a metal foil.
[0040]
The material of the metal foil is desirably copper because of its low resistance and suppression of migration. It is desirable that the wiring layers 3 and 6 be formed of copper foil for the same reason.
[0041]
For the wiring layer 3 and the wiring layer 6 made of such a metal foil, a method is known in which a desired circuit is formed by a method such as a well-known photo-etching method after bonding the metal foil to the surface of the green sheet 1. However, in such a method, the green sheet 1 is deteriorated by the etching solution. Therefore, in the present invention, the green sheet 1 is formed by a transfer method.
[0042]
As a method of forming the wiring layer 3 and the wiring layer 6 by the transfer method, first, a high-purity metal conductor, in particular, a copper foil is bonded to one surface of a resin film 5 made of a polymer material with an adhesive made of a thermoplastic resin.
[0043]
After applying a resist on the surface of the metal conductor to a mirror image wiring pattern or a portion where a through hole is formed, a general wiring layer 3 and a through hole 11 are formed on the surface of the resin film 5 by a method of etching and removing the resist. The wiring layer 6 serving as the formed ground layer can be formed.
[0044]
Next, the wiring layer 3 and the wiring layer 6 on the resin film 5 are aligned and laminated and pressed on the surface of the green sheet 1 on which the via-hole conductor 2 is formed (FIG. 3B). By peeling off, one unit of the green sheet 1 including the wiring layer 3 and the wiring layer 6 connected to the via hole conductor 2 can be formed.
[0045]
Thereafter, the plurality of green sheets 1a to 1d obtained in the same manner are laminated and pressed to form a laminate (FIG. 3C).
[0046]
The stacking of the green sheets 1 may be performed by applying heat and pressure to the stacked green sheets 1 to perform thermocompression bonding, or by applying an adhesive made of an organic binder, a plasticizer, a solvent, or the like between the sheets and performing thermocompression bonding. it can.
[0047]
Next, in order to suppress shrinkage in the X-Y direction (planar direction) of the above-mentioned laminate during sintering, a restraint mainly composed of a non-sinterable ceramic material at the sintering temperature of the laminate of green sheets 1a to 1c. The sheet 8 is laminated under pressure on both sides or one side of the laminated body of the glass ceramic green sheets 1a to 1d to produce a laminated body (FIG. 3D).
[0048]
The constraining sheet 8 is obtained by forming a slurry in which an organic binder, a plasticizer, a solvent, and the like are added to an inorganic component mainly composed of a non-sinterable ceramic material into a sheet shape.
[0049]
The non-sinterable ceramic material is specifically composed of a ceramic composition that does not densify at a temperature of 1000 ° C. or less, and specifically, Al ₂ O having an average particle size of 1 to 20 μm, particularly 3 to 10 μm. _{3, SiO 2, MgO, ZrO} 2, BN, at least one and / or the composite oxide thereof selected from the group consisting of TiO ₂ (forsterite _(Mg 2 _SiO 4), enstatite (MgSiO ₃₎ or the like) powder Is mentioned.
[0050]
As the organic binder, plasticizer and solvent in the constraining sheet 8, the same materials as those forming the glass ceramic green sheet, specifically, an acrylic resin, a plasticizer such as DBP, and a solvent such as IPA, acetone and toluene are used. Etc. can be suitably used.
[0051]
Further, it is desirable that the constraining sheet 8 contains a glass component, in other words, an amorphous component in an amount of 0.5 to 15% by weight, particularly 1 to 12% by weight, thereby increasing the binding force of firing shrinkage. In addition, it is possible to suppress the movement of the glass at the portion in contact with the restraining sheet 8 and prevent the occurrence of poor sintering or the like.
[0052]
Although this glass component may be different from the glass component contained in the green sheet 1, it is desirable to use the same glass component in order to prevent the glass in the green sheet 1 from diffusing.
[0053]
Next, the laminate is subjected to heat treatment in an oxidizing or weakly oxidizing atmosphere at 100 to 850 ° C., particularly 400 to 750 ° C. to decompose and remove organic components in the green sheets 1 a to 1 d and the via-hole conductor 2. The conditions at this time are set such that the organic components in the green sheet 1 are removed and the adhesive layer formed on the surface of the wiring layer 3 can be decomposed and removed when the wiring layers 3 and 6 are transferred and formed.
[0054]
In the case of using an acrylic resin having excellent thermal decomposability, it is possible to make almost no carbon residue by holding the resin in an atmosphere of N ₂ at 500 to 800 ° C. for about 0.5 to 2 hours. it can. Then co-fired in a _{N 2} atmosphere at 800 to 1050 ° C..
[0055]
After the firing, the constraining sheet 8 is formed by applying abrasive grains containing at least one selected from Al ₂ O ₃ , SiO ₂ , MgO, ZrO ₂ , BN, TiO _{2 and the} like together with air at a pressure of 0.05 to 0.5 MPa. The multilayer wiring board of the present invention can be manufactured by spraying and removing.
[0056]
By baking using the restraint sheet 8, shrinkage during firing is suppressed only in the thickness direction by the restraint sheet 8, so that shrinkage in the plane of the laminate is reduced, for example, when the laminate has a rectangular shape. Can reduce the shrinkage rate of one side length to 0.5% or less, and moreover, the glass ceramic green sheets 1a to 1d are uniformly and securely bonded by the constraint sheet 8 over the entire surface. 8 can be prevented from warping or deforming due to partial peeling or the like.
[0057]
【Example】
_{BaO-MgO-SiO 2 -B 2} O 3 system as the glass powder 50 wt% and the ceramic filler powder was weighed and Quartz 50% by weight, the acrylic resin (mainly methacrylic acid) as a binder thereto, DBP as a plasticizer (Dibutyl phthalate) and a slurry prepared by adding and mixing toluene and isopropyl alcohol as a solvent were used to prepare a green sheet having a thickness of 500 μm by a doctor blade method.
[0058]
Next, with respect to Cu powder having an average particle diameter of 5 μm, 8 wt% of SiO ₂ powder as a filler component, 2 parts by weight of an acrylic resin as an organic binder with respect to these inorganic components, and 75 wt% of acetone as a solvent. The mixture was added and kneaded at a ratio of parts by weight to prepare a paste-like paste for via-hole conductor. Then, via holes were formed at predetermined locations of the green sheet, and the via holes were filled with the paste for via holes.
[0059]
On the other hand, a copper foil having a purity of 99.5% or more and a thickness of 9 to 35 μm is adhered to the resin film with an adhesive made of an acrylic resin (adhesion strength of 160 g / 10 mm according to JISZ0237), and then resist application, development, etching, By removing the resist, a wiring layer having a predetermined pattern such as a wiring layer having a circular through hole was formed.
[0060]
In the experiment, in order to examine the relationship between the wiring area ratio and delamination, cracks, etc., as shown in Table 1, a 9 μm thick copper foil was used and the wiring area ratio in the layer plane was variously changed in the range of 20 to 70%.
[0061]
Further, as shown in Table 2, for the wiring layer having an area ratio of more than 50% in the layer plane, the average pitch of the through-holes, the average of the through-hole diameters, and the relationship between the thickness of the copper foil and the delamination, cracks, etc. were examined. Using a copper foil having a thickness of ~ 35 µm, the average pitch of the sample in which no through hole is formed and the adjacent through hole is 0.05 to 2.5 mm, and the average of the through hole diameter is in the range of 0.01 to 0.50 mm. Samples in which various through-holes having a through-hole diameter of 0.01 to 0.50 mm were formed were produced.
[0062]
Due to the formation by etching, a very fine wiring layer could be formed as compared with the conventional screen printing method.
[0063]
Then, an adhesive made of an acrylic resin was applied to the wiring layer forming surface of the resin film by screen printing.
[0064]
Then, the resin film on which the wiring layer was formed was laminated on the green sheet on which the via hole was formed while being aligned with the position of the via hole, and thermocompression bonded at 60 ° C. and 15 MPa to form a wiring layer on the surface of the green sheet. Thereafter, the resin film was peeled off while applying a temperature of 30 to 50 ° C., thereby forming one unit of a wiring layer having a wiring layer to which a via-hole conductor was connected. In addition, five arbitrary one unit green sheets were laminated to form a laminate.
[0065]
On the other hand, a 250-μm-thick restraint sheet made of a composition of a ceramic powder mainly containing alumina or forsterite having an average particle diameter of 2 μm and a glass powder having an average particle diameter of 5 μm was prepared. In addition, the organic binder, plasticizer, solvent, etc. at the time of sheet production were the same compounding quantity as the green sheet. This constrained sheet was laminated under pressure at 60 ° C. and 20 MPa on both sides of the green sheet laminate to obtain a laminate.
[0066]
Next, this laminate is placed on an Al ₂ O ₃ setter and heated to 700 ° C. in a nitrogen atmosphere to further decompose and remove organic components such as an organic binder, and further at 950 ° C. for 1 hour in a nitrogen atmosphere. The firing was performed. The cooling rate after firing was 300 ° C./hr.
[0067]
Thereafter, the constraining sheet (non-sintered inorganic composition) was removed by spraying the Al ₂ O ₃ abrasive grains with air at a pressure of 0.2 MPa, and then Au plating was performed to produce a multilayer wiring board for evaluation. .
(Delamination, crack)
With respect to the obtained multilayer wiring board, the presence or absence of delamination and cracks in the cross section of the board was confirmed. Those with more than 20 NGs per 100 multilayer wiring boards were judged as NG. The results are shown in Tables 1 and 2.
(Conduction resistance)
Also, the conduction resistance of the wiring layer was evaluated using this multilayer wiring board. For evaluation, the wiring resistance was measured with a tester at both ends of a wiring layer (40 mm square) made of copper foil, and the wiring resistance exceeding 16 mΩ was regarded as NG. The results are shown in Tables 1 and 2.
[0068]
[Table 1]

[0069]
As is clear from the results in Table 1, the sample No. having a wiring area ratio of 50% or less in the wiring layer surface was used. In Nos. 1 to 5, neither delamination nor cracks occurred, and a product was produced with a high yield. On the other hand, the sample No. having the wiring area ratio in the wiring layer plane exceeding 50%. In Nos. 6 to 9, delamination and cracks occurred frequently, and the yield was reduced.
[0070]
[Table 2]

[0071]
As is clear from the results in Table 2, samples Nos. 10 and 26 having no through-hole have many delaminations and cracks, and the yield is less than 50%, which is not practical.
[0072]
Further, the sample No. having a through hole pitch exceeding 2.0 mm was used. Samples Nos. 18 and 34 are improved as compared with Sample Nos. 10 and 26 having no through hole, but are not practical because the number of cracks and delaminations in 100 samples exceeds 20.
[0073]
Sample Nos. 11 and 27 having a through-hole pitch of less than 0.1 mm are not practical because the conduction resistance exceeds 16 mΩ.
[0074]
Sample No. having an average diameter of through holes smaller than 0.05 mm. In Nos. 19 and 35, since a few delaminations and cracks occurred, the average of the through-hole diameters had to be 0.05 mm or more.
[0075]
Sample No. having an average diameter of the through holes larger than 0.40 mm. In 25 and 41, since the substrate conduction resistance exceeded 16 mΩ, the average of the through-hole diameters had to be 0.4 mm or less.
[0076]
On the other hand, in Sample Nos. 12 to 17, 20 to 24, 28 to 33, 36 to 40, and 42 to 44, which are within the scope of the present invention, cracks and delaminations are not or very few, and the problem of electric characteristics is also low. No sample was obtained.
[0077]
Sample No. having a wiring layer thickness of 25, 35 μm. With respect to Sample Nos. 43 and 44, no problem was found in terms of characteristics. In No. 44, the etching failure occurred in the through-holes of 0.05 mm or less among the through-holes.
[0078]
【The invention's effect】
As described above in detail, according to the present invention, in an insulating substrate made of glass ceramic and a multilayer wiring substrate having a wiring layer formed of metal foil on the surface and / or inside of the insulating substrate, A plurality of through holes are formed in a wiring layer having a wiring area ratio of 50% or more, the pitch between the adjacent through holes is set to an average of 0.1 to 2.0 mm, and the average of the maximum diameter of the through holes is set to 0.05. By setting the thickness to 0.40 mm, generation of cracks, delaminations, and the like in the substrate is suppressed, and a multilayer wiring substrate having excellent electrical characteristics can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining a multilayer wiring board of the present invention.
FIG. 2 is a schematic view of a wiring layer in which a through hole is formed in a multilayer wiring board of the present invention, as viewed from above.
FIG. 3 is a process diagram illustrating a method for manufacturing a multilayer wiring board according to the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 ceramic green sheet 2 via hole conductor 3 wiring layer 5 resin film 6 wiring layer 8 restraining sheet 10 insulating substrate 11 through hole A multilayer wiring board B electronic component a, a1 to 9, b, b1 to 6 through hole

Claims (3)

In a multi-layer wiring board in which a wiring layer is formed of a metal foil on the surface and / or inside of the insulating substrate made of ceramic, and the wiring layer has an area ratio of more than 50% in the plane of the wiring layer, a plurality of through-holes are formed in the wiring layer. A multilayer wiring board having holes formed therein, wherein the pitch between adjacent through holes is 0.1 to 2.0 mm on average, and the average of the maximum diameter of the through holes is 0.05 to 0.40 mm. 2. The multilayer wiring board according to claim 1, wherein said metal foil is made of copper foil. 2. The multilayer wiring board according to claim 1, wherein the thickness of the wiring layer is 25 μm or less.

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