JP2006222307A - Wiring board - Google Patents

Wiring board Download PDF

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JP2006222307A
JP2006222307A JP2005035003A JP2005035003A JP2006222307A JP 2006222307 A JP2006222307 A JP 2006222307A JP 2005035003 A JP2005035003 A JP 2005035003A JP 2005035003 A JP2005035003 A JP 2005035003A JP 2006222307 A JP2006222307 A JP 2006222307A
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insulating
wiring
wiring board
less
glass
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JP4703207B2 (en
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Shinya Kawai
信也 川井
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having an insulating layer made thin to have a thickness ≤100 μm and exhibiting high insulation, even if it is subjected to plating treatment. <P>SOLUTION: This wiring board is composed of an insulating board comprising a plurality of laminated insulating layers and formed with a wiring layer at least on the surface of the insulating board, and the surface of the insulating board is composed of a glass ceramic sintered substance with a thickness of ≤100 μm containing glass and a crystal phase. The areal occupation rate of voids at the cross section of the insulating board is ≤3%, and the weight reduction thereof upon one minute immersion in a 1 mass% HF aqueous solution is ≤3 μg/mm<SP>2</SP>. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電気素子収納用パッケージや混成集積回路装置等に用いられる配線基板に関するものである。   The present invention relates to a wiring board used in an electrical element storage package, a hybrid integrated circuit device, or the like.

近年における情報通信技術の急速な発展は、使用する周波数の高周波化をもたらし、情報通信用途に使用される配線基板では、高周波信号の伝送損失を低減するために、配線層の低抵抗化と絶縁層の低誘電率化が求められている。そこで、1000℃以下での焼成によって緻密化でき、金、銀、銅等の低抵抗金属を主成分とする配線層との同時焼成が可能なガラスセラミックス焼結体を絶縁層とする配線基板が提案されている。   The rapid development of information communication technology in recent years has led to higher frequencies used, and in wiring boards used for information communication applications, in order to reduce transmission loss of high-frequency signals, lower resistance and insulation of the wiring layer There is a demand for a low dielectric constant of the layer. Therefore, a wiring board having a glass ceramic sintered body that can be densified by firing at 1000 ° C. or less and can be simultaneously fired with a wiring layer mainly composed of a low-resistance metal such as gold, silver, or copper is used as an insulating layer. Proposed.

さらに、これら配線基板においては高密度化、小型軽量化への要求が非常に強く要求されており、携帯電話に代表される携帯型の情報通信機器へ搭載される配線基板においてその要求が特に強い。このような、高密度化、小型軽量化への要求に対して、特に、低背化という要求に対して、配線基板を構成する絶縁層の厚みを薄層化することが提案されているが、絶縁層が薄くなることによって絶縁性が低下するという問題が発生する。   Furthermore, these wiring boards are extremely demanded for high density, small size, and light weight, and the demand is particularly strong in wiring boards mounted on portable information communication devices represented by mobile phones. . In response to such demands for higher density and smaller size and weight, it has been proposed to reduce the thickness of the insulating layer constituting the wiring board, particularly for the demand for lower height. As a result, a problem arises in that the insulating properties are lowered due to the thin insulating layer.

そこで、各絶縁層の厚みを100μm以下に薄層化を図ると同時に、結晶子の最大径を5μm以下、絶縁層のボイド面積率を3%以下、最大ボイド径を5μm以下に制御した絶縁性ガラスセラミックスを用いることにより絶縁層の比抵抗を1011Ω・cm以上に絶縁性を改善したことが開示されている(例えば、特許文献1参照)。
特開2004−235347号公報
Therefore, the thickness of each insulating layer is reduced to 100 μm or less, and at the same time, the maximum crystallite diameter is controlled to 5 μm or less, the void area ratio of the insulating layer is controlled to 3% or less, and the maximum void diameter is controlled to 5 μm or less. It is disclosed that the insulating property is improved to 10 11 Ω · cm or more by using glass ceramics (see, for example, Patent Document 1).
JP 2004-235347 A

しかしながら、上記特許文献1に記載されている絶縁層は、低抵抗金属からなる配線層と同時焼成を行った後、表面配線層にめっき膜を形成するが、めっき処理において絶縁層の内部にまでめっき液が浸透し、絶縁層内部にめっき成分である金属が析出するため、表面の絶縁層を挟む配線層間の絶縁性が低下し、短絡等が発生するという問題があった。   However, the insulating layer described in Patent Document 1 forms a plating film on the surface wiring layer after co-firing with a wiring layer made of a low-resistance metal. Since the plating solution penetrates and the metal as the plating component is deposited inside the insulating layer, there is a problem that the insulation between the wiring layers sandwiching the insulating layer on the surface is lowered, and a short circuit or the like occurs.

従って、本発明は、絶縁層の厚みを100μm以下と薄層化し、めっき処理を施しても、高い絶縁性を示す配線基板を提供することを目的とする。   Accordingly, an object of the present invention is to provide a wiring board that exhibits high insulation even when the thickness of the insulating layer is reduced to 100 μm or less and plating is performed.

本発明の配線基板は、複数の絶縁層を積層してなる絶縁基板からなり、該絶縁基板の少なくとも表面に配線層を具備する配線基板であって、前記絶縁基板の表面に配設された絶縁層が、ガラス及び結晶相を含み、厚みが100μm以下のガラスセラミック焼結体からなり、前記絶縁基板の断面におけるボイドの面積占有率が3%以下、1質量%HF水溶液に1分間浸漬した際の重量減少が3μg/mm以下であることを特徴とする。 The wiring board of the present invention comprises an insulating substrate formed by laminating a plurality of insulating layers, and has a wiring layer on at least the surface of the insulating substrate, and the insulating substrate disposed on the surface of the insulating substrate. When the layer is made of a glass ceramic sintered body containing glass and a crystalline phase and having a thickness of 100 μm or less, the void area occupancy in the cross section of the insulating substrate is 3% or less, and when immersed in a 1% by mass HF aqueous solution for 1 minute The weight loss is 3 μg / mm 2 or less.

特に、前記ボイドのうち、略球状のボイドの占有面積が全体の75%以上であることが好ましい。これにより、めっき液の浸透をより効果的に抑制できるという利点がある。   In particular, among the voids, the area occupied by the substantially spherical voids is preferably 75% or more of the whole. Thereby, there exists an advantage that the osmosis | permeation of plating solution can be suppressed more effectively.

前記ボイドのうち、孤立して存在するボイドの占有面積が全体の75%以上であることが好ましい。これにより、めっき液の浸透をより効果的に抑制することが可能となる。   Among the voids, it is preferable that the occupied area of the voids present in isolation is 75% or more of the whole. Thereby, it is possible to more effectively suppress the penetration of the plating solution.

前記ガラスセラミック焼結体が、実質的にアルカリ金属酸化物を含有しないことが好ましい。これにより、絶縁層の絶縁性を高めることができるという利点がある。   It is preferable that the glass ceramic sintered body does not substantially contain an alkali metal oxide. Thereby, there exists an advantage that the insulation of an insulating layer can be improved.

前記表面に配置された絶縁層の厚み方向の電気抵抗が、10Ω/mm以上であることが好ましい。これにより、絶縁層の厚み方向の絶縁性を確保することができるという利点がある。 The electrical resistance in the thickness direction of the insulating layer disposed on the surface is preferably 10 9 Ω / mm 2 or more. Thereby, there exists an advantage that the insulation of the thickness direction of an insulating layer can be ensured.

前記配線層が、金、銀及び銅の少なくとも1種を主成分とすることが好ましい。これにより、低抵抗の配線を形成することができるという利点がある。   The wiring layer preferably contains at least one of gold, silver and copper as a main component. This has an advantage that a low-resistance wiring can be formed.

前記絶縁基板の表面に配設された配線層の表面に、めっき層が被着形成されていることが好ましい。これにより、配線層の半田濡れ性や耐酸化性を確保することができるという利点がある。   It is preferable that a plating layer is deposited on the surface of the wiring layer disposed on the surface of the insulating substrate. Thereby, there is an advantage that solder wettability and oxidation resistance of the wiring layer can be ensured.

本発明は、めっき処理の前処理として酸を用いた表面処理を行うため、酸溶液に浸された絶縁層を構成する絶縁性ガラスセラミックスからガラス成分が溶出し、絶縁層の内部に溶液の浸透する微細な空間が形成され、その空間からめっき液が絶縁層の内部に浸透し、絶縁層の内部に金属が析出することにより絶縁性が低下する、との新規な知見に基づきなされたものであり、耐酸性の高い絶縁性ガラスセラミックスを用いることによって、表面に配置された絶縁層の厚みが100μm以下の配線基板に、めっき処理を行った場合においても高い絶縁性を実現したものである。   Since the present invention performs a surface treatment using an acid as a pretreatment for the plating treatment, the glass component is eluted from the insulating glass ceramics constituting the insulating layer immersed in the acid solution, and the solution penetrates into the insulating layer. It was made based on the novel knowledge that a fine space is formed, the plating solution penetrates into the insulating layer from the space, and the metal is deposited inside the insulating layer, resulting in a decrease in insulation. In addition, by using insulating glass ceramics with high acid resistance, a high insulating property is realized even when a wiring substrate having a thickness of an insulating layer disposed on the surface of 100 μm or less is plated.

即ち、絶縁層が厚い場合には、絶縁層の内部にめっき液が浸透し金属が析出しても、内部電極との絶縁距離が十分あったため、短絡することはなかったが、絶縁層が100μm以下、特に50μm以下、更には30μm以下と薄くなると、上記絶縁距離が短くなり、短絡すること、そして、それがめっきの前処理として行う薬品処理によって絶縁性ガラスセラミックスが溶出することが原因であることを見出し、絶縁層のボイドの面積占有率を3%以下にするとともに、1質量%HF水溶液に1分間浸漬した際の重量減少を3μg/mm以下とすることによって、高い絶縁性を維持することができる。 That is, when the insulating layer is thick, even if the plating solution penetrates into the insulating layer and the metal is deposited, there is a sufficient insulation distance from the internal electrode, so there is no short circuit, but the insulating layer is 100 μm. Hereinafter, particularly when the thickness is reduced to 50 μm or less, and further to 30 μm or less, the insulation distance is shortened and short-circuited. This is because the insulating glass ceramic is eluted by chemical treatment performed as a pretreatment for plating. And found that the void area occupancy of the insulating layer is 3% or less, and the weight loss when immersed in a 1% by mass HF aqueous solution for 1 minute is 3 μg / mm 2 or less, thereby maintaining high insulation. can do.

以下、本発明の配線基板について、図面に基づいて説明する。図1は本発明の配線基板を用いた、混成集積回路装置の概略断面図を示す。   Hereinafter, a wiring board of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view of a hybrid integrated circuit device using the wiring board of the present invention.

図1において、配線基板Aは複数の絶縁層1a〜1eを積層してなる絶縁基板1からなり、各絶縁層の表面および界面には、金、銀及び銅のいずれかを主成分とする低抵抗金属からなる配線層2が形成されている。また、上記の配線層2を電気的に接続するためのビアホール導体3が、絶縁層1a〜1eを貫通するように形成されており、該ビアホール導体3は、金、銀、銅等のいずれかを主成分とする低抵抗金属からなる。さらに、配線基板Aの下面には複数の接続用電極4Aが配列されており、この接続用電極4Aは、プリント基板等の外部回路基板Bの接続用電極4Bと半田9等により接続されている。   In FIG. 1, a wiring board A is composed of an insulating substrate 1 formed by laminating a plurality of insulating layers 1a to 1e, and the surface and interface of each insulating layer are low in the main component of gold, silver or copper. A wiring layer 2 made of a resistance metal is formed. A via-hole conductor 3 for electrically connecting the wiring layer 2 is formed so as to penetrate the insulating layers 1a to 1e, and the via-hole conductor 3 is any one of gold, silver, copper, and the like. It consists of a low resistance metal whose main component is. Furthermore, a plurality of connection electrodes 4A are arranged on the lower surface of the wiring board A, and the connection electrodes 4A are connected to the connection electrodes 4B of the external circuit board B such as a printed circuit board by solder 9 or the like. .

配線基板Aの表面には、SiやGaAsなどの半導体素子、SAWデバイスやコンデンサ等の各種電子部品5がガラスやアンダーフィル剤等の接着剤10あるいは半田8を介して接着固定され、この電子部品5の表面はポッティング剤等からなる封止樹脂6により封止されている。また、電子部品5は配線層2とワイヤボンディング7や半田8等を介して電気的に接続される。   Various electronic components 5 such as semiconductor elements such as Si and GaAs, SAW devices and capacitors are bonded and fixed to the surface of the wiring board A via an adhesive 10 such as glass or an underfill agent or solder 8. The surface of 5 is sealed with a sealing resin 6 made of a potting agent or the like. In addition, the electronic component 5 is electrically connected to the wiring layer 2 via the wire bonding 7, solder 8, and the like.

本発明の配線基板においては、表面に配置された絶縁層1aが、ガラス及び結晶相を含み、厚みが100μm以下のガラスセラミック焼結体からなることを大きな特徴とするものである。絶縁層1aは、さらなる低背化を図るため、50μm以下、特に30μm以下であることが好ましい。   The wiring board of the present invention is characterized in that the insulating layer 1a disposed on the surface is made of a glass ceramic sintered body having a thickness of 100 μm or less, including glass and a crystal phase. In order to further reduce the height of the insulating layer 1a, it is preferably 50 μm or less, particularly preferably 30 μm or less.

本発明によれば、100μm以下の薄層化した絶縁層の絶縁性を高めるためには、絶縁基板の断面におけるボイドの面積占有率(以下、単にボイド率と言う)が3%以下であることが重要であり、特に2.5%以下、更には2%以下が好ましい。   According to the present invention, in order to improve the insulation of a thin insulating layer having a thickness of 100 μm or less, the void area occupation ratio (hereinafter simply referred to as void ratio) in the cross section of the insulating substrate is 3% or less. Is important, and is preferably 2.5% or less, more preferably 2% or less.

ボイド率が3%を超えると、ボイド同士が連結し易くなり、このような連結したボイドが表面にあると、ボイドの内部に酸が進入し、さらに内部までボイドが拡大し、拡大した連結ボイドの内部にめっき膜が形成されるため、絶縁層の絶縁性が低下する恐れがある。   When the void ratio exceeds 3%, the voids are easily connected to each other. When such a connected void is present on the surface, the acid enters the inside of the void, and the void further expands to the inside. Since the plating film is formed inside the insulating layer, the insulating property of the insulating layer may be lowered.

また、大きなボイドが表面に存在する場合でも同様の現象が発生するため、緻密化を進めてボイド率を3%以下とし、大きなボイドを除去することが重要である。特に、ボイドの平均径を5μm以下、更には3μm以下、より好適には2μm以下とすることが好ましい。   In addition, since a similar phenomenon occurs even when a large void exists on the surface, it is important to remove the large void by proceeding with densification to reduce the void ratio to 3% or less. In particular, it is preferable that the average diameter of the voids is 5 μm or less, further 3 μm or less, and more preferably 2 μm or less.

なお、本発明におけるボイドの平均径は、ボイドの断面積を円換算し、その直径を平均径として算出したものである。   In addition, the average diameter of the void in the present invention is calculated by converting the cross-sectional area of the void into a circle and using the diameter as the average diameter.

本発明によれば、絶縁基板に含まれるボイドのうち、略球状のボイドの占有面積が全体の75%以上、特に80%以上、更には85%以上とすることが好ましい。ボイドの形状が略球状であれば、複数のボイドが3次元的に結合しにくくなり、そのような球状ボイドの占有面積を上記範囲に設定することによって、絶縁層の内部へのめっき液の浸透をより効果的に抑制し、高い絶縁性を維持できる。   According to the present invention, among the voids included in the insulating substrate, the area occupied by the substantially spherical voids is preferably 75% or more, particularly 80% or more, and more preferably 85% or more. If the shape of the void is substantially spherical, a plurality of voids are difficult to combine three-dimensionally. By setting the occupied area of such a spherical void in the above range, the plating solution penetrates into the insulating layer. Can be more effectively suppressed and high insulation can be maintained.

また、絶縁基板に含まれるボイドのうち、孤立して存在するボイドの占有面積が全体の75%以上、特に80%以上、更には85%以上であることが好ましい。ボイドが孤立して存在すれば、ボイドの内部にめっき液が進入しても、その深度はボイド径と略同一程度であり、めっき液の浸透をより効果的に抑制し、高い絶縁性を維持できる。   In addition, among the voids included in the insulating substrate, it is preferable that the occupied area of the isolated voids is 75% or more, particularly 80% or more, and more preferably 85% or more. If voids exist in isolation, even if the plating solution enters the inside of the void, the depth is almost the same as the diameter of the void, which suppresses plating solution penetration more effectively and maintains high insulation. it can.

また、本発明によれば、1質量%HF水溶液に1分間浸漬した際の重量減少が3μg/mm以下であることも重要であり、特に2.5μg/mm以下、更には2μm/mm以下であることが好ましい。1質量%HF水溶液に1分間浸漬した際の重量減少を小さくするということは、即ち、絶縁層を構成するガラスセラミックス焼結体からのガラス成分の溶出を抑制するということであり、これにより、絶縁層の内部へのめっき液の浸透をより効果的に抑制し、高い絶縁性を維持できる。 Further, according to the present invention, it is also important that the weight loss when immersed in a 1% by mass aqueous HF solution for 1 minute is 3 μg / mm 2 or less, particularly 2.5 μg / mm 2 or less, and further 2 μm / mm. It is preferable that it is 2 or less. Reducing the weight loss when immersed in a 1% by mass HF aqueous solution for 1 minute means that the elution of the glass component from the glass ceramic sintered body constituting the insulating layer is suppressed. It is possible to more effectively suppress the penetration of the plating solution into the insulating layer and maintain high insulation.

逆に重量減少が3μg/mmよりも大きい場合には、絶縁層を構成するガラスセラミックス焼結体からガラス成分が溶出し、絶縁層の内部に溶液の浸透する微細な空間が形成され、その空間からめっき液も絶縁層の内部に浸透し、絶縁層の内部に金属が析出する結果、絶縁性を大きく損なう恐れがある。 On the other hand, when the weight loss is larger than 3 μg / mm 2 , the glass component is eluted from the glass ceramic sintered body constituting the insulating layer, and a fine space into which the solution permeates is formed inside the insulating layer. The plating solution also penetrates into the insulating layer from the space, and as a result of the metal depositing inside the insulating layer, there is a possibility that the insulating property is greatly impaired.

なお、HFは、めっき処理の前に、配線層上に存在するガラスを除去するために行うガラスエッチング処理において一般に使用される薬品であり、SiOを含有するガラスを溶解させる働きを有する。 HF is a chemical generally used in a glass etching process for removing glass existing on the wiring layer before the plating process, and has a function of dissolving glass containing SiO 2 .

本発明によれば、配線基板の表面に配置された絶縁層の厚み方向の電気抵抗を、10Ω/mm以上、特に1010Ω/mm以上、更には1011Ω/mm以上とすることが好ましい。これにより、めっき後の絶縁層の厚み方向の絶縁性を確保することが容易になり、具体的には、めっき後の絶縁層の厚み方向の電気抵抗を10Ω/mm以上とすることができる。 According to the present invention, the electrical resistance in the thickness direction of the insulating layer disposed on the surface of the wiring board is 10 9 Ω / mm 2 or more, particularly 10 10 Ω / mm 2 or more, more preferably 10 11 Ω / mm 2 or more. It is preferable that This makes it easy to ensure insulation in the thickness direction of the insulating layer after plating. Specifically, the electrical resistance in the thickness direction of the insulating layer after plating is set to 10 9 Ω / mm 2 or more. Can do.

本発明で用いるガラスセラミック焼結体は、ガラスと結晶相とを含有する。結晶相を含有せしめ、かつその量を増加させることにより、耐酸性を向上させることができる。   The glass ceramic sintered body used in the present invention contains glass and a crystalline phase. Acid resistance can be improved by containing a crystal phase and increasing the amount thereof.

ガラスセラミック焼結体に含まれるガラスとしては、少なくともSiOを含有し、ZrO、TiO、SnOといった4価金属酸化物や、Al、B、Y、Laといった3価金属酸化物や、アルカリ土類酸化物(以下MO)、ZnO、PbOなどの2価金属酸化物、遷移金属酸化物のうち少なくとも1種を含むことが好ましい。これらの組み合わせを調整することにより、酸処理を行っても高い絶縁性を維持することができる。 The glass contained in the glass ceramic sintered body contains at least SiO 2 , a tetravalent metal oxide such as ZrO 2 , TiO 2 , SnO 2 , Al 2 O 3 , B 2 O 3 , Y 2 O 3 , It is preferable to include at least one of trivalent metal oxides such as La 2 O 3 , alkaline earth oxides (hereinafter referred to as MO), divalent metal oxides such as ZnO and PbO, and transition metal oxides. By adjusting these combinations, high insulating properties can be maintained even when acid treatment is performed.

例えば、SiO−B系ガラス、SiO−B−MO系ガラス、SiO−B−Al−MO系ガラス等のほう珪酸系ガラスやBi系ガラス等を例示できる。 For example, borosilicate glass or Bi glass such as SiO 2 —B 2 O 3 glass, SiO 2 —B 2 O 3 —MO glass, SiO 2 —B 2 O 3 —Al 2 O 3 —MO glass, etc. Etc. can be illustrated.

これらのうち、低温で焼成するために好適な軟化特性を制御することが容易であるという点でSiO−B−MO系ガラスを採用するのが好ましく、また、より優れた耐酸性を有する点において、さらにAlやY、ZrO等を含有せしめることが望ましく、特にAlを含有せしめることが望ましい。 Among these, it is preferable to employ SiO 2 —B 2 O 3 —MO-based glass because it is easy to control softening characteristics suitable for firing at low temperature, and more excellent acid resistance. In view of the above, it is desirable to further contain Al 2 O 3 , Y 2 O 3 , ZrO 2 or the like, and it is particularly desirable to contain Al 2 O 3 .

なお、環境調和性を考慮すると、上記ガラスにはPbO、As、CdO、Hg等の有害物質を実質的に含有しないことが望ましい。なお、実質的に含有しないとは、意図的に含有せしめないことを指し、微量の不可避不純物はこの限りではない。 In consideration of environmental harmony, it is desirable that the glass does not substantially contain harmful substances such as PbO, As 2 O 3 , CdO, and Hg. “Substantially not contained” means not intentionally contained, and a trace amount of inevitable impurities is not limited to this.

ガラスセラミック焼結体に含まれる結晶相としては、アルミナ、ジルコニア、クオーツ、クリストバライト、コーディエライト、ムライト、スピネル、ガーナイト、エンスタタイト、フォルステライト、アノーサイト、スラウソナイト、セルジアン、ディオプサイド、モンティセライト、アケルマナイト、ウイレマイト、窒化珪素、窒化アルミニウム、炭化珪素、炭化ホウ素やその固溶体、置換誘導体などを例示できる。   The crystalline phases contained in the sintered glass ceramic include alumina, zirconia, quartz, cristobalite, cordierite, mullite, spinel, garnite, enstatite, forsterite, anorsite, slausonite, serdian, diopside, and montcelite. , Akermanite, willemite, silicon nitride, aluminum nitride, silicon carbide, boron carbide and its solid solutions, substituted derivatives, and the like.

これら結晶相のうち、抗折強度向上させるという点で、アルミナやジルコニア、フォルステライト、エンスタタイト、スピネル、アノーサイト、スラウソナイト、セルジアンを採用するのが好ましく、特に、アルミナ、ジルコニア、フォルステライトが好ましい。また、耐酸性を向上させるという点では、アルミナやジルコニア、フォルステライト、エンスタタイト、スピネル、アノーサイト、スラウソナイト、セルジアン、コーディエライトが好ましく、特に、アルミナ、ジルコニアが好ましい。   Of these crystal phases, it is preferable to employ alumina, zirconia, forsterite, enstatite, spinel, anorthite, slusonite, and serdian, particularly alumina, zirconia, and forsterite in terms of improving the bending strength. . In terms of improving acid resistance, alumina, zirconia, forsterite, enstatite, spinel, anorthite, slausonite, serdian, cordierite are preferable, and alumina and zirconia are particularly preferable.

さらには、誘電率を低下させ高周波信号の伝送損失を低減させるためには、フォルステライト、エンスタタイト、クオーツ、クリストバライト、コーディエライト、ムライト、が好ましく、特に、フォルステライト、クオーツ、コーディエライトが好ましい。さらに、熱伝導率を向上させるためには、アルミナ、窒化珪素、窒化アルミニウム、炭化珪素が好ましく、特に、窒化アルミニウムが好ましい。   Furthermore, forsterite, enstatite, quartz, cristobalite, cordierite, and mullite are preferred to lower the dielectric constant and reduce transmission loss of high-frequency signals, and in particular, forsterite, quartz, and cordierite are preferred. preferable. Furthermore, in order to improve thermal conductivity, alumina, silicon nitride, aluminum nitride, and silicon carbide are preferable, and aluminum nitride is particularly preferable.

これらのガラスと結晶相を適宜組み合わせることにより、ガラスセラミック焼結体の機械的特性や熱特性、誘電特性等の磁器特性を用途に応じて制御することが可能となる。   By appropriately combining these glasses and crystalline phases, it is possible to control the ceramic properties, thermal properties, dielectric properties and other porcelain properties of the glass ceramic sintered body according to the application.

また、ガラスセラミック焼結体が、アルカリ金属酸化物、特に酸化リチウムを実質的に含有しないことが、高い絶縁性を確保するために望ましい。これは、アルカリ金属酸化物が、導電性キャリアとしてガラス相の絶縁性を低下させる恐れのある成分であり、特に酸化リチウムを排除することにより、絶縁層の絶縁性を維持することが容易となる。   Further, it is desirable for the glass ceramic sintered body to contain substantially no alkali metal oxide, particularly lithium oxide, in order to ensure high insulation. This is a component in which the alkali metal oxide may lower the insulating property of the glass phase as a conductive carrier, and in particular, by excluding lithium oxide, it becomes easy to maintain the insulating property of the insulating layer. .

なお、実質的に含有しないとは、意図的に含有せしめないことを指し、微量の不可避不純物はこの限りではない。   “Substantially not contained” means not intentionally contained, and a trace amount of inevitable impurities is not limited to this.

また、高周波信号の伝送損失を低減するために、配線基板の表面に形成された配線層2が、金、銀及び銅の低抵抗金属のうち少なくとも1種を主成分とすることが望ましい。   In order to reduce the transmission loss of the high frequency signal, it is desirable that the wiring layer 2 formed on the surface of the wiring board is mainly composed of at least one of gold, silver and copper low resistance metals.

さらに、表層の配線層の半田濡れ性や耐酸化性等を確保するために、配線基板の表面に配設された配線層の表面に、NiやAu、Cu等のめっき層が被着形成されていることが望ましい。   Furthermore, in order to ensure the solder wettability and oxidation resistance of the surface wiring layer, a plating layer of Ni, Au, Cu or the like is deposited on the surface of the wiring layer disposed on the surface of the wiring substrate. It is desirable that

本発明の配線基板をかかる構成とすることにより、表面に配置された絶縁層1aの厚みが100μm以下と薄層化しても、めっき処理を行った後に高い絶縁性を確保することができる。   By adopting such a configuration of the wiring board of the present invention, even if the thickness of the insulating layer 1a disposed on the surface is reduced to 100 μm or less, high insulation can be ensured after the plating process.

次に、図1に示した配線基板を製造する方法ついて説明する。   Next, a method for manufacturing the wiring board shown in FIG. 1 will be described.

まず、原料粉末としてガラス粉末と所望によりセラミック粉末を準備する。   First, glass powder and optionally ceramic powder are prepared as raw powder.

ガラス粉末としては、前述したガラスが好適に用いられる。このとき、焼成中に結晶化しない非晶質ガラス、逆に焼成中に結晶化する結晶化ガラスのいずれを用いても差し支えないが、高い抗折強度や低い誘電損失を発現させるためには結晶化ガラスを用いることが望ましい。   As the glass powder, the glass described above is preferably used. At this time, either an amorphous glass that does not crystallize during firing or a crystallized glass that crystallizes during firing may be used. However, in order to develop a high bending strength and a low dielectric loss, a crystal can be used. It is desirable to use a vitrified glass.

一方、セラミック粉末としては、前述した結晶相を有するものが好適に用いられるが、これに加えて、石英ガラス等の非晶質の粉末を用いることも可能である。   On the other hand, as the ceramic powder, those having the above-mentioned crystal phase are preferably used, but in addition to this, amorphous powder such as quartz glass can be used.

これらの原料粉末の粒径としては、低いボイド率を達成するために、平均粒径(D50)が、5.0μm以下、特に3.5μm以下、さらには2.5μm以下、最適には2.0μm以下であることが望ましい。   As for the particle size of these raw material powders, in order to achieve a low void ratio, the average particle size (D50) is 5.0 μm or less, particularly 3.5 μm or less, further 2.5 μm or less, and optimally 2. It is desirable that it is 0 μm or less.

また、ボイドの形状を略球状とし、さらに、それぞれのボイドを孤立させるためには、ガラス粉末とセラミック粉末の粒度分布の相違を小さくする、即ち、平均粒径(D50)の差を±1μm以下、特に±0.5μm以下と小さくすることが効果的である。   Further, in order to make the shape of the void substantially spherical and to isolate each void, the difference in the particle size distribution between the glass powder and the ceramic powder is reduced, that is, the difference in the average particle size (D50) is ± 1 μm or less. In particular, it is effective to make it as small as ± 0.5 μm or less.

さらに、高い絶縁性を確保するために、ガラスセラミック焼結体中のアルカリ金属酸化物を実質的に含有せしめないようにするために、ガラス粉末及びセラミック粉末中にアルカリ金属酸化物を実質的に含有せしめないことが望ましい。   Further, in order to ensure high insulation, the alkali metal oxide is substantially contained in the glass powder and the ceramic powder so as not to substantially contain the alkali metal oxide in the glass ceramic sintered body. It is desirable not to contain it.

こうして適宜選択した、ガラス粉末とセラミック粉末とを一定の量比で混合した混合粉末を用いて成形用スラリーを調製し、この成形用スラリーを用いて、例えば厚みが25〜500μmのセラミックグリーンシート(絶縁層1a〜1e用のシート)を成形する。   A molding slurry is prepared by using a mixed powder obtained by appropriately mixing glass powder and ceramic powder in a certain quantitative ratio as described above, and using this molding slurry, for example, a ceramic green sheet having a thickness of 25 to 500 μm ( Sheets for insulating layers 1a to 1e) are formed.

このグリーンシートの所定位置にスルーホールを形成し、このスルーホール内に、銅や銀、金等の低抵抗金属を主成分とする導体ペーストを充填し、ビアホール導体3を形成する。また、表面または界面に配線層2が形成される絶縁層に対応するグリーンシートの表面には、上記の導体ペーストを用いて、スクリーン印刷法、グラビア印刷法などの公知の印刷手法を用いて配線層2の厚みが2〜30μmとなるように、配線パターンを印刷塗布する。   A through hole is formed at a predetermined position of the green sheet, and a conductor paste mainly composed of a low resistance metal such as copper, silver, or gold is filled in the through hole, thereby forming a via hole conductor 3. Further, the surface of the green sheet corresponding to the insulating layer on which the wiring layer 2 is formed on the surface or the interface is wired using the above-described conductor paste by a known printing method such as a screen printing method or a gravure printing method. A wiring pattern is printed and applied so that the thickness of the layer 2 is 2 to 30 μm.

そして、上記のようにして作成された複数のグリーンシートを位置合わせして積層圧着し、次いで、大気中、あるいは水蒸気を含有した窒素雰囲気中にて450〜750℃の温度にて脱バインダ処理した後、1000℃以下の大気中または窒素雰囲気で焼成することにより、配線層2、ビアホール導体3を備えた絶縁基板1が作製される。   Then, the plurality of green sheets prepared as described above were aligned and laminated and pressure-bonded, and then subjected to binder removal treatment at a temperature of 450 to 750 ° C. in the atmosphere or in a nitrogen atmosphere containing water vapor. Then, the insulating substrate 1 provided with the wiring layer 2 and the via-hole conductor 3 is manufactured by firing in the air at 1000 ° C. or lower or in a nitrogen atmosphere.

なお、脱バインダ雰囲気や焼成雰囲気は、用いる低抵抗金属の種類に応じて適宜決定され、例えば、銅を配線導体として用いた場合には大気中での焼成により酸化するため、窒素雰囲気中にて脱バインダ或いは焼成が行なわれる。   Note that the binder removal atmosphere and firing atmosphere are appropriately determined according to the type of low-resistance metal used. For example, when copper is used as the wiring conductor, it is oxidized by firing in the air. Binder removal or firing is performed.

上記のようにして形成された絶縁層1の表面に、半導体素子等の電子部品5を搭載し、配線層2と信号の伝達が可能なように接続される。先にも述べた通り、配線層2上に電子部品5を直接搭載させて半田8等にて両者を接続することもできるし、あるいはワイヤボンディング7を用いて電子部品5と絶縁層1表面の配線層2とを接続させることもできる。また、フリップチップ接続などにより、両者を接続することも可能である。   An electronic component 5 such as a semiconductor element is mounted on the surface of the insulating layer 1 formed as described above, and is connected to the wiring layer 2 so that signals can be transmitted. As described above, the electronic component 5 can be directly mounted on the wiring layer 2 and can be connected by solder 8 or the like. Alternatively, the wire bonding 7 can be used to connect the electronic component 5 and the surface of the insulating layer 1. The wiring layer 2 can also be connected. It is also possible to connect the two by flip chip connection or the like.

さらに、電子部品5が搭載された絶縁層1表面に、封止樹脂6を塗布して硬化させるか、絶縁層1と同種の絶縁材料や、その他の絶縁材料、あるいは放熱性が良好な金属等からなる蓋体をガラス、樹脂、ロウ材等の接着剤により接合することにより、電子部品5を気密に封止することができ、これにより配線基板Aを作製することができる。また、必要に応じて各種放熱板を、配線基板Aにロウ材や接着剤を介して被着形成することも可能である。   Furthermore, the sealing resin 6 is applied to the surface of the insulating layer 1 on which the electronic component 5 is mounted and cured, or the insulating material of the same type as the insulating layer 1, other insulating materials, or a metal with good heat dissipation, etc. The electronic component 5 can be hermetically sealed by bonding the lid made of the above with an adhesive such as glass, resin, or brazing material, whereby the wiring board A can be manufactured. Further, if necessary, various heat sinks can be attached to the wiring board A via a brazing material or an adhesive.

このようにして作製した本発明の配線基板は、複数の絶縁層を積層してなる絶縁基板からなり、該絶縁基板の少なくとも表面に配線層を具備する配線基板であって、前記絶縁基板の表面に配置された絶縁層が、ガラス及び結晶相を含み、厚みが100μm以下のガラスセラミック焼結体からなり、前記絶縁基板の断面におけるボイドの面積占有率が3%以下、1質量%HF水溶液に1分間浸漬した際の重量減少が3μg/mm以下とすることにより、めっき処理後においても高い絶縁性を確保することができる。 The wiring board of the present invention thus produced is an insulating board formed by laminating a plurality of insulating layers, and has a wiring layer on at least the surface of the insulating board, and the surface of the insulating board The insulating layer disposed on the substrate is made of a glass ceramic sintered body having a glass and a crystal phase and a thickness of 100 μm or less, and the void area occupancy in the cross-section of the insulating substrate is 3% or less. By setting the weight loss when immersed for 1 minute to 3 μg / mm 2 or less, high insulation can be ensured even after the plating treatment.

まず、表1に示す組成を有するガラス粉末を準備し、粒径(D50)の異なるガラス粉末およびセラミック粉末を表2に従い秤量、混合し、この混合物にアクリル系樹脂からなるバインダ、可塑剤、トルエンを添加し、スラリーを調製した後、このスラリーを用いてドクターブレード法により焼成後の厚みが15〜100μmとなるようにシート状成形体を作製した。

Figure 2006222307
First, glass powder having the composition shown in Table 1 is prepared, glass powder and ceramic powder having different particle diameters (D50) are weighed and mixed according to Table 2, and a binder made of an acrylic resin, a plasticizer, and toluene are mixed into this mixture. Was added to prepare a slurry, and a sheet-like molded body was prepared using the slurry by a doctor blade method so that the thickness after firing was 15 to 100 μm.
Figure 2006222307

次に、該シート状成形体の所定位置にビアホールを形成し、銅を主成分とする導体ペーストを充填した後、スクリーン印刷法により銅を主成分とする導体ペーストを用いてシート状成形体の表面に焼成後の厚みが5μmとなるような配線パターンを形成した。   Next, after forming a via hole at a predetermined position of the sheet-like molded body and filling a conductor paste mainly composed of copper, the sheet-like molded body is formed using the conductor paste mainly composed of copper by a screen printing method. A wiring pattern having a thickness of 5 μm after firing was formed on the surface.

そして、前記配線パターンを形成したシート状成形体を位置合わせしながら複数枚数積層、熱圧着し焼成前の生絶縁基板を作製した。このとき、該生絶縁基板の表面に表3に示す厚みのシート状成形体を配置した。   Then, while aligning the sheet-like molded body on which the wiring pattern was formed, a plurality of sheets were laminated and thermocompression bonded to produce a raw insulating substrate before firing. At this time, a sheet-like molded body having a thickness shown in Table 3 was disposed on the surface of the raw insulating substrate.

この生積層をN/HO雰囲気中、700℃で脱バインダ処理した後、200℃/時間で昇温し、N/HO雰囲気中、900℃で1時間焼成して銅を主成分とする配線層を具備する絶縁基板からなる配線基板を作製し、さらに、前処理としてHF水溶液処理を含むNi−Auめっきを施した。なお、この際のめっき厚みはNi:3μm、Au:0.5μmとした。 During this raw laminated N 2 / H 2 O atmosphere, after binder removal treatment at 700 ° C., the temperature was raised at 200 ° C. / time, in N 2 / H 2 O atmosphere, copper and calcined 1 hour at 900 ° C. A wiring substrate made of an insulating substrate having a wiring layer as a main component was produced, and Ni-Au plating including HF aqueous solution treatment was applied as a pretreatment. The plating thickness at this time was set to Ni: 3 μm and Au: 0.5 μm.

こうして、表層にNi−Auめっきを施した配線層を有する薄層の絶縁層を配置した配線基板を作製した。   In this way, a wiring board having a thin insulating layer having a wiring layer with Ni—Au plating on the surface layer was prepared.

ここで絶縁層の厚み方向に対向し、かつ1mm□の大きさを有する配線パットを30個用いて、前記表層にNi−Auめっきを施した配線層を有する薄層の絶縁層の絶縁抵抗を測定した。測定結果の最低値を表2に示す。   Here, the insulation resistance of the thin insulating layer having the wiring layer with the Ni—Au plating on the surface layer is used by using 30 wiring pads facing the insulating layer in the thickness direction and having a size of 1 mm □. It was measured. Table 2 shows the minimum measurement results.

一方、前記シート状成形体に配線層およびビアホールを形成せずに、前述と同様の方法にて、積層、熱圧着を行い、絶縁層のみからなるガラスセラミック焼結体を作製した。   On the other hand, without forming a wiring layer and a via hole in the sheet-like molded body, lamination and thermocompression bonding were performed in the same manner as described above to produce a glass ceramic sintered body consisting only of an insulating layer.

得られた焼結体を鏡面研磨し、走査型電子顕微鏡(SEM)写真を撮影し、画像解析装置を用いてボイド率を算出した。また、該SEM写真から略球状のボイドと孤立したボイドの面積と全ボイドの面積を測定し、略球状のボイド面積率と孤立したボイドの面積率を算出した。結果を表2に示す。   The obtained sintered body was mirror-polished, a scanning electron microscope (SEM) photograph was taken, and the void ratio was calculated using an image analyzer. Further, from the SEM photograph, the area of substantially spherical voids and isolated voids and the area of all voids were measured, and the area ratio of substantially spherical voids and the area of isolated voids were calculated. The results are shown in Table 2.


このガラスセラミック焼結体を、1質量%HF水溶液に1分間浸漬し、その前後の重量変化を測定し、表面積で規格化することにより、1質量%HF水溶液に1分間浸漬した際の重量減少を測定した。結果を表2に示す。

Figure 2006222307

This glass ceramic sintered body is immersed in a 1% by mass HF aqueous solution for 1 minute, the weight change before and after that is measured, and normalized by the surface area, thereby reducing the weight when immersed in a 1% by mass HF aqueous solution for 1 minute. Was measured. The results are shown in Table 2.
Figure 2006222307

本発明の配線基板である試料No.2〜14においては、絶縁基板の断面におけるボイドの面積占有率が3%以下、1質量%HF水溶液に1分間浸漬した際の重量減少が3μg/mm以下とすることにより、めっき後においても絶縁基板表面に配置された絶縁層の厚み方向の電気抵抗が、10Ω/mm以上と高い絶縁性を示した。 Sample No. which is the wiring board of the present invention. 2 to 14, the void area occupancy in the cross section of the insulating substrate is 3% or less, and the weight loss when immersed in a 1% by mass HF aqueous solution for 1 minute is 3 μg / mm 2 or less, so that even after plating. The electric resistance in the thickness direction of the insulating layer disposed on the surface of the insulating substrate showed a high insulating property of 10 9 Ω / mm 2 or more.

この中で、Cガラスを使用し、ボイド率が2%以下、かつ1質量%HF水溶液に1分間浸漬した際の重量減少が2μg/mm以下である試料No.5〜13は、電気抵抗が1011Ω/mm以上と特に絶縁性に優れていた。 Among them, sample No. 2 using C glass, having a void ratio of 2% or less and a weight loss of 2 μg / mm 2 or less when immersed in a 1% by mass HF aqueous solution for 1 minute. Nos. 5 to 13 were particularly excellent in insulation with an electric resistance of 10 11 Ω / mm 2 or more.

一方、絶縁基板の断面におけるボイド面積率と1質量%HF水溶液に1分間浸漬した際の重量減少が本発明の範囲よりも大きい試料No.1では、絶縁層内部へのめっき液の浸透が多く、絶縁基板表面に配置された絶縁層の厚み方向の電気抵抗が、10Ω/mmよりも低いものとなった。 On the other hand, in the cross section of the insulating substrate, the sample area No. in which the void area ratio and the weight loss when immersed in a 1 mass% HF aqueous solution for 1 minute are larger than the range of the present invention. In No. 1, there was much penetration of the plating solution into the insulating layer, and the electric resistance in the thickness direction of the insulating layer disposed on the surface of the insulating substrate was lower than 10 9 Ω / mm 2 .

本発明の配線基板の構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the wiring board of this invention.

符号の説明Explanation of symbols

1・・・絶縁基板
2・・・配線層
3・・・ビアホール導体
4・・・接続用電極
5・・・電子部品
6・・・封止樹脂
7・・・ワイヤボンディング
8・・・半田
9・・・半田
10・・接着剤
A・・・配線基板
B・・・プリント基板
DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Wiring layer 3 ... Via-hole conductor 4 ... Connection electrode 5 ... Electronic component 6 ... Sealing resin 7 ... Wire bonding 8 ... Solder 9 ... Solder 10 ... Adhesive A ... Wiring board B ... Printed circuit board

Claims (7)

複数の絶縁層を積層してなる絶縁基板からなり、該絶縁基板の少なくとも表面に配線層を具備する配線基板であって、前記絶縁基板の表面が、ガラス及び結晶相を含み、厚みが100μm以下のガラスセラミック焼結体からなり、前記絶縁基板の断面におけるボイドの面積占有率が3%以下、1質量%HF水溶液に1分間浸漬した際の重量減少が3μg/mm以下であることを特徴とする配線基板。 A wiring board comprising a plurality of insulating layers laminated and having a wiring layer on at least a surface of the insulating board, the surface of the insulating board including glass and a crystal phase, and a thickness of 100 μm or less The void area occupancy in the cross section of the insulating substrate is 3% or less, and the weight loss when immersed in a 1% by mass HF aqueous solution for 1 minute is 3 μg / mm 2 or less. Wiring board. 前記ボイドのうち、略球状のボイドの占有面積が全体の75%以上であることを特徴とする請求項1記載の配線基板。 2. The wiring board according to claim 1, wherein an area occupied by substantially spherical voids is 75% or more of the voids. 前記ボイドのうち、孤立して存在するボイドの占有面積が全体の75%以上であることを特徴とする請求項1又は請求項2記載の配線基板。 3. The wiring board according to claim 1, wherein an occupied area of the voids isolated from the voids is 75% or more of the whole. 4. 前記ガラスセラミック焼結体が、実質的にアルカリ金属酸化物を含有しないことを特徴とする請求項1〜4のいずれかに記載の配線基板。 The wiring substrate according to any one of claims 1 to 4, wherein the glass ceramic sintered body does not substantially contain an alkali metal oxide. 前記表面に配置された絶縁層の厚み方向の電気抵抗が、10Ω/mm以上であることを特徴とする請求項1〜3のいずれかに記載の配線基板。 The wiring substrate according to claim 1, wherein an electrical resistance in a thickness direction of the insulating layer disposed on the surface is 10 9 Ω / mm 2 or more. 前記配線層が、金、銀及び銅の少なくとも1種を主成分とすることを特徴とする請求項1〜5のいずれかに記載の配線基板。 The wiring board according to claim 1, wherein the wiring layer contains at least one of gold, silver, and copper as a main component. 前記絶縁基板の表面に配設された配線層の表面に、めっき層が被着形成されていることを特徴とする請求項1〜6のいずれかに記載の配線基板。

The wiring board according to claim 1, wherein a plating layer is deposited on the surface of the wiring layer disposed on the surface of the insulating substrate.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085040A (en) * 2006-09-27 2008-04-10 Kyocera Corp Multilayer substrate and its manufacturing method
JP2010055157A (en) * 2008-08-26 2010-03-11 Panasonic Corp Intersection situation recognition system
JP2010283319A (en) * 2009-06-03 2010-12-16 Samsung Electro-Mechanics Co Ltd Multilayer ceramic substrate and method of manufacturing the same
EP2790215A4 (en) * 2011-12-08 2015-08-12 Ngk Insulators Ltd Substrate for large-capacity module, and manufacturing method for said substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175496A (en) * 1987-01-16 1988-07-19 旭硝子株式会社 Thick film circuit board
JPH03193656A (en) * 1989-12-21 1991-08-23 Hitachi Chem Co Ltd Production of ceramic substrate
JPH04206988A (en) * 1990-11-30 1992-07-28 Kyocera Corp High insulation ceramic board and manufacture thereof
JP2003342060A (en) * 2002-05-23 2003-12-03 Kyocera Corp Glass ceramic sintered compact and wiring board
JP2004235347A (en) * 2003-01-29 2004-08-19 Kyocera Corp Insulating ceramics and multilayer ceramic substrate using the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175496A (en) * 1987-01-16 1988-07-19 旭硝子株式会社 Thick film circuit board
JPH03193656A (en) * 1989-12-21 1991-08-23 Hitachi Chem Co Ltd Production of ceramic substrate
JPH04206988A (en) * 1990-11-30 1992-07-28 Kyocera Corp High insulation ceramic board and manufacture thereof
JP2003342060A (en) * 2002-05-23 2003-12-03 Kyocera Corp Glass ceramic sintered compact and wiring board
JP2004235347A (en) * 2003-01-29 2004-08-19 Kyocera Corp Insulating ceramics and multilayer ceramic substrate using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085040A (en) * 2006-09-27 2008-04-10 Kyocera Corp Multilayer substrate and its manufacturing method
JP2010055157A (en) * 2008-08-26 2010-03-11 Panasonic Corp Intersection situation recognition system
JP2010283319A (en) * 2009-06-03 2010-12-16 Samsung Electro-Mechanics Co Ltd Multilayer ceramic substrate and method of manufacturing the same
EP2790215A4 (en) * 2011-12-08 2015-08-12 Ngk Insulators Ltd Substrate for large-capacity module, and manufacturing method for said substrate

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