JP2004231453A - Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate - Google Patents

Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate Download PDF

Info

Publication number
JP2004231453A
JP2004231453A JP2003020861A JP2003020861A JP2004231453A JP 2004231453 A JP2004231453 A JP 2004231453A JP 2003020861 A JP2003020861 A JP 2003020861A JP 2003020861 A JP2003020861 A JP 2003020861A JP 2004231453 A JP2004231453 A JP 2004231453A
Authority
JP
Japan
Prior art keywords
glass
sintered body
mass
ceramic sintered
less
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003020861A
Other languages
Japanese (ja)
Inventor
Toshifumi Azuma
登志文 東
Shinya Kawai
信也 川井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003020861A priority Critical patent/JP2004231453A/en
Publication of JP2004231453A publication Critical patent/JP2004231453A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Compositions Of Oxide Ceramics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Inorganic Insulating Materials (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate which can be baked at ≤1,050°C, can form a wiring layer containing a low-resistance metal through simultaneous baking, and shows a high packaging reliability. <P>SOLUTION: The wiring substrate has an insulating substrate and a wiring layer. The insulating substrate is a glass ceramic sintered compact obtained by mixing at least, by mass, 60-99% glass powder containing 30-70% SiO<SB>2</SB>, 5-30% Al<SB>2</SB>O<SB>3</SB>, 3-25% MgO, 3-25% BaO, 1-15% B<SB>2</SB>O<SB>3</SB>and 1-15% ZnO with 1-40% at least one filler powder chosen from the group consisting of cordierite, mullite, anorthite, slawsonite, celsian and quartz glass, molding the mixture, and baking it at ≤1,050°C in atmospheric or nitrogen atmosphere. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子収納用パッケージ、多層配線基板等に適用される配線基板等に最適なガラスセラミック組成物およびガラスセラミック焼結体に関するものであり、また、これを絶縁基板として用いた配線基板とその実装構造に関するものである。
【０００２】
【従来技術】
近年、高度情報化時代を迎え、情報通信技術が急速に発達し、それに伴い、半導体素子等の高速化、大型化が図られ、配線層においても、信号の伝送損失を低減する上で配線層の低抵抗化と絶縁基板の低誘電率化が求められている。そこで、１０００℃以下での焼成によって緻密化でき、銅、銀または金等の低抵抗金属を主成分とする配線層との同時焼成が可能で、かつ誘電率の低いガラスセラミックスを絶縁層とする配線基板が提案されている。
【０００３】
特に、Ｓｉを主体とする半導体素子に関して、素子の高速化に伴い、近年機械的強度が低下する傾向が見られている。そこで、半導体素子を半導体素子収納用パッケージ上に実装（以下、一次実装と称す。）した場合、素子とパッケージ間の熱膨張係数のミスマッチにより発生する熱応力により、半導体素子が破壊してしまうといった問題が懸念されている。さらに、素子が大型化すると熱応力がそれに伴い大きくなるため、素子が破壊する危険性が増大する。
【０００４】
そのため、一次実装に関わる熱応力を低減するために、パッケージの熱膨張係数をＳｉの熱膨張係数（２〜４×１０−６／℃：４０−４００℃）に合わせることが求められている。
【０００５】
例えば、特公平４−５８１９８公報では、ムライト、石英ガラス、ほう珪酸ガラスからなるガラスセラミック焼結体を絶縁材料とすることで、低熱膨張係数の多層セラミック回路基板が得られることが記載されている。
【０００６】
例えば、特開平５−２５４９２３公報では、ＳｉＯ２、Ｂ２Ｏ３、Ｋ２Ｏ、Ａｌ２Ｏ３からなる硼珪酸ガラスとアルミナ、コージェライト、石英ガラスとを組み合わせることにより、低抵抗配線が可能な低熱膨張係数のセラミック基板が得られることが記載されている。
【０００７】
【特許文献１】
特公平４−５８１９８号公報
【特許文献２】
特開平５−２５４９２３号公報
【０００８】
【発明が解決しようとする課題】
しかしながら、上述したような従来のガラスセラミック焼結体は、低い熱膨張係数を実現していることによって一次実装の信頼性を向上できるが、逆に、熱膨張係数が１５〜２０×１０−６／℃程度と非常に大きいプリント配線基板で構成されるマザーボード上に実装（以下、二次実装と称す。）する際には、熱膨張係数のミスマッチが非常に大きくなるため、二次実装信頼性を確保することが困難となる問題があった。
【０００９】
従って、本発明は、銀、銅、金等の低抵抗金属との同時焼成が可能であり、低い熱膨張係数、低い誘電率を有しつつ低ヤング率の焼結体を形成するガラスセラミック組成物、およびガラスセラミック焼結体と、かかる焼結体を用い、一次実装信頼性とともに、高い二次実装信頼性を確保できる配線基板とその実装構造を提供することを目的とする。
【００１０】
【課題を解決するための手段】
本発明者らは、上記課題に対して検討した結果、少なくともＳｉＯ２、Ａｌ２Ｏ３、ＭｇＯ、ＢａＯ、Ｂ２Ｏ３、ＺｎＯを所定の比率で含むガラス粉末に対して、フィラーとして少なくともコーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種を所定の比率で添加し、混合し、成形後、１０５０℃以下で焼成し、所定の結晶相を析出または分散させることによって、低熱膨張率化、低誘電率化とともに、低ヤング率化を同時に達成できること、また低熱膨張係数、低誘電率とともに低ヤング率を有する焼結体を絶縁基板とする配線基板が、一次実装信頼性とともに、二次実装信頼性を高めることができることを見出し、本発明に至った。
【００１１】
すなわち、本発明のガラスセラミック組成物は、少なくとも、ＳｉＯ２ ３０〜７０質量％、Ａｌ２Ｏ３ ５〜３０質量％、ＭｇＯ ３〜２５質量％、ＢａＯ ３〜２５質量％、Ｂ２Ｏ３ １〜１５質量％、ＺｎＯ １〜１５質量％、を含有するガラス粉末６０〜９９質量％とコーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％とを含有することを特徴とするものである。
【００１２】
なお、前記ガラス粉末は、１０５０℃以下の熱処理を行うことにより、少なくともセルジアンを結晶相として析出することが望ましい。それによって、低熱膨張化、低誘電率化、低ヤング率化を図ることができる。また、上記セルジアンは少なくとも単斜晶を含むことが望ましい。また、かかる組成物は、ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）の含有量がそれぞれ０．１質量％以下に抑制されていることが耐環境負荷、耐薬品性を向上させる上で望ましい。
【００１３】
また、本発明のガラスセラミック焼結体は、少なくともセルジアンを結晶相として含有し、４０〜４００℃における熱膨張係数が５×１０−６／℃以下、誘電率が７以下、ヤング率が１５０ＧＰａ以下であることを特徴とするものである。
【００１４】
ここで、かかる焼結体は、結晶相として、さらに、コーディエライト、ガーナイト、スピネル、ムライト、アノーサイト、スラウソナイト、セルジアンの群から選ばれる少なくとも１種を含有することが望ましく、さらに抗折強度が１５０ＭＰａ以上であることが望ましく、さらに、ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）の含有量がそれぞれ０．１質量％以下であることが望ましいものである。
【００１５】
また、かかるガラスセラミック焼結体は、少なくとも、ＳｉＯ２ ３０〜７０質量％、Ａｌ２Ｏ３ ５〜３０質量％、ＭｇＯ ３〜２５質量％、ＢａＯ ３〜２５質量％、Ｂ２Ｏ３ １〜１５質量％、ＺｎＯ １〜１５質量％、を含有するガラス粉末６０〜９９質量％と、コーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％とを混合、成形し、大気中あるいは窒素雰囲気中で１０５０℃以下の温度にて焼成して得られることを特徴とするものである。
【００１６】
また、本発明の配線基板は、絶縁基板の表面および／または内部に、低抵抗金属を含有する配線層を配設してなり、前記絶縁基板が、上記のガラスセラミック焼結体からなることを特徴とするものであり、かかる配線基板の表面および／または表面に設けた凹部にＳｉを主体とする半導体素子を載置してなることが望ましい。
【００１７】
また、上記の配線基板を、有機樹脂を含有する絶縁基板を具備するプリント配線基板の表面に実装することによって、一次実装信頼性および二次実装信頼性に優れた実装構造を提供できる。
【００１８】
【発明の実施の形態】
本発明のガラスセラミック組成物は、構成成分として、少なくとも、ＳｉＯ２３０〜７０質量％、特に４５〜６０質量％、Ａｌ２Ｏ３ ５〜３０質量％、特に１０〜２５質量％、ＭｇＯ ３〜２５質量％、特に５〜２０質量％、ＢａＯ ３〜２５質量％、特に５〜２０質量％、Ｂ２Ｏ３ １〜１５質量％、特に３〜１２質量％、ＺｎＯ １〜１５質量％、特に２〜１０質量％を含有するガラス粉末６０〜９９質量％、特に６５〜９７質量％、最適には７０〜９５質量％と、コーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％、特に３〜３５質量％、最適には５〜３０質量％とを含有することを特徴とするものである。
【００１９】
ここで、上記ガラス粉末は、該組成物を銅、あるいは銀、金といった低抵抗導体と同時焼成可能な温度である１０５０℃以下の低温で焼結させるために必要であり、ガラス粉末の軟化流動により該組成物を低温で焼結可能とせしめるものである。ガラス粉末の量が、前記範囲よりも少ない場合には、該組成物を１０５０℃以下で焼結させることが困難となり、逆に前記範囲よりも多い場合には、該組成物を焼成した場合に、その原型を保つことが困難となる。
【００２０】
さらに、ＳｉＯ２は、ガラスのネットワークフォーマーであり、かつセルジアン、コーディエライト等のＳｉＯ２を構成成分として含有する結晶相、特にセルジアンをガラスから析出せしめるための必須成分である。ＳｉＯ２が前記範囲よりも少ないと、前記結晶相の析出量が不十分となり、前記ガラスセラミック焼結体の特性を望ましい範囲内とすることが困難となり、逆に前記範囲よりも多い場合には、ガラスの軟化温度が上昇し１０５０℃以下の低温焼成が困難となる。
【００２１】
また、Ａｌ２Ｏ３は、ガラスのヤング率や耐薬品性を向上させる成分であると同時に、セルジアン、コーディエライト、ガーナイト、スピネル等のＡｌ２Ｏ３を構成成分として含有する結晶相、特にセルジアンをガラスから析出せしめるための必須成分である。Ａｌ２Ｏ３が前記範囲よりも少ない場合には、前記結晶相の析出量が不十分となり、前記ガラスセラミック焼結体の特性を望ましい範囲内とすることが困難となり、逆に前記範囲よりも多い場合には、ガラスの軟化温度が上昇し１０５０℃以下の低温焼成が困難となると同時に、前記ガラスセラミック焼結体のヤング率が上昇し、高い二次実装信頼性を確保することが困難となる。
【００２２】
また、Ｂ２Ｏ３は、ガラスのネットワークフォーマーであると同時に、軟化温度、溶解温度を低下せしめる働きがあり、Ｂ２Ｏ３が前記範囲よりも少ないと、ガラスの溶解温度が上昇しすぎて、工業的に安価に製造することが困難となると同時にガラスの軟化温度が上昇し１０５０℃以下の低温焼成が困難となる。逆に前記範囲よりも多い場合には、ガラスの軟化温度が低下し前記ガラスセラミック焼結体の原型を保つことが困難となると同時に、前記ガラスセラミック焼結体の耐薬品性が著しく低下する。
【００２３】
また、ＭｇＯは、コーディエライト、スピネル等のＭｇＯを構成成分として含有する結晶相の必須成分である。ＭｇＯが前記範囲よりも多い場合には、前記ガラスセラミック焼結体のヤング率が上昇し、高い二次実装信頼性を確保することが困難となる。また、ＭｇＯが上記範囲より少ない場合には、結晶相の析出が不十分となり目的とする特性が得られない。
【００２４】
また、ＢａＯは、セルジアンを析出せしめるための必須成分であり、且つガラスの軟化温度を低下せしめる働きがある。ＢａＯが前記範囲よりも少ない場合には、前記結晶相の析出量が不十分となり、前記ガラスセラミック焼結体の特性を望ましい範囲内とすることが困難となり、逆に前記範囲よりも多い場合には、ガラスの軟化温度が低下し前記ガラスセラミック焼結体の原型を保つことが困難となると同時に、前記ガラスセラミック焼結体の耐薬品性が著しく低下する。
さらに、ＺｎＯは、ガラスの軟化温度を低下せしめると同時にガーナイト等のＺｎＯを構成成分として含有する結晶相をガラスから析出せしめるための必須成分である。ＺｎＯが前記範囲よりも少ない場合には、前記結晶相の析出量が不十分となり、前記ガラスセラミック焼結体の特性を望ましい範囲内とすることが困難となり、逆に前記範囲よりも多い場合には、ガラスの軟化温度が低下し前記ガラスセラミック焼結体の原型を保つことが困難となると同時に、前記ガラスセラミック焼結体の耐薬品性が著しく低下する。
【００２５】
なお、前記ガラス粉末中には、前記成分量が本発明の範囲を逸脱しない範囲で、ＣａＯ、ＳｒＯ、ＺｒＯ２、ＳｎＯ２、希土類酸化物の他の成分を１０質量％以下、特に７質量％以下、さらには５質量％以下の範囲で含有してもよく、これにより、前記ガラスセラミック焼結体の焼結性や特性を微調整することが可能となる。
【００２６】
但し、ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）は、環境への負荷が大きく、また耐薬品性や絶縁性の観点から全量中、それぞれ０．１質量％以下に抑制されていることが望ましい。
【００２７】
さらに、本発明においては、前記ガラス粉末が、１０５０℃以下の熱処理を行うことにより少なくともセルジアンを結晶相として析出することが、前記ガラスセラミック焼結体の熱膨張係数、誘電率、ヤング率を低下せしめることが可能となるため望ましい。さらには、セルジアン結晶相を粉末としてではなくガラス中から析出せしめることにより、焼結性を向上させる効果もあるため、前記ガラスセラミック焼結体のヤング率を低下させつつも、抗折強度を向上せしめることが可能となる。
（フィラー）
一方、フィラーとなる、コーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種の粉末は、該組成物を焼成してなるガラスセラミック焼結体の熱膨張係数、誘電率を低くするために特に有効な成分であり、なかでもムライト、アノーサイト、スラウソナイトの群から選ばれる少なくとも１種は、抗折強度の向上にも効果的であり、コーディエライト、石英ガラスは熱膨張係数、誘電率、ヤング率を低下させる効果が特に著しいものである。
【００２８】
これらの粉末が前記範囲内よりも少ない場合には、前記ガラスセラミック焼結体の特性を望ましい範囲内とすることが困難となり、逆に前記範囲よりも多い場合には、該組成物を１０５０℃以下で焼結せしめることが困難となる。
【００２９】
なお、前記ガラスセラミック組成物中には、上記フィラー量が本発明の量を逸脱しない範囲で、ＳｉＯ２、Ｃａ２ＭｇＳｉ２Ｏ７、Ｓｒ２ＭｇＳｉ２Ｏ７、Ｂａ２ＭｇＳｉ２Ｏ７、ＺｒＯ２、ＺｎＯ、ＭｇＳｉＯ３、Ｍｇ２ＳｉＯ４、ＺｒＳｉＯ４、Ｚｎ２ＳｉＯ４、ＣａＭｇＳｉ２Ｏ６、Ｚｎ２Ａｌ４Ｓｉ５Ｏ１８、ＣａＳｉＯ３、ＳｒＳｉＯ３、ＢａＳｉＯ３の群から選ばれる他のフィラー粉末を、総量が１５質量％以下、特に１０質量％以下、さらには５質量％以下の範囲で含有してもよく、これにより、前記ガラスセラミック焼結体の焼結性や特性を微調整することが可能となる。
【００３０】
本発明のガラスセラミック焼結体は、少なくともセルジアンを結晶相として含有し、４０〜４００℃における熱膨張係数が５×１０−６／℃以下、特に４．８×１０−６／℃以下、最適には４．５×１０−６／℃以下、誘電率が７以下、特に６．５以下、最適には６以下、ヤング率が１５０ＧＰａ以下、特に１４０ＧＰａ以下、最適には１３０ＧＰａ以下であることを特徴とするものである。さらには、ＪＩＳＲ１６０１に基づく３点曲げ強度が１５０ＭＰａ以上であることが望ましい。
【００３１】
ここで、上記セルジアン結晶相は、前記ガラスセラミック焼結体の低熱膨張化、低誘電率化、低ヤング率化を達成するための必須成分である。このセルジアン結晶は、原料粉末として出発組成中に含有せしめることもできるが、最適には、出発組成中にはセルジアンは添加せず、ガラス粉末中から析出させることにより、低ヤング率とさらに高い抗折強度とを同時に実現させることができるため望ましい。
【００３２】
また、このガラスセラミック焼結体の熱膨張係数は、Ｓｉを主体とする半導体素子を、前記ガラスセラミック焼結体を絶縁基板として用いた配線基板上に一次実装する際に絶縁基板と半導体素子との熱膨張係数のミスマッチにより生じる熱応力を低減するために、Ｓｉの熱膨張係数の値に近いものでなくてはならず、前記範囲よりもその値が大きい場合には、一次実装の信頼性を確保することが困難となる。
【００３３】
さらに、誘電率は、信号遅延時間を短縮するために低いことが望ましく、前記範囲よりも大きいと、前記配線基板の遅延時間が長くなり性能が低下する。
【００３４】
また、ヤング率が低いということは、該ガラスセラミック焼結体が応力により変形しやすいことを意味する。従って、焼結体の熱膨張係数を半導体素子に整合させるために低熱膨張化することによって、プリント配線基板への二次実装における熱膨張差が大きくなっても、二次実装部において発生する熱応力を焼結体の変形により緩和することができ、二次実装信頼性を向上させることができる。従って、ヤング率が前記範囲よりも大きいと、二次実装信頼性が著しく低下する。
【００３５】
さらに、本発明においては、結晶相として、前記セルジアン以外に、さらに、コーディエライト、ガーナイト、スピネル、ムライト、アノーサイト、スラウソナイトの群から選ばれる少なくとも１種を含有せしめることによって、該ガラスセラミック焼結体の抗折強度を向上させることができる。特に、ムライト、アノーサイト、スラウソナイト、セルジアンの群から選ばれる少なくとも１種は、抗折強度向上のみならず、熱膨張係数、誘電率を低下させるためにも望ましい。
【００３６】
さらに、本発明においては、ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）の含有量がそれぞれ０．１質量％以下に抑制されていることが、対環境負荷、耐薬品性、絶縁性の観点から望ましい。
【００３７】
また、上記焼結体中には、本発明を逸脱しない範囲で、ＳｉＯ２、Ｃａ２ＭｇＳｉ２Ｏ７、Ｓｒ２ＭｇＳｉ２Ｏ７、Ｂａ２ＭｇＳｉ２Ｏ７、ＺｒＯ２、ＺｎＯ、ＭｇＳｉＯ３、Ｍｇ２ＳｉＯ４、ＺｒＳｉＯ４、Ｚｎ２ＳｉＯ４、ＣａＭｇＳｉ２Ｏ６、Ｚｎ２Ａｌ４Ｓｉ５Ｏ１８、ＣａＳｉＯ３、ＳｒＳｉＯ３、ＢａＳｉＯ３の群から選ばれる他の結晶相を、総量が１５質量％以下、特に１０質量％以下、さらには５質量％以下の範囲で含有してもよく、これにより、前記ガラスセラミック焼結体の焼結性や特性を制御することが可能となる。
【００３８】
上記のガラスセラミック焼結体を製造するには、まず、構成成分として、少なくとも、ＳｉＯ２ ３０〜７０質量％、特に４５〜６０質量％、Ａｌ２Ｏ３ ５〜３０質量％、特に１０〜２５質量％、ＭｇＯ ３〜２５質量％、特に５〜２０質量％、ＢａＯ ３〜２５質量％、特に５〜２０質量％、Ｂ２Ｏ３ １〜１５質量％、特に３〜１２質量％、ＺｎＯ １〜１５質量％、特に２〜１０質量％を含有するガラス粉末６０〜９９質量％、特に６５〜９７質量％、最適には７０〜９５質量％と、コーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％、特に３〜３５質量％、最適には５〜３０質量％の割合で混合する。
【００３９】
ここで、前記ガラス粉末、フィラー粉末の組成および前記ガラス粉末の組成が前記範囲内から外れる場合には、前述のように、該ガラスセラミック焼結体の特性が望ましい範囲とならない。
【００４０】
そして、この混合物に、有機バインダ、溶媒、必要に応じて可塑剤を添加、混合し、プレス成形、押出形成、射出成形、鋳込み成形、テープ成形の群から選ばれる少なくとも１種の成形方法によって所定形状に成形する。
【００４１】
そして、該成形体を、４５０〜７５０℃で脱バインダ処理した後、酸化性雰囲気あるいは窒素雰囲気中、１０５０℃以下、特に７００〜１０００℃、さらに８００〜９５０℃の温度で焼成することにより、本発明のガラスセラミック焼結体を作製することができる。
【００４２】
ガラスセラミック焼結体を後述する配線基板の絶縁基板として用いる際に、導体材料として、銀、金を用いる場合は、導体は酸化しないため、大気雰囲気中で焼成することが望ましく、銅を用いる場合には、銅の酸化を抑制する為に窒素雰囲気中にて焼成することが望ましい。
【００４３】
なお、前記ガラスセラミック焼結体は、還元雰囲気下でも焼成することは可能であるが、コスト、安全性の面から、望ましくは酸化性雰囲気あるいは窒素雰囲気中での焼成が望ましい。
【００４４】
また、焼結体中に上述した特定の結晶相の析出を促進するためには、脱バインダ処理後の昇温速度を５０℃／時間以上、特に１００℃／時間以上とすることが望ましく、また、焼成温度での保持時間を０．０２〜１０時間、特に０．２〜２時間とすることが望ましい。
【００４５】
さらに、本発明の配線基板は、絶縁基板の表面および／または内部に低抵抗金属を含有する配線層が配設されたものであり、前記絶縁基板が、上記のガラスセラミック焼結体からなるものである。
【００４６】
上記ガラスセラミック焼結体を絶縁基板とすることによって、銅、銀、金の群から選ばれる少なくとも１種の低抵抗金属を含有する配線層との同時焼成が可能となる。
【００４７】
また、この配線基板の表面には、本発明においては、前記配線基板の表面および／または表面に設けた凹部に、Ｓｉを主体とする半導体素子を載置してなることが、一次実装信頼性を確保する上で望ましい。
【００４８】
上述したガラスセラミック焼結体を絶縁基板として用いた本発明の配線基板について、その好適例であるＳｉを主体とする半導体素子等の素子をフリップチップ実装によって搭載したＢＧＡ（ボールグリッドアレイ）型の電気素子収納用パッケージと、該パッケージをプリント配線基板上に実装した場合の概略断面図である図１をもとに説明する。
【００４９】
図１によれば、電気素子収納用パッケージＡは、複数の絶縁層１ａ〜１ｄからなる絶縁基板１の表面および／あるいは内部に配線層２が形成されている。また、図１によれば、絶縁層１ａ〜１ｄ間に形成される銅、銀、金の群から選ばれる少なくとも１種の低抵抗金属を含有する配線層２、および配線層２同士を電気的に接続する銅、銀、金の群から選ばれる少なくとも１種の低抵抗金属を含有するビアホール導体３が形成されている。
【００５０】
さらに、パッケージＡの下面には複数の接続用電極４Ａが配列されており、絶縁基板１の上面中央部には、半導体素子等の電気素子５が半田６を介して絶縁基板１上にフリップチップ実装により接着固定されると同時に、パッケージＡと電気的に接続される。
【００５１】
また、電気素子５とパッケージＡとの間は、一次実装信頼性を高める為に熱硬化性樹脂を含有するアンダーフィル７が注入され、硬化されている。さらに、電気素子５と、絶縁基板１の下面に形成された複数の接続用電極４Ａとは、半田６、配線層２およびビアホール導体３を介して電気的に接続されている。
【００５２】
一方、プリント配線基板Ｂは、４０〜４００℃における熱膨張係数が１５〜２０×１０−６／℃の絶縁基板の上面に、接続用電極４Ｂが接続用電極４Ａと対を成すように形成されている。そして、接続用電極４Ａ、４Ｂ間は、共晶半田９、高温半田ボール８を介して電気的に接続される。
【００５３】
本発明によれば、絶縁基板１を、前述したような、少なくともセルジアンを結晶相として含有し、４０〜４００℃における熱膨張係数が５×１０−６／℃以下、誘電率が７以下、ヤング率が１５０ＧＰａ以下のガラスセラミック焼結体によって形成することが大きな特徴であり、これによって、絶縁基板１の熱膨張係数、およびヤング率を低下させることができ、パッケージＡの一次実装信頼性とともに、二次実装信頼性を高めることができる。
【００５４】
また、絶縁基板１の誘電率を低下させるとともに、配線層２やビアホール導体３として、銅、銀または金のうちの少なくとも一種の低抵抗金属を主成分として含有するために、配線層２を低抵抗化でき、信号の遅延を小さくできる。
【００５５】
なお、上記図１の例では、Ｓｉ系半導体素子を例示したが、本発明の配線基板は、熱膨張係数が５×１０−６／℃以下の他の電気素子を搭載する配線基板に好適に用いられる。また、図１のパッケージにおいては、素子５は半田６を介して配線層２と接続される場合に好適であるが、素子５と配線層２がワイヤボンディング等によって接続されたものであってもよい。また、素子５は、その上にさらに封止樹脂にて覆う形態であってもよい。また、絶縁基板１にキャビティを形成して素子５を収納し、蓋体によってキャビティを気密封止するものであってもよい。
【００５６】
また、図１においては、パッケージＡとプリント配線基板Ｂとは、高温半田ボール８を介して相互に接続されるＢＧＡ型のパッケージ構造について説明したが、本発明は、リードピンなどを用いずに、パッケージＡとプリント配線基板Ｂとが、半田を介して接続される前記ＢＧＡ、ＬＧＡ、ＬＣＣ型などのタイプの場合において発生する応力が大きく二次実装信頼性が求められることから、この種のパッケージに特に好適に用いられる。その他、樹脂を含有するボール、柱状の半田カラム、樹脂を含有するカラム、さらにはピンにて接続される形態であってももちろん有用性を有する。
【００５７】
次に、本発明の配線基板を製造する方法について、上記パッケージＡを例にすると、前述したようなガラス粉末と、フィラー粉末との混合粉末に対して、適当な有機バインダ、溶媒、必要に応じて可塑剤を添加、混合してスラリーを調製し、これを従来周知のドクターブレード法やカレンダーロール法、あるいは圧延法、プレス成形法等により、シート状に成形する。そして、このシート状成形体に所望によりスルーホールを形成した後、スルーホール内に、銅、銀、金の群から選ばれる少なくとも１種の低抵抗金属を含有する導体ペーストを充填する。そして、シート状成形体表面には、前記導体ペーストを用いてスクリーン印刷法、グラビア印刷法などの公知の印刷手法を用いて配線層の厚みが５〜３０μｍとなるように配線パターンを印刷塗布する。
【００５８】
そして、複数のシート状成形体を位置合わせして積層圧着した後、大気中、または窒素雰囲気中にて脱バインダ処理した後、１０５０℃以下の大気中または窒素雰囲気で焼成することにより、配線基板を作製することができる。
【００５９】
なお、焼成雰囲気については、導体材料として、銀、金を用いる場合は、導体は酸化しないため、大気雰囲気中で焼成することが望ましく、銅を用いる場合には、銅の酸化を抑制する為に窒素雰囲気中にて焼成することが望ましい。
【００６０】
そして、この配線基板の表面に、半導体素子等の電気素子５を搭載し、配線層２と信号の伝達が可能なように接続される。接続方法としては、前述したように、半田を用いたフリップチップ実装や、ワイヤボンディング、さらには配線層２上に直接搭載させて接続させる形態が好適である。
【００６１】
さらに、電気素子５とパッケージＡとの間隙にアンダーフィル材７を充填、硬化したり、素子上にポッティング樹脂を被覆し、硬化させるか、絶縁基板１と同種の絶縁材料や、その他の絶縁材料、あるいは放熱性が良好な金属等からなる蓋体をガラス、樹脂、ロウ材等の接着剤により接合することにより、素子収納用パッケージＡを作製することができる。
【００６２】
また、パッケージＡの下面に、低融点ハンダによって高融点半田ボール８を接続する。そして、このパッケージＡをプリント配線基板Ｂに実装する場合には、プリント配線基板Ｂの表面に、前記パッケージＡの半田ボール８を低融点半田を介してプリント配線基板Ｂの接続用電極４Ｂ上に載置し、半田リフロー処理することによって、パッケージＡをプリント配線基板Ｂ上に二次実装することができる。
【００６３】
【実施例】
（実施例１）
表１に示した組成からなる本発明の４種の平均粒径が２μｍのガラスＡ、Ｂ、Ｃ、Ｄの粉末を準備し、これらのガラス粉末に対して、平均粒径が１〜２μｍの表２に示すフィラー粉末を用いて、表２、３の組成に従い混合した。
【００６４】
そして、この混合物に有機バインダ、可塑剤、トルエンを添加し、スラリーを調製した後、このスラリーを用いてドクターブレード法により厚さ３００μｍのグリーンシートを作製した。さらに、このグリーンシートを所望の厚さになるように複数枚積層し、６０℃の温度で１０ＭＰａの圧力を加えて熱圧着した。
【００６５】
得られた積層体を窒素雰囲気中、７５０℃で脱バインダ処理した後、２００℃／時間で昇温して、大気中で表２、３の条件にて焼成してガラスセラミック焼結体を得た。
【００６６】
得られた焼結体について、焼結体を２ｍｍ□、長さ１８ｍｍに加工し、１０℃／分の速度で焼温しながらレーザー測距計にて寸法変化を測定することにより、４０〜４００℃における熱膨張係数を測定した。また、５０ｍｍ□、厚さ１．０ｍｍに加工し、空洞共振器法にて２ＧＨｚにおける誘電率を測定した。さらに、焼結体を３ｍｍ×４ｍｍ×４０ｍｍに加工し、超音波パルス法にてヤング率を測定した。また、同様のサンプルを用いて、オートグラフを用いＪＩＳＲ−１６０１に基づく３点曲げ抗折強度を測定した。また、焼結体中における結晶相をＸ線回折測定から同定し、主ピーク強度の大きい順に並べた。以上の測定結果を表２、３に示す。
【００６７】
一方、上記４種類のガラスに代わり、表１に示す２種類のガラスＥ、Ｆを用いて同様に評価を行った。また、フィラー粉末として、ＴｉＯ２、ＺｒＯ２を用いて同様の評価を行った。結果を表２、３に示す。
【００６８】
【表１】

Figure 2004231453
【００６９】
【表２】
Figure 2004231453
【００７０】
【表３】
Figure 2004231453
【００７１】
表１〜３の結果から明らかなように、本発明に基づき、セルジアン結晶相を含む特定の結晶相が析出した試料Ｎｏ．１〜４、６〜１６、２１〜２３、２５〜３０では、熱膨張係数が５×１０−６／℃以下、誘電率が７以下、ヤング率が１５０ＧＰａ以下となり、さらに抗折強度も１５０ＭＰａ以上と良好な値を示した。
【００７２】
それに対して、ガラス粉末の量が９９質量％よりも多い試料Ｎｏ．５では、ガラスの軟化流動が著しく焼結体の原型を保つことができず、評価可能な試料を得ることができなかった。また、ガラス粉末の量が６０質量％よりも少ない試料Ｎｏ．２４は、１０５０℃以下の焼成にて緻密な焼結体を得ることができなかった。
【００７３】
また、フィラー粉末として、本発明の範囲外であるＺｒＯ２、ＴｉＯ２を用いた試料Ｎｏ．１７〜２０は、いずれも熱膨張係数が５×１０−６／℃よりも高くなった。
【００７４】
さらに、本発明の範囲外のガラス粉末Ｅ、Ｆを用いた試料Ｎｏ．３１〜３４では、いずれの試料もセルジアン結晶相を含有せず、熱膨張係数が５×１０−６／℃よりも高くなった。
【００７５】
（実施例２）
実施例１の試料Ｎｏ．１〜４、６〜１６、２１〜２３、２５〜３０の原料粉末に対して、アクリル系バインダと可塑剤とトルエンを添加、混合し、ドクターブレード法によって厚み２５０μｍのグリーンシートを作製した。次に、該グリーンシートの所定位置にビアホールを形成し、銅を主成分とする導体ペーストを充填した後、スクリーン印刷法により前記導体ペーストを用いてグリーンシート表面に配線層を形成した。
【００７６】
そして、前記配線層を形成したグリーンシートを位置合わせしながら４枚積層、熱圧着した。この積層体を水蒸気含有窒素中、７５０℃で脱バインダ処理した後、２００℃／時間で昇温した後、窒素中、９５０℃で１時間焼成して銅を主成分とする配線層を具備する多層配線基板を作製した。
【００７７】
得られた配線基板について、配線層の導通を確認したところ、断線等がなく、低抵抗で良好な導通特性を示した。
【００７８】
（実施例３）
さらに、上記グリーンシートの表面に、銅を主体とした導体ペーストをスクリーン印刷法にて、パッケージＡの表面には、０．１２ｍｍφのパッドをマトリックス状に配設したフリップチップパッドを形成し、裏面には１ｍｍφのパッドをマトリックス状に配設したボールパッドを形成した。焼成後の形状が３０ｍｍ□、厚み１．５ｍｍとなるようにグリーンシートを積層、切断後、表２に示す条件にて焼成した。得られた配線基板にＮｉ−Ａｕめっきを施した後、Ｓｉを主体とする熱膨張係数が３×１０−６／℃の半導体素子５をパッケージＡの表面に、半田層をめっきにて形成し、リフロー処理を行った後、エポキシ樹脂からなるアンダーフィル材を半導体素子とパッケージＡとの間隙に注入し、硬化させることにより半導体素子をフリップチップ実装した。
次に、ボールパッド上に共晶半田ペーストを印刷し、１．２ｍｍφの高温半田ボールを位置合わせして載置し、リフロー処理を行うことにより、高温半田ボールを搭載したパッケージＡを作製した。
【００７９】
さらに、パッケージＡと同様の配線パターンを形成した熱膨張係数が１５×１０−６／℃のプリント配線基板Ｂを用意し、その上にパッケージＡを位置合わせして載置し、再度リフロー処理を行うことによりパッケージＡをプリント配線基板Ｂ上に実装した二次実装サンプルをそれぞれ２０個作製した。
【００８０】
上記二次実装サンプルを、０〜１００℃の温度範囲で温度サイクル試験を行い、１００サイクル終了毎に一次実装側、二次実装側の双方に関して抵抗値を測定し、断線の有無を確認し、断線したサイクル数を表２、３に示した。ここで、１０００サイクルまで断線のなきものを合格（ＯＫ）とした。
【００８１】
さらに、比較例として熱膨張係数が４．７×１０−６／℃、ヤング率が３１０ＧＰａのＡｌＮセラミックスを絶縁基板とし、タングステンによって配線層、ビア導体を形成し、１６００℃で同時焼成してパッケージを作製し、同様の温度サイクル試験を行った。
【００８２】
表１〜３の結果から明らかなように、本発明に基づき、特定の結晶相が析出した熱膨張係数が５×１０−６／℃以下、ヤング率が１５０ＧＰａ以下の試料Ｎｏ．１〜４、６〜１６、２１〜２３、２５〜３０では、一次実装、および二次実装の双方において１０００サイクルの温度サイクル試験において断線が見られず、高い実装信頼性を示すことが確認できる。
【００８３】
一方、本発明の範囲外であり、熱膨張係数が５×１０−６／℃よりも大きい試料Ｎｏ．１７〜２０、３１〜３４においては、温度サイクル試験において、半導体素子と絶縁基板間の熱膨張係数のミスマッチが大きく、いずれの試料も１０００サイクルよりも短いサイクル数にて断線が生じ、一次実装信頼性が確保できなかった。
【００８４】
また、熱膨張係数が４．７×１０−６／℃と低いものの、ヤング率が３１０ＧＰａと高い値を示すＡｌＮを用いた試料Ｎｏ．３５においては、温度サイクル試験の結果、一次実装側は１０００サイクルにて断線が見られないものの、ヤング率が高く熱応力の緩和効果が不充分なため、二次実装側で１０００サイクルよりも短いサイクル数にて断線が生じ、実装信頼性が確保できなかった。
【００８５】
【発明の効果】
以上詳述した通り、本発明のガラスセラミック組成物および焼結体は、１０５０℃以下の焼成にて、銅、銀、金などの低抵抗金属を主成分とする導体材料を用いて配線層を形成することができ、低熱膨張係数と低誘電率、低ヤング率とを兼ね備えることにより、Ｓｉなどの半導体素子の一次実装、高熱膨張のプリント配線基板への二次実装の双方に対して高い実装信頼性を示す配線基板を提供することができる。
【図面の簡単な説明】
【図１】本発明の配線基板を用いたＢＧＡ型の半導体素子収納用パッケージをプリント配線基板上に実装した一例を説明するための概略断面図である。
【符号の説明】
Ａ 素子収納用パッケージ
Ｂ プリント配線基板
１ 絶縁基板
２ 配線層
３ ビアホール導体
４ 接続用電極
５ 電気素子
６ 半田
７ アンダーフィル材
８ 高温半田ボール
９ 共晶半田[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a glass-ceramic composition and a glass-ceramic sintered body that are optimal for a wiring board or the like applied to a package for housing a semiconductor element, a multilayer wiring board, and the like, and a wiring board using the same as an insulating substrate And its mounting structure.
[0002]
[Prior art]
In recent years, with the advance of the information age, information and communication technology has been rapidly developed, and as a result, the speed and size of semiconductor elements and the like have been increased, and the wiring layer has also been required to reduce signal transmission loss. , There is a demand for lower resistance and lower dielectric constant of the insulating substrate. Therefore, it can be densified by firing at 1000 ° C. or less, can be simultaneously fired with a wiring layer mainly composed of a low-resistance metal such as copper, silver or gold, and has a glass dielectric material having a low dielectric constant as an insulating layer. Wiring boards have been proposed.
[0003]
In particular, with respect to semiconductor elements mainly composed of Si, the mechanical strength tends to decrease in recent years as the element speeds up. Therefore, when a semiconductor element is mounted on a package for housing a semiconductor element (hereinafter, referred to as primary mounting), the semiconductor element may be broken due to thermal stress generated due to a mismatch in coefficient of thermal expansion between the element and the package. The problem is a concern. Furthermore, as the size of the device increases, the thermal stress increases with the increase in the size of the device.
[0004]
Therefore, in order to reduce the thermal stress related to the primary mounting, it is required to match the thermal expansion coefficient of the package with the thermal expansion coefficient of Si (2 to 4 × 10 −6 / ° C .: 40 to 400 ° C.).
[0005]
For example, Japanese Patent Publication No. 4-58198 describes that a multilayer ceramic circuit board having a low coefficient of thermal expansion can be obtained by using a glass ceramic sintered body made of mullite, quartz glass, and borosilicate glass as an insulating material. .
[0006]
For example, in JP-A-5-254923, low-resistance wiring is possible by combining borosilicate glass composed of SiO 2 , B 2 O 3 , K 2 O, and Al 2 O 3 with alumina, cordierite, and quartz glass. It is described that a ceramic substrate having a low coefficient of thermal expansion can be obtained.
[0007]
[Patent Document 1]
Japanese Patent Publication No. 4-58198 [Patent Document 2]
JP-A-5-254923
[Problems to be solved by the invention]
However, the conventional glass ceramic sintered body as described above can improve the reliability of the primary mounting by realizing a low coefficient of thermal expansion, but conversely, the coefficient of thermal expansion is 15 to 20 × 10 −6. When mounted on a motherboard composed of a very large printed wiring board of about / ° C (hereinafter referred to as “secondary mounting”), the mismatch in the coefficient of thermal expansion becomes very large, so that the secondary mounting reliability is high. There was a problem that it was difficult to secure the
[0009]
Accordingly, the present invention provides a glass-ceramic composition which can be simultaneously fired with a low-resistance metal such as silver, copper, or gold, and has a low coefficient of thermal expansion and a low dielectric constant while forming a sintered body having a low Young's modulus. It is an object of the present invention to provide an object, a glass-ceramic sintered body, and a wiring board and a mounting structure using the sintered body, which can ensure high secondary mounting reliability as well as primary mounting reliability.
[0010]
[Means for Solving the Problems]
The present inventors have studied the above problem, and as a result, have at least a cordier as a filler for a glass powder containing at least SiO 2 , Al 2 O 3 , MgO, BaO, B 2 O 3 , and ZnO at a predetermined ratio. Ellite, mullite, anorthite, slausonite, Serdian, at least one selected from the group of quartz glass is added at a predetermined ratio, mixed, molded, and fired at 1050 ° C. or lower to precipitate a predetermined crystal phase or By dispersing, a low thermal expansion coefficient, a low dielectric constant, and a low Young's modulus can be achieved at the same time.Also, a wiring board using a sintered body having a low thermal expansion coefficient, a low dielectric constant and a low Young's modulus as an insulating substrate is required. The present inventors have found that the secondary mounting reliability can be enhanced together with the primary mounting reliability, and the present invention has been made.
[0011]
That is, the glass ceramic composition of the present invention contains at least 30 to 70% by mass of SiO 2 , 5 to 30% by mass of Al 2 O 3 , 3 to 25% by mass of MgO, 3 to 25% by mass of BaO, and B 2 O 3 1 60 to 99% by mass of a glass powder containing 1 to 15% by mass of ZnO and 1 to 15% by mass of ZnO, and at least one kind of filler powder 1 selected from the group consisting of cordierite, mullite, anorthite, slausonite, Celsian, and quartz glass -40% by mass.
[0012]
It is desirable that the glass powder be subjected to a heat treatment at 1050 ° C. or less to precipitate at least Celsian as a crystal phase. Thereby, low thermal expansion, low dielectric constant, and low Young's modulus can be achieved. In addition, it is desirable that the Celsian contains at least a monoclinic crystal. In addition, in such a composition, it is desirable that the contents of PbO and A 2 O (A: alkali metal) are each suppressed to 0.1% by mass or less in order to improve environmental resistance and chemical resistance.
[0013]
Further, the glass-ceramic sintered body of the present invention contains at least Celsian as a crystal phase, has a thermal expansion coefficient of 5 × 10 −6 / ° C. or less at 40 to 400 ° C., a dielectric constant of 7 or less, and a Young's modulus of 150 GPa or less. It is characterized by being.
[0014]
Here, such a sintered body desirably further contains, as a crystal phase, at least one selected from the group consisting of cordierite, garnet, spinel, mullite, anorthite, slausonite, and Celsian. Is preferably 150 MPa or more, and more preferably, the contents of PbO and A 2 O (A: alkali metal) are each 0.1 mass% or less.
[0015]
Moreover, such glass-ceramic sintered body, at least, SiO 2 30 to 70 wt%, Al 2 O 3 5~30 wt%, MgO 3 to 25 mass%, BaO 3 to 25 wt%, B 2 O 3 1~ 60 to 99% by mass of a glass powder containing 15% by mass and 1 to 15% by mass of ZnO, and at least one type of filler powder 1 selected from the group consisting of cordierite, mullite, anorthite, slausonite, cellian, and quartz glass 1 -40% by mass, mixed, molded, and fired in air or nitrogen atmosphere at a temperature of 1050 ° C or less.
[0016]
Further, the wiring board of the present invention is provided with a wiring layer containing a low-resistance metal on the surface and / or inside of the insulating substrate, wherein the insulating substrate is made of the above glass ceramic sintered body. It is preferable that a semiconductor element mainly composed of Si is mounted on the surface of the wiring substrate and / or a concave portion provided on the surface.
[0017]
Further, by mounting the above-mentioned wiring board on the surface of a printed wiring board provided with an insulating substrate containing an organic resin, a mounting structure having excellent primary mounting reliability and secondary mounting reliability can be provided.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
The glass-ceramic composition of the present invention contains at least 30 to 70% by mass of SiO 2 , especially 45 to 60% by mass, 5 to 30% by mass of Al 2 O 3 , particularly 10 to 25% by mass, and MgO 3 to 25 wt%, particularly 5 to 20 wt%, BaO 3 to 25% by weight, particularly 5 to 20 wt%, B 2 O 3 1 to 15% by weight, in particular 3 to 12 wt%, ZnO 1 to 15% by weight, in particular A glass powder containing 2 to 10% by weight, 60 to 99% by weight, especially 65 to 97% by weight, optimally 70 to 95% by weight, and a group of cordierite, mullite, anorthite, slausonite, celsian, quartz glass; At least one kind of filler powder selected from the group consisting of 1 to 40% by mass, particularly 3 to 35% by mass, and most preferably 5 to 30% by mass.
[0019]
Here, the glass powder is necessary for sintering the composition at a low temperature of 1050 ° C. or less, which is a temperature at which co-firing can be performed with a low-resistance conductor such as copper, silver, or gold. This allows the composition to be sintered at a low temperature. When the amount of the glass powder is smaller than the above range, it becomes difficult to sinter the composition at 1050 ° C. or lower, and conversely, when the amount is larger than the above range, the composition is fired. , It is difficult to keep its original form.
[0020]
Further, SiO 2 is a glass network former and is an essential component for precipitating a crystal phase containing SiO 2 as a constituent, such as Celdian and cordierite, in particular, Celsian from glass. When the content of SiO 2 is less than the above range, the precipitation amount of the crystal phase becomes insufficient, and it becomes difficult to set the characteristics of the glass ceramic sintered body within a desired range. In addition, the softening temperature of the glass rises, making it difficult to fire at a low temperature of 1050 ° C. or less.
[0021]
Al 2 O 3 is a component that improves the Young's modulus and chemical resistance of glass, and at the same time, is a crystal phase containing Al 2 O 3 as a component, such as Celsian, cordierite, garnite, and spinel, particularly, It is an essential component for precipitating Celsian from glass. When Al 2 O 3 is less than the above range, the amount of the crystal phase precipitated becomes insufficient, and it becomes difficult to set the properties of the glass ceramic sintered body within a desired range. If the amount is too high, the softening temperature of the glass increases, making it difficult to fire at a low temperature of 1050 ° C. or lower, and at the same time, the Young's modulus of the glass ceramic sintered body increases, making it difficult to secure high secondary mounting reliability. Become.
[0022]
In addition, B 2 O 3 is a glass network former and also has a function of lowering the softening temperature and melting temperature. If B 2 O 3 is less than the above range, the melting temperature of glass rises too much. As a result, it becomes difficult to manufacture the glass at low cost industrially, and at the same time, the softening temperature of the glass rises, making it difficult to fire at a low temperature of 1050 ° C. or lower. On the other hand, when the amount is larger than the above range, the softening temperature of the glass decreases and it becomes difficult to maintain the original shape of the glass ceramic sintered body, and at the same time, the chemical resistance of the glass ceramic sintered body is significantly reduced.
[0023]
MgO is an essential component of a crystal phase containing MgO as a constituent, such as cordierite and spinel. If the content of MgO is larger than the above range, the Young's modulus of the glass ceramic sintered body increases, and it is difficult to secure high secondary mounting reliability. On the other hand, if the content of MgO is less than the above range, the precipitation of the crystal phase becomes insufficient and the desired properties cannot be obtained.
[0024]
BaO is an essential component for precipitating Celsian, and has a function of lowering the softening temperature of glass. When BaO is less than the above range, the precipitation amount of the crystal phase becomes insufficient, and it becomes difficult to set the properties of the glass ceramic sintered body within a desired range. In addition, the softening temperature of the glass decreases, making it difficult to maintain the original shape of the glass ceramic sintered body, and at the same time, the chemical resistance of the glass ceramic sintered body is significantly reduced.
Further, ZnO is an essential component for lowering the softening temperature of the glass and at the same time precipitating a crystal phase containing ZnO as a constituent component such as garnet from the glass. When ZnO is less than the above range, the precipitation amount of the crystal phase becomes insufficient, and it becomes difficult to set the characteristics of the glass ceramic sintered body within a desired range. In addition, the softening temperature of the glass decreases, making it difficult to maintain the original shape of the glass ceramic sintered body, and at the same time, the chemical resistance of the glass ceramic sintered body is significantly reduced.
[0025]
In the glass powder, CaO, SrO, ZrO 2 , SnO 2 , and other components of the rare earth oxide are contained in an amount of 10% by mass or less, particularly 7% by mass, as long as the amount of the component does not deviate from the range of the present invention. Hereinafter, it may further be contained in a range of 5% by mass or less, whereby it becomes possible to finely adjust the sinterability and characteristics of the glass ceramic sintered body.
[0026]
However, it is desirable that PbO and A 2 O (A: alkali metal) have a large load on the environment and are each suppressed to 0.1% by mass or less in the total amount from the viewpoint of chemical resistance and insulation. .
[0027]
Further, in the present invention, the heat treatment at 1050 ° C. or lower causes the glass powder to precipitate at least Celsian as a crystal phase, thereby lowering the thermal expansion coefficient, dielectric constant, and Young's modulus of the glass ceramic sintered body. It is desirable because it will be possible. Furthermore, since the Celsian crystal phase is precipitated from glass instead of as a powder, there is also an effect of improving the sinterability, so that while reducing the Young's modulus of the glass ceramic sintered body, the bending strength is improved. It is possible to make it.
(Filler)
On the other hand, at least one powder selected from the group consisting of cordierite, mullite, anorthite, slausonite, cellian, and quartz glass, which serves as a filler, has a thermal expansion coefficient of a glass ceramic sintered body obtained by firing the composition. , A particularly effective component for lowering the dielectric constant, at least one selected from the group consisting of mullite, anorthite, and slausonite is also effective in improving the transverse rupture strength, cordierite, quartz Glass has a particularly remarkable effect of lowering the coefficient of thermal expansion, dielectric constant, and Young's modulus.
[0028]
When the amount of these powders is less than the above range, it is difficult to make the properties of the glass ceramic sintered body within a desired range, and when the amount is more than the above range, the composition is heated to 1050 ° C. The following makes it difficult to sinter.
[0029]
In the glass ceramic composition, SiO 2 , Ca 2 MgSi 2 O 7 , Sr 2 MgSi 2 O 7 , Ba 2 MgSi 2 O 7 , ZrO are used as long as the amount of the filler does not deviate from the amount of the present invention. 2 , other fillers selected from the group consisting of ZnO, MgSiO 3 , Mg 2 SiO 4 , ZrSiO 4 , Zn 2 SiO 4 , CaMgSi 2 O 6 , Zn 2 Al 4 Si 5 O 18 , CaSiO 3 , SrSiO 3 , and BaSiO 3 The powder may be contained in a total amount of 15% by mass or less, particularly 10% by mass or less, or even 5% by mass or less, whereby the sinterability and properties of the glass ceramic sintered body are finely adjusted. It becomes possible.
[0030]
The glass ceramic sintered body of the present invention contains at least Celsian as a crystal phase and has a thermal expansion coefficient at 40 to 400 ° C. of 5 × 10 −6 / ° C. or less, particularly 4.8 × 10 −6 / ° C. or less. It is required that 4.5 × 10 −6 / ° C. or less, dielectric constant is 7 or less, especially 6.5 or less, optimally 6 or less, Young's modulus is 150 GPa or less, especially 140 GPa or less, and optimally 130 GPa or less. It is a feature. Furthermore, it is desirable that the three-point bending strength based on JISR1601 is 150 MPa or more.
[0031]
Here, the Celsian crystal phase is an essential component for achieving low thermal expansion, low dielectric constant, and low Young's modulus of the glass ceramic sintered body. The Serdian crystal may be contained in the starting composition as a raw material powder, but optimally, the Serdian is not added to the starting composition, but is precipitated out of the glass powder, thereby obtaining a low Young's modulus and a higher resistance. It is desirable because the bending strength can be realized at the same time.
[0032]
The coefficient of thermal expansion of the glass ceramic sintered body is such that when the semiconductor element mainly composed of Si is primarily mounted on a wiring board using the glass ceramic sintered body as an insulating substrate, the insulating substrate and the semiconductor element are separated from each other. Must be close to the value of the coefficient of thermal expansion of Si in order to reduce the thermal stress caused by the mismatch of the coefficient of thermal expansion of Si. If the value is larger than the above range, the reliability of the primary mounting Is difficult to secure.
[0033]
Further, it is desirable that the dielectric constant is low in order to reduce the signal delay time. If the dielectric constant is larger than the above range, the delay time of the wiring board becomes longer and the performance is reduced.
[0034]
Also, a low Young's modulus means that the glass ceramic sintered body is easily deformed by stress. Therefore, by lowering the thermal expansion coefficient to match the thermal expansion coefficient of the sintered body with the semiconductor element, even if the thermal expansion difference in the secondary mounting on the printed wiring board becomes large, the heat generated in the secondary mounting portion Stress can be reduced by deformation of the sintered body, and secondary mounting reliability can be improved. Therefore, when the Young's modulus is larger than the above range, the secondary mounting reliability is significantly reduced.
[0035]
Furthermore, in the present invention, in addition to the above-mentioned Serdian, at least one selected from the group consisting of cordierite, garnitite, spinel, mullite, anorthite, and slausonite is contained as a crystal phase, so that the glass ceramic is sintered. The bending strength of the body can be improved. In particular, at least one selected from the group consisting of mullite, anorthite, slausonite, and Celsian is desirable not only for improving the transverse rupture strength but also for decreasing the thermal expansion coefficient and the dielectric constant.
[0036]
Furthermore, in the present invention, the fact that the contents of PbO and A 2 O (A: alkali metal) are each suppressed to 0.1% by mass or less is from the viewpoint of environmental load, chemical resistance, and insulation. desirable.
[0037]
Further, in the sintered body, SiO 2 , Ca 2 MgSi 2 O 7 , Sr 2 MgSi 2 O 7 , Ba 2 MgSi 2 O 7 , ZrO 2 , ZnO, MgSiO 3 , and the like do not depart from the scope of the present invention. Another crystal phase selected from the group consisting of Mg 2 SiO 4 , ZrSiO 4 , Zn 2 SiO 4 , CaMgSi 2 O 6 , Zn 2 Al 4 Si 5 O 18 , CaSiO 3 , SrSiO 3 , and BaSiO 3 , having a total amount of 15 mass %, Especially 10% by mass or less, and even 5% by mass or less, whereby the sinterability and properties of the glass ceramic sintered body can be controlled.
[0038]
In order to produce the above-mentioned glass ceramic sintered body, first, at least 30 to 70% by mass of SiO 2 , particularly 45 to 60% by mass, and 5 to 30% by mass of Al 2 O 3 , particularly 10 to 25% by mass as constituent components. wt%, MgO 3 to 25% by weight, particularly 5 to 20 wt%, BaO 3 to 25% by weight, particularly 5 to 20 wt%, B 2 O 3 1 to 15% by weight, in particular 3 to 12 wt%, ZnO 1 From 60 to 99% by weight, especially from 65 to 97% by weight, optimally from 70 to 95% by weight, of cordierite, mullite, anorthite, slausonite, At least one kind of filler powder selected from the group consisting of Celsian and quartz glass is mixed at a ratio of 1 to 40% by mass, particularly 3 to 35% by mass, and optimally 5 to 30% by mass.
[0039]
Here, when the composition of the glass powder, the filler powder, and the composition of the glass powder are out of the above ranges, the characteristics of the glass ceramic sintered body are not in the desired range as described above.
[0040]
Then, an organic binder, a solvent, and a plasticizer, if necessary, are added to and mixed with the mixture, and the mixture is subjected to predetermined molding by at least one molding method selected from the group consisting of press molding, extrusion molding, injection molding, casting molding, and tape molding. Form into shape.
[0041]
After the binder is removed at 450 to 750 ° C. in a oxidizing atmosphere or a nitrogen atmosphere, the molded body is fired at a temperature of 1050 ° C. or less, particularly 700 to 1000 ° C., and further 800 to 950 ° C. The glass ceramic sintered body of the invention can be manufactured.
[0042]
When using a glass ceramic sintered body as an insulating substrate of a wiring board described later, when silver or gold is used as the conductor material, since the conductor is not oxidized, it is desirable to sinter in an air atmosphere, and when using copper. In order to suppress the oxidation of copper, it is desirable to perform firing in a nitrogen atmosphere.
[0043]
The glass ceramic sintered body can be fired even in a reducing atmosphere, but is preferably fired in an oxidizing atmosphere or a nitrogen atmosphere in terms of cost and safety.
[0044]
Further, in order to promote the precipitation of the above-mentioned specific crystal phase in the sintered body, it is desirable that the rate of temperature rise after the binder removal treatment is 50 ° C./hour or more, particularly 100 ° C./hour or more. The holding time at the firing temperature is preferably 0.02 to 10 hours, particularly preferably 0.2 to 2 hours.
[0045]
Further, the wiring board of the present invention is provided with a wiring layer containing a low-resistance metal disposed on the surface and / or inside of the insulating substrate, wherein the insulating substrate is made of the above-mentioned glass ceramic sintered body. It is.
[0046]
By using the above-mentioned glass ceramic sintered body as an insulating substrate, simultaneous firing with a wiring layer containing at least one low-resistance metal selected from the group consisting of copper, silver and gold becomes possible.
[0047]
In the present invention, it is preferable that a semiconductor element mainly composed of Si is mounted on the surface of the wiring substrate and / or a concave portion provided on the surface of the wiring substrate. It is desirable in securing.
[0048]
With respect to the wiring substrate of the present invention using the above-described glass ceramic sintered body as an insulating substrate, a BGA (ball grid array) type in which elements such as semiconductor elements mainly composed of Si, which are preferable examples, are mounted by flip-chip mounting. A description will be given based on FIG. 1 which is a schematic sectional view of a package for storing an electric element and a case where the package is mounted on a printed wiring board.
[0049]
According to FIG. 1, the electric element housing package A has a wiring layer 2 formed on the surface and / or inside of an insulating substrate 1 composed of a plurality of insulating layers 1a to 1d. According to FIG. 1, the wiring layer 2 containing at least one low-resistance metal selected from the group consisting of copper, silver and gold formed between the insulating layers 1a to 1d, and the wiring layers 2 are electrically connected to each other. A via-hole conductor 3 containing at least one low-resistance metal selected from the group consisting of copper, silver and gold is formed.
[0050]
Further, a plurality of connection electrodes 4A are arranged on the lower surface of the package A, and an electric element 5 such as a semiconductor element is flip-chip mounted on the insulating substrate 1 via solder 6 at the center of the upper surface of the insulating substrate 1. At the same time as being bonded and fixed by mounting, it is electrically connected to the package A.
[0051]
Further, between the electric element 5 and the package A, an underfill 7 containing a thermosetting resin is injected and hardened in order to enhance primary mounting reliability. Further, the electric element 5 and the plurality of connection electrodes 4A formed on the lower surface of the insulating substrate 1 are electrically connected via the solder 6, the wiring layer 2, and the via hole conductor 3.
[0052]
On the other hand, the printed wiring board B is formed on the upper surface of an insulating substrate having a coefficient of thermal expansion of 15 to 20 × 10 −6 / ° C. at 40 to 400 ° C. so that the connection electrode 4B forms a pair with the connection electrode 4A. ing. The connection electrodes 4A and 4B are electrically connected via a eutectic solder 9 and a high-temperature solder ball 8.
[0053]
According to the present invention, the insulating substrate 1 contains at least Celsian as a crystal phase as described above, has a coefficient of thermal expansion at 40 to 400 ° C. of 5 × 10 −6 / ° C. or less, a dielectric constant of 7 or less, and a Young's modulus. It is a great feature that it is formed of a glass-ceramic sintered body having a modulus of 150 GPa or less, whereby the thermal expansion coefficient and the Young's modulus of the insulating substrate 1 can be reduced. Secondary mounting reliability can be improved.
[0054]
Further, since the dielectric constant of the insulating substrate 1 is reduced, and the wiring layer 2 and the via-hole conductor 3 contain at least one low-resistance metal of copper, silver or gold as a main component, the wiring layer 2 has a low resistance. Resistance can be reduced, and signal delay can be reduced.
[0055]
In the example of FIG. 1 described above, a Si-based semiconductor element is illustrated, but the wiring board of the present invention is suitable for a wiring board on which another electric element having a thermal expansion coefficient of 5 × 10 −6 / ° C. or less is mounted. Used. Also, in the package of FIG. 1, the element 5 is suitable for being connected to the wiring layer 2 via the solder 6, but the element 5 and the wiring layer 2 may be connected by wire bonding or the like. Good. Further, the element 5 may be in a form in which the element 5 is further covered with a sealing resin. Alternatively, a cavity may be formed in the insulating substrate 1 to house the element 5 and the cavity may be hermetically sealed with a lid.
[0056]
In FIG. 1, the BGA type package structure in which the package A and the printed wiring board B are connected to each other via the high-temperature solder balls 8 has been described, but the present invention does not use lead pins and the like. In the case where the package A and the printed wiring board B are connected via solder, such as the BGA, LGA, and LCC types, the stress generated is large, and secondary mounting reliability is required. It is particularly preferably used. In addition, of course, the present invention has utility even in the form of a ball containing a resin, a columnar solder column, a column containing a resin, or even a form connected by pins.
[0057]
Next, regarding the method for manufacturing the wiring board of the present invention, taking the above package A as an example, an appropriate organic binder, a solvent, A plasticizer is added and mixed to prepare a slurry, which is formed into a sheet by a conventionally known doctor blade method, calender roll method, rolling method, press forming method, or the like. Then, after a through-hole is formed in the sheet-like molded body as required, a conductive paste containing at least one low-resistance metal selected from the group consisting of copper, silver, and gold is filled in the through-hole. Then, a wiring pattern is printed and applied on the surface of the sheet-shaped molded body by using a known printing method such as a screen printing method or a gravure printing method using the conductor paste so that the thickness of the wiring layer is 5 to 30 μm. .
[0058]
Then, after the plurality of sheet-shaped molded bodies are aligned and laminated and pressed, the binder is removed in the air or in a nitrogen atmosphere, and then fired in the air or a nitrogen atmosphere at 1050 ° C. or lower, thereby forming a wiring board. Can be produced.
[0059]
In addition, as for the firing atmosphere, when silver or gold is used as the conductor material, the conductor is not oxidized. Therefore, it is preferable that the firing be performed in an air atmosphere, and when copper is used, in order to suppress oxidation of copper, It is desirable to fire in a nitrogen atmosphere.
[0060]
An electric element 5 such as a semiconductor element is mounted on the surface of the wiring board, and is connected to the wiring layer 2 so that signals can be transmitted. As described above, the connection method is preferably a flip-chip mounting using solder, wire bonding, or a mode of directly mounting on the wiring layer 2 for connection.
[0061]
Further, the gap between the electric element 5 and the package A is filled with the underfill material 7 and cured, or the element is covered with a potting resin and cured, or the same kind of insulating material as the insulating substrate 1 or another insulating material is used. Alternatively, the element storage package A can be manufactured by joining a lid made of a metal or the like having good heat dissipation with an adhesive such as glass, resin, or brazing material.
[0062]
A high melting point solder ball 8 is connected to the lower surface of the package A by low melting point solder. When the package A is mounted on the printed wiring board B, the solder balls 8 of the package A are placed on the connection electrodes 4B of the printed wiring board B via the low melting point solder on the surface of the printed wiring board B. The package A can be secondarily mounted on the printed wiring board B by mounting and performing a solder reflow process.
[0063]
【Example】
(Example 1)
Four kinds of powders of glasses A, B, C, and D having an average particle size of 2 μm of the present invention having the compositions shown in Table 1 were prepared, and the average particle size of these glass powders was 1 to 2 μm. Using the filler powders shown in Table 2, mixing was performed according to the compositions shown in Tables 2 and 3.
[0064]
Then, an organic binder, a plasticizer, and toluene were added to this mixture to prepare a slurry, and then a green sheet having a thickness of 300 μm was produced using the slurry by a doctor blade method. Further, a plurality of the green sheets were laminated so as to have a desired thickness, and thermocompression bonding was performed at a temperature of 60 ° C. by applying a pressure of 10 MPa.
[0065]
After the obtained laminate is subjected to a binder removal treatment at 750 ° C. in a nitrogen atmosphere, the temperature is increased at a rate of 200 ° C./hour and fired in the air under the conditions shown in Tables 2 and 3 to obtain a glass ceramic sintered body. Was.
[0066]
The obtained sintered body was processed into a 2 mm square and a length of 18 mm, and the dimensional change was measured by a laser range finder while heating at a rate of 10 ° C./min. The coefficient of thermal expansion at ℃ was measured. Moreover, it processed into 50 mm square and thickness 1.0 mm, and measured the dielectric constant at 2 GHz by the cavity resonator method. Further, the sintered body was processed into a size of 3 mm × 4 mm × 40 mm, and the Young's modulus was measured by an ultrasonic pulse method. Using the same sample, the three-point bending strength based on JISR-1601 was measured using an autograph. Further, the crystal phases in the sintered body were identified from X-ray diffraction measurement, and were arranged in descending order of main peak intensity. Tables 2 and 3 show the above measurement results.
[0067]
On the other hand, the same evaluation was performed using two types of glasses E and F shown in Table 1 instead of the above four types of glasses. Similar evaluations were made using TiO 2 and ZrO 2 as filler powders. The results are shown in Tables 2 and 3.
[0068]
[Table 1]
Figure 2004231453
[0069]
[Table 2]
Figure 2004231453
[0070]
[Table 3]
Figure 2004231453
[0071]
As is clear from the results of Tables 1 to 3, based on the present invention, Sample No. on which a specific crystal phase including a Serdian crystal phase was precipitated. In 1-4, 6-16, 21-23, and 25-30, the thermal expansion coefficient is 5 × 10 −6 / ° C. or less, the dielectric constant is 7 or less, the Young's modulus is 150 GPa or less, and the bending strength is 150 MPa or more. And a good value.
[0072]
On the other hand, the sample No. in which the amount of the glass powder was more than 99% by mass. In No. 5, the softening flow of the glass was remarkable, and the prototype of the sintered body could not be maintained, and an evaluable sample could not be obtained. Also, in Sample No. in which the amount of glass powder was less than 60% by mass. In No. 24, a dense sintered body could not be obtained by firing at 1050 ° C. or lower.
[0073]
Sample No. using ZrO 2 or TiO 2 outside the scope of the present invention as the filler powder. In all of Nos. 17 to 20, the thermal expansion coefficients were higher than 5 × 10 −6 / ° C.
[0074]
Further, Sample Nos. Using glass powders E and F outside the scope of the present invention. In samples 31 to 34, none of the samples contained the Serdian crystal phase, and the coefficient of thermal expansion was higher than 5 × 10 −6 / ° C.
[0075]
(Example 2)
Sample No. of Example 1 An acrylic binder, a plasticizer and toluene were added to and mixed with the raw material powders Nos. 1 to 4, 6 to 16, 21 to 23, and 25 to 30, and a green sheet having a thickness of 250 μm was produced by a doctor blade method. Next, a via hole was formed at a predetermined position of the green sheet, and a conductive paste containing copper as a main component was filled, and a wiring layer was formed on the surface of the green sheet by using the conductive paste by a screen printing method.
[0076]
Then, while aligning the green sheets on which the wiring layers were formed, four sheets were laminated and thermocompression bonded. This laminate is subjected to a binder removal treatment in steam-containing nitrogen at 750 ° C., heated at a rate of 200 ° C./hour, and then baked in nitrogen at 950 ° C. for 1 hour to provide a wiring layer mainly containing copper. A multilayer wiring board was manufactured.
[0077]
With respect to the obtained wiring board, the conduction of the wiring layer was confirmed. As a result, there was no disconnection or the like, and low resistance and good conduction characteristics were exhibited.
[0078]
(Example 3)
Furthermore, on the surface of the green sheet, a flip-chip pad in which 0.12 mmφ pads are arranged in a matrix is formed on the surface of the package A by a screen printing method using a conductive paste mainly composed of copper. Formed a ball pad having 1 mmφ pads arranged in a matrix. The green sheets were laminated and cut so that the shape after firing was 30 mm square and the thickness was 1.5 mm, and then fired under the conditions shown in Table 2. After subjecting the obtained wiring board to Ni-Au plating, a semiconductor element 5 mainly composed of Si and having a thermal expansion coefficient of 3 × 10 −6 / ° C. was formed on the surface of the package A by plating a solder layer. After the reflow treatment, an underfill material made of an epoxy resin was injected into the gap between the semiconductor element and the package A, and the semiconductor element was cured by flip-chip mounting.
Next, a eutectic solder paste was printed on the ball pad, a 1.2 mmφ high-temperature solder ball was positioned and placed, and reflow processing was performed to manufacture a package A on which the high-temperature solder ball was mounted.
[0079]
Further, a printed wiring board B having a thermal expansion coefficient of 15 × 10 −6 / ° C. on which a wiring pattern similar to that of the package A is formed is prepared, and the package A is positioned and mounted thereon, and reflow processing is performed again. By doing so, 20 secondary mounting samples each having the package A mounted on the printed wiring board B were produced.
[0080]
The above secondary mounting sample is subjected to a temperature cycle test in a temperature range of 0 to 100 ° C., and each time 100 cycles are completed, the resistance value is measured for both the primary mounting side and the secondary mounting side, and the presence or absence of disconnection is confirmed. Tables 2 and 3 show the number of disconnected cycles. Here, those without disconnection up to 1000 cycles were regarded as acceptable (OK).
[0081]
Further, as a comparative example, an AlN ceramic having a coefficient of thermal expansion of 4.7 × 10 −6 / ° C. and a Young's modulus of 310 GPa is used as an insulating substrate, a wiring layer and a via conductor are formed of tungsten, and the package is simultaneously fired at 1600 ° C. And a similar temperature cycle test was performed.
[0082]
As is clear from the results of Tables 1 to 3, based on the present invention, sample No. 5 having a specific crystal phase precipitated and having a coefficient of thermal expansion of 5 × 10 −6 / ° C. or less and a Young's modulus of 150 GPa or less. In Nos. 1-4, 6-16, 21-23, and 25-30, no disconnection was observed in the temperature cycle test of 1000 cycles in both the primary mounting and the secondary mounting, and it was confirmed that high mounting reliability was exhibited. .
[0083]
On the other hand, Sample No. which is out of the range of the present invention and has a coefficient of thermal expansion larger than 5 × 10 −6 / ° C. 17 to 20, 31 to 34, in the temperature cycle test, there was a large mismatch in the coefficient of thermal expansion between the semiconductor element and the insulating substrate. Could not be secured.
[0084]
Sample No. using AlN having a low coefficient of thermal expansion of 4.7 × 10 −6 / ° C. but a high Young's modulus of 310 GPa. In No. 35, as a result of the temperature cycle test, no disconnection was observed on the primary mounting side at 1000 cycles, but since the Young's modulus was high and the effect of relaxing thermal stress was insufficient, the secondary mounting side was shorter than 1000 cycles. Disconnection occurred at the number of cycles, and the mounting reliability could not be secured.
[0085]
【The invention's effect】
As described in detail above, the glass ceramic composition and the sintered body of the present invention are formed by firing at 1050 ° C. or lower using a conductive material mainly composed of a low-resistance metal such as copper, silver, and gold to form a wiring layer. It can be formed, and has both low coefficient of thermal expansion, low dielectric constant, and low Young's modulus, so that it is high in both primary mounting of semiconductor elements such as Si and secondary mounting on printed wiring boards with high thermal expansion. A wiring board exhibiting reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining an example in which a BGA type semiconductor element housing package using a wiring board of the present invention is mounted on a printed wiring board.
[Explanation of symbols]
A package for element storage B printed wiring board 1 insulating board 2 wiring layer 3 via hole conductor 4 connection electrode 5 electric element 6 solder 7 underfill material 8 high-temperature solder ball 9 eutectic solder

Claims (12)

少なくとも、ＳｉＯ２ ３０〜７０質量％、Ａｌ２Ｏ３ ５〜３０質量％、ＭｇＯ ３〜２５質量％、ＢａＯ ３〜２５質量％、Ｂ２Ｏ３ １〜１５質量％、ＺｎＯ １〜１５質量％、を含有するガラス粉末６０〜９９質量％と、コーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％とを含有することを特徴とするガラスセラミック組成物。At least, SiO 2 30 to 70 wt%, Al 2 O 3 5~30 wt%, MgO 3 to 25 mass%, BaO 3 to 25 wt%, B 2 O 3 1~15 wt%, ZnO 1 to 15 wt% And at least one filler powder selected from the group consisting of cordierite, mullite, anorthite, slausonite, serdian and quartz glass in an amount of 1 to 40% by mass. A glass-ceramic composition characterized by the following: 前記ガラス粉末が、１０５０℃以下の熱処理を行うことにより、少なくともセルジアンを結晶相として析出することを特徴とする請求項１に記載のガラスセラミック組成物。The glass-ceramic composition according to claim 1, wherein the glass powder is subjected to a heat treatment at 1050 ° C. or less to precipitate at least Celsian as a crystal phase. 上記セルジアンが少なくとも単斜晶を含むことを特徴とする請求項１または請求項２のいずれかに記載のガラスセラミック組成物。3. The glass-ceramic composition according to claim 1, wherein said Celsian comprises at least monoclinic. ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）の含有量がそれぞれ０．１質量％以下であることを特徴とする請求項１乃至請求項３のいずれかに記載のガラスセラミック組成物。PbO and A 2 O: glass ceramic composition according to any one of claims 1 to 3 content is equal to or more than 0.1 mass% each of (A alkali metal). 少なくともセルジアンを結晶相として含有し、４０〜４００℃における熱膨張係数が５×１０−６／℃以下、誘電率が７以下、ヤング率が１５０ＧＰａ以下であることを特徴とするガラスセラミック焼結体。A glass ceramic sintered body containing at least Celsian as a crystalline phase, having a coefficient of thermal expansion at 40 to 400 ° C. of 5 × 10 −6 / ° C. or less, a dielectric constant of 7 or less, and a Young's modulus of 150 GPa or less. . 結晶相として、さらに、コーディエライト、ガーナイト、スピネル、ムライト、アノーサイト、スラウソナイト、セルジアンの群から選ばれる少なくとも１種を含有することを特徴とする請求項５に記載のガラスセラミック焼結体。The glass-ceramic sintered body according to claim 5, further comprising at least one selected from the group consisting of cordierite, garnitite, spinel, mullite, anorthite, slausonite, and Celsian as a crystal phase. 抗折強度が１５０ＭＰａ以上であることを特徴とする請求項５または請求項６のいずれかに記載のガラスセラミック焼結体。7. The glass ceramic sintered body according to claim 5, wherein the transverse rupture strength is 150 MPa or more. ＰｂＯおよびＡ２Ｏ（Ａ：アルカリ金属）の含有量がそれぞれ０．１質量％以下であることを特徴とする請求項５乃至請求項７のいずれかに記載のガラスセラミック焼結体。PbO and A 2 O (A: alkali metal) glass ceramic sintered body according to any one of claims 5 to 7 content is characterized in that 0.1 wt% or less each. 少なくとも、ＳｉＯ２ ３０〜７０質量％、Ａｌ２Ｏ３ ５〜３０質量％、ＭｇＯ ３〜２５質量％、ＢａＯ ３〜２５質量％、Ｂ２Ｏ３ １〜１５質量％、ＺｎＯ １〜１５質量％、を含有するガラス粉末６０〜９９質量％とコーディエライト、ムライト、アノーサイト、スラウソナイト、セルジアン、石英ガラスの群から選ばれる少なくとも１種のフィラー粉末１〜４０質量％を混合、成形し、大気中あるいは窒素雰囲気中で１０５０℃以下の温度にて焼成して得られることを特徴とする請求項５乃至請求項８のいずれかに記載のガラスセラミック焼結体。At least, SiO 2 30 to 70 wt%, Al 2 O 3 5~30 wt%, MgO 3 to 25 mass%, BaO 3 to 25 wt%, B 2 O 3 1~15 wt%, ZnO 1 to 15 wt% Is mixed with 60 to 99% by mass of a glass powder containing 1 to 40% by mass of at least one filler powder selected from the group consisting of cordierite, mullite, anorthite, slausonite, Celsian, and quartz glass, molded and air-mixed. The glass ceramic sintered body according to any one of claims 5 to 8, which is obtained by firing at a temperature of 1050 ° C or lower in a medium or a nitrogen atmosphere. 絶縁基板の表面および／または内部に、低抵抗金属を含有する配線層を配設してなる配線基板において、前記絶縁基板が、請求項５乃至請求項９のいずれかに記載のガラスセラミック焼結体からなることを特徴とする配線基板。10. A glass ceramic sintered body according to claim 5, wherein a wiring layer containing a low-resistance metal is disposed on a surface and / or inside of the insulating substrate. A wiring board comprising a body. 前記配線基板の表面に、Ｓｉ（シリコン）を主体とする半導体素子を載置してなることを特徴とする請求項１０記載の配線基板。The wiring substrate according to claim 10, wherein a semiconductor element mainly composed of Si (silicon) is mounted on the surface of the wiring substrate. 請求項１０または請求項１１のいずれかに記載の配線基板を、有機樹脂を含有する絶縁基板を具備するプリント配線基板の表面に実装してなることを特徴とする配線基板の実装構造。A mounting structure of a wiring board, wherein the wiring board according to claim 10 or 11 is mounted on a surface of a printed wiring board having an insulating substrate containing an organic resin.
JP2003020861A 2003-01-29 2003-01-29 Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate Pending JP2004231453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003020861A JP2004231453A (en) 2003-01-29 2003-01-29 Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003020861A JP2004231453A (en) 2003-01-29 2003-01-29 Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate

Publications (1)

Publication Number Publication Date
JP2004231453A true JP2004231453A (en) 2004-08-19

Family

ID=32950378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003020861A Pending JP2004231453A (en) 2003-01-29 2003-01-29 Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate

Country Status (1)

Country Link
JP (1) JP2004231453A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006232645A (en) * 2005-02-28 2006-09-07 Kyocera Corp Glass ceramic composition, glass ceramic sintered compact, wiring board using the same and mounting structure of the same
JP2010006690A (en) * 2008-06-26 2010-01-14 Korea Inst Of Science & Technology Low permittivity dielectric ceramic composition for low temperature firing
WO2012036219A1 (en) * 2010-09-17 2012-03-22 旭硝子株式会社 Light-emitting element substrate and light-emitting device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006232645A (en) * 2005-02-28 2006-09-07 Kyocera Corp Glass ceramic composition, glass ceramic sintered compact, wiring board using the same and mounting structure of the same
JP2010006690A (en) * 2008-06-26 2010-01-14 Korea Inst Of Science & Technology Low permittivity dielectric ceramic composition for low temperature firing
WO2012036219A1 (en) * 2010-09-17 2012-03-22 旭硝子株式会社 Light-emitting element substrate and light-emitting device
JPWO2012036219A1 (en) * 2010-09-17 2014-02-03 旭硝子株式会社 Light emitting element substrate and light emitting device

Similar Documents

Publication Publication Date Title
JP3426926B2 (en) Wiring board and its mounting structure
JP2005306714A (en) Glass ceramic composition, glass ceramic sintered body and manufacturing method for the same, and circuit board and thin film circuit board both using the same
JP4780995B2 (en) Glass ceramic sintered body and wiring board using the same
JP2012167008A (en) Glass ceramic composition, glass ceramic sintered compact, wiring board using the same, and mounting structure of the same
JP2003342060A (en) Glass ceramic sintered compact and wiring board
JP4549029B2 (en) Glass ceramic composition, glass ceramic sintered body, method for producing glass ceramic sintered body, and wiring board
JP4703207B2 (en) Wiring board
JP4549028B2 (en) Glass ceramic composition, glass ceramic sintered body, method for producing glass ceramic sintered body, and wiring board
JP2002362937A (en) Glass composition, glass sintered compact and wiring board obtained by using the sintered compact
JP5383962B2 (en) Glass ceramic composition, glass ceramic sintered body, wiring board using the same, and mounting structure thereof
JP2004231453A (en) Glass-ceramic composition, glass-ceramic sintered compact, wiring substrate using the compact, and packaging structure of the wiring substrate
JP2001261432A (en) Porcelain composition for high-frequency and porcelain for high-frequency
JP2004168557A (en) Glass ceramic composition, glass ceramic sintered compact, its manufacturing process, wiring board using the same and its mounted structure
JP4077625B2 (en) Low temperature fired porcelain composition and method for producing low temperature fired porcelain
JP3865967B2 (en) Porcelain and wiring board using the same
JP3559407B2 (en) Glass ceramic sintered body and multilayer wiring board using the same
JP2004143010A (en) Glass-ceramic composition, glass-ceramic sintered compact, and wiring board using the same and installation structure of the same
JP4383113B2 (en) Manufacturing method of multilayer wiring board
JP2007119288A (en) Glass ceramic sintered compact, its producing method and wiring board
JP3719834B2 (en) Low temperature fired ceramics
JP3643264B2 (en) Conductive paste and wiring board using the same
JP3339999B2 (en) Wiring board, semiconductor device storage package using the same, and mounting structure thereof
JP2004323308A (en) Low-temperature firing ceramic composition, low-temperature firing ceramic and method for manufacturing the same as well as wiring board using the same and packaging structure thereof
JP3323074B2 (en) Wiring board, package for housing semiconductor element and its mounting structure
JP2005101095A (en) Porcelain composition, porcelain, and its manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050712

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080916

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081014

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090227