JPH088329B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents
Semiconductor integrated circuit device and manufacturing method thereofInfo
- Publication number
- JPH088329B2 JPH088329B2 JP63311975A JP31197588A JPH088329B2 JP H088329 B2 JPH088329 B2 JP H088329B2 JP 63311975 A JP63311975 A JP 63311975A JP 31197588 A JP31197588 A JP 31197588A JP H088329 B2 JPH088329 B2 JP H088329B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- lead
- circuit chip
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は、例えばICを組み込んだカードなどに好ま
しくは用いることができる半導体集積回路装置及びその
製造方法に関し、特に装置の薄形化に関するものであ
る。Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device which can be preferably used, for example, in a card incorporating an IC, and a method for manufacturing the same, and more particularly to thinning of the device. Is.
［従来の技術］ 第６図〜第９図は従来の一般的な半導体集積回路装置
または、その製造方法を説明するための図であり、第６
図は、リードフレームの一部を示す斜視図、第７図は、
ワイヤーボンド完了時点の状態を示す斜視図、第８図は
樹脂封止された状態を示す斜視図、第９図はパツケイジ
厚みを説明する為の断面図である。[Prior Art] FIGS. 6 to 9 are views for explaining a conventional general semiconductor integrated circuit device or a manufacturing method thereof.
FIG. 7 is a perspective view showing a part of the lead frame, and FIG.
FIG. 8 is a perspective view showing a state at the time of completion of wire bonding, FIG. 8 is a perspective view showing a resin-sealed state, and FIG. 9 is a sectional view for explaining a package thickness.
リードフレーム（１）は、第６図に示すようにダイパ
ツド（２）、外部引出用リード（３）を有している。別
工程で製造された半導体集積回路チップ（４）は、第７
図に示されるようにダイパツド（２）上に、樹脂やロー
材（図示省略）等で接着される。その後、金属細線から
なるワイヤ（５）によつて、チツプ（４）上の電極（図
示省略）と、外部引出用リード（３）のインナーリード
部（3a）とを電気的に接続する。次いで第８図に示すよ
うに、例えばエポキシ樹脂組成物などのパツケイジ材
（６）により封止成形し、さらに外部引出用リード
（３）を所定の形状に加工することにより目的とする半
導体集積回路（８）が得られる。（第９図） ［発明が解決しようとする課題］ 従来の半導体集積回路装置は以上のように構成され、
製造されているので、第９図に示すようにパツケイジ厚
としては、金属細線が封止樹脂より露出しない厚み
Ａ、チツプ厚Ｂ、ダイパツド厚Ｃ、及びダイパツ
ド下面の樹脂厚Ｄの４項目の合計が必要であり、この
為、約1mmより薄いパツケイジを得ることが出来ず、さ
らに薄いパツケイジの要求を満足することが困難である
という問題があつた。The lead frame (1) has a die pad (2) and an external lead (3) as shown in FIG. The semiconductor integrated circuit chip (4) manufactured in a separate process has a seventh
As shown in the figure, it is adhered onto the die pad (2) with a resin or a brazing material (not shown). After that, an electrode (not shown) on the chip (4) and the inner lead portion (3a) of the external lead (3) are electrically connected by a wire (5) made of a thin metal wire. Next, as shown in FIG. 8, a target semiconductor integrated circuit is obtained by sealing and molding with a package material (6) such as an epoxy resin composition, and further processing the external lead (3) into a predetermined shape. (8) is obtained. (FIG. 9) [Problems to be Solved by the Invention] A conventional semiconductor integrated circuit device is configured as described above,
Since it is manufactured, as shown in FIG. 9, as the package thickness, a total of four items, that is, the thickness A at which the thin metal wire is not exposed from the sealing resin, the chip thickness B, the die pad thickness C, and the resin thickness D on the lower surface of the die pad Therefore, there was a problem that it was impossible to obtain a package thinner than about 1 mm, and it was difficult to satisfy the requirements for a thinner package.
この発明は上記のような問題点を解決する為になされ
たもので、超薄形の半導体集積回路装置及びその製造方
法を提供することを目的とする。The present invention has been made to solve the above problems, and an object thereof is to provide an ultrathin semiconductor integrated circuit device and a manufacturing method thereof.
［課題を解決するための手段］］ この発明に係る半導体集積回路装置は、半導体集積回
路チップは、その裏面が外部引出用リードの裏面より下
方に位置するように、上記外部引出用リードに対し、ワ
イヤ接続面とは反対方向に変位して配設され、かつ、半
導体集積回路チップの背面部にはダイパッドが存在せず
裏面が露出するようにパッケイジ材に封止され、さら
に、少なくとも一対の吊りリードが、半導体集積回路チ
ップと離間して半導体集積回路チップを挟んで配設さ
れ、かつ、その裏面が半導体集積回路チップの裏面と同
じ面位置で露出するようにパッケイジ材に封止されてい
るものである。[Means for Solving the Problem] In the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit chip is mounted on the external lead-out lead so that its back surface is located below the back surface of the external lead-out lead. , Is displaced in the opposite direction to the wire connection surface, and is sealed with a package material so that the back surface of the semiconductor integrated circuit chip does not have a die pad and the back surface is exposed. The suspension lead is arranged so as to be separated from the semiconductor integrated circuit chip with the semiconductor integrated circuit chip interposed therebetween, and is sealed with a package material so that the back surface of the suspension lead is exposed at the same surface position as the back surface of the semiconductor integrated circuit chip. There is something.
また、その製造方法は、リードフレームの外部引出用
リードの延在面から変位した位置にダイパッドを接着す
る工程、上記ダイパツドに半導体集積回路チツプを接着
する工程、及びパツケイジ材による封止工程の後、上記
ダイパツドを除去する工程を含むように構成したもので
ある。In addition, the manufacturing method includes a step of adhering a die pad to a position displaced from the extending surface of the lead-out lead of the lead frame, a step of adhering a semiconductor integrated circuit chip to the die pad, and a step of sealing with a package material. It is configured to include a step of removing the die pad.
［作用］ この発明における半導体集積回路装置は半導体集積回
路チツプを外部引出用リードの延在面から変位して配設
すると共に、ダイパツドを除去したことにより、装置の
厚みを薄形化している。[Operation] In the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit chip is disposed while being displaced from the extending surface of the lead for external extraction, and the die pad is removed, thereby making the device thin.
［実施例］ 以下、この発明の実施例を図について説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.
第１図〜第５図は上記実施例を説明するためのもの
で、第１図は完成状態を示す断面図、第２図は本発明の
実施例に用いるリードフレームを示す斜視図、第３図は
分離独立されたダイパツドを示す斜視図、第４図は第３
図のダイパッド（20）を第２図のリードフレームに接着
固定した状態を示す斜視図、第５図は樹脂封止後の構造
を示す断面図である。1 to 5 are for explaining the above embodiment, FIG. 1 is a sectional view showing a completed state, FIG. 2 is a perspective view showing a lead frame used in an embodiment of the present invention, and FIG. FIG. 4 is a perspective view showing the die pad which is separated and independent, and FIG.
FIG. 5 is a perspective view showing a state in which the die pad (20) shown in the figure is adhesively fixed to the lead frame in FIG. 2, and FIG. 5 is a sectional view showing the structure after resin sealing.
上記実施例に用いたリードフレームは第２図に示すよ
うに、吊りリード（９）（９）が設けられており、集積
回路チツプを保持するためのダイパツドを有していな
い。ダイパツド（20）は第３図に示すように、リードフ
レームとは別途にパツケイジとほぼ同一の大きさに加工
される。なお、（20a）は集積回路チツプ（４）の載置
エリアである。このダイパツド（20）を第４図に示すよ
うにリードフレームの吊りリード（９）に接着し、その
後ないしはそれ以前に半導体集積回路チツプ（４）を載
置エリア（20a）に接着する。この接着に使用する材料
は、融点のはつきりした半田等のロー材や軟化点のはつ
きりしている熱可塑性樹脂を使用することが好ましい。
この後、使用した接着材料の融点又は軟化点以下でワイ
ヤーボンドしさらに樹脂からなるパツケイジ材（６）に
よつて封止する。この場合に用いる樹脂封止用金型（図
示省略）はダイパツド（20）の側面、裏面に樹脂が回り
込まぬ様、ダイパツド（20）と寸法の整合をとる必要が
ある。As shown in FIG. 2, the lead frame used in the above embodiment is provided with suspension leads (9) and (9) and does not have a die pad for holding an integrated circuit chip. As shown in FIG. 3, the die pad (20) is machined separately from the lead frame to have substantially the same size as the package. Incidentally, (20a) is a mounting area of the integrated circuit chip (4). The die pad (20) is bonded to the suspension leads (9) of the lead frame as shown in FIG. 4, and the semiconductor integrated circuit chip (4) is bonded to the mounting area (20a) after that or before it. As a material used for this adhesion, it is preferable to use a brazing material such as solder having a melting point or a thermoplastic resin having a softening point.
After that, wire bonding is performed below the melting point or softening point of the adhesive material used, and the package material (6) made of resin is used for sealing. The resin sealing die (not shown) used in this case needs to be dimensionally matched with the die pad (20) so that the resin does not wrap around the side surface and the back surface of the die pad (20).
この様にして樹脂封止した後の断面を示した図が第５
図である。なお、同図中、（10）は接着材である。この
後、ダイパツド（20）を接着材（10）の融点又は軟化点
以上に昇温させてダイパツド（20）を吊りリード（９）
及び半導体集積回路チツプ（４）から剥離する。この剥
離後の状態を示した図が第１図である。The cross-sectional view after resin sealing in this way is shown in FIG.
FIG. In the figure, (10) is an adhesive material. Thereafter, the die pad (20) is heated to a temperature equal to or higher than the melting point or softening point of the adhesive material (10), and the die pad (20) is suspended in the lead (9).
And the semiconductor integrated circuit chip (4). FIG. 1 shows the state after the peeling.
剥離後、チツプ（４）の裏面は露出しているか、ある
いは薄い接着材（10）の膜でコートされた状態となる。After peeling, the back surface of the chip (4) is exposed or is in a state of being coated with a thin film of the adhesive material (10).
このように上記実施例ではダイパツドを除去すること
により薄形化した半導体集積回路装置を得ることができ
る。さらに、半導体集積回路チップ（４）の裏面が引出
用リード（3a）の裏面より下方に位置しているので、引
出用リード（3a）のワイヤ接続面からのワイヤ（５）頂
点の高さがその分低くなる。その結果、ワイヤ（５）が
パツケイジ材（６）より露出しない厚みＡ、すなわち半
導体集積回路チップ（４）の上部側のパッケイジ材
（６）の厚みがその分薄くなり、薄形化した半導体集積
回路装置を得ることができる。As described above, in the above-described embodiment, the thin semiconductor integrated circuit device can be obtained by removing the die pad. Furthermore, since the back surface of the semiconductor integrated circuit chip (4) is located below the back surface of the lead-out lead (3a), the height of the apex of the wire (5) from the wire connection surface of the lead-out lead (3a) is That will be lower. As a result, the thickness A at which the wire (5) is not exposed from the package material (6), that is, the thickness of the package material (6) on the upper side of the semiconductor integrated circuit chip (4) is correspondingly reduced, and the semiconductor integrated circuit is reduced in thickness. A circuit device can be obtained.
また、上記実施例では、ダイパツド（20）とリードフ
レーム（１）とを別体に構成したが、吊りリード（９）
の位置をかえることにより一体に構成しても差支えな
い。さらに吊りリード（９）がパツケージ材（６）の内
部に残留するようにしたが、これに限定されるものでは
ない。Further, in the above-mentioned embodiment, the die pad (20) and the lead frame (1) are configured separately, but the suspension lead (9)
It does not matter if they are integrally formed by changing the position of. Furthermore, the suspension lead (9) is made to remain inside the package material (6), but the present invention is not limited to this.
［発明の効果］ 以上のように、この発明によれば、半導体集積回路チ
ップは、その裏面が外部引出用リードの裏面より下方に
位置するように、外部引出用リードに対し、ワイヤの接
続面とは反対方向に変位して配設すると共に、集積回路
チツプの背面部からダイパツドを取り去ることにより超
薄型パツケイジからなる半導体集積回路装置が得られる
効果がある。As described above, according to the present invention, in the semiconductor integrated circuit chip, the connecting surface of the wire is connected to the external drawing lead so that the back surface of the semiconductor integrated circuit chip is located below the rear surface of the external drawing lead. The semiconductor integrated circuit device composed of an ultra-thin package can be obtained by disposing the semiconductor integrated circuit chip in a direction opposite to the above and arranging the die pad from the back surface of the integrated circuit chip.
第１図〜第５図はこの発明の一実施例を説明するための
図であり、第１図は最終的に得られた半導体集積回路装
置を示す要部断面図、第２図は用いたリードフレームの
要部を示す斜視図、第３図は用いたダイパツドを示す斜
視図、第４図は上記ダイパツドを上記リードフレームに
接着した状態を示す斜視図、第５図はパツケイジ材によ
つて封止した状態を示す断面図である。 第６図〜第９図は従来装置及び従来の製造法を説明する
図であり、第６図はリードフレームの要部を示す斜視
図、第７図はワイヤーボンデイングの完了した状態を示
す斜視図、第８図はパツケイジ材によるモールドの完了
した状態を示す斜視図、第９図は第８図のIX−IX線にお
ける断面図である。 図において、（３）は外部引出用リード、（４）は半導
体集積回路チツプ、（５）はワイヤ、（６）はパツケイ
ジ材である。 なお、各図中、同一符号は同一又は相当部分を示す。1 to 5 are views for explaining one embodiment of the present invention. FIG. 1 is a cross-sectional view of an essential part showing a semiconductor integrated circuit device finally obtained, and FIG. 2 is used. FIG. 3 is a perspective view showing a main part of the lead frame, FIG. 3 is a perspective view showing a die pad used, FIG. 4 is a perspective view showing a state in which the die pad is bonded to the lead frame, and FIG. 5 is a package material. It is sectional drawing which shows the state which was sealed. 6 to 9 are views for explaining a conventional device and a conventional manufacturing method, FIG. 6 is a perspective view showing a main part of a lead frame, and FIG. 7 is a perspective view showing a state where wire bonding is completed. FIG. 8 is a perspective view showing a completed state of molding with a package material, and FIG. 9 is a sectional view taken along line IX-IX in FIG. In the figure, (3) is a lead for external extraction, (4) is a semiconductor integrated circuit chip, (5) is a wire, and (6) is a package material. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (2)
ームの外部引出用リードとをワイヤによって電気的に接
続し、これら半導体集積回路チップ、ワイヤ及び外部引
出用リードをパッケイジ材によって一体的に封止してな
るものにおいて、 上記半導体集積回路チップは、その裏面が上記外部引出
用リードの裏面より下方に位置するように、上記外部引
出用リードに対し、ワイヤ接続面とは反対方向に変位し
て配設され、かつ、上記半導体集積回路チップの背面部
にはダイパッドが存在せず裏面が露出するように上記パ
ッケイジ材に封止され、 さらに、少なくとも一対の吊りリードが、上記半導体集
積回路チップと離間して上記半導体集積回路チップを挟
んで配設され、かつ、その裏面が上記半導体集積回路チ
ップの裏面と同じ面位置で露出するように上記パッケイ
ジ材に封止されていることを特徴とする半導体集積回路
装置。1. An electrode of a semiconductor integrated circuit chip and an external lead of a lead frame are electrically connected by a wire, and the semiconductor integrated circuit chip, the wire and the external lead of the lead frame are integrally sealed by a package material. In the semiconductor integrated circuit chip, the semiconductor integrated circuit chip is displaced in a direction opposite to the wire connecting surface with respect to the external lead-out lead so that the back surface of the semiconductor integrated circuit chip is located below the back surface of the external lead-out lead. The semiconductor integrated circuit chip is disposed and is sealed in the package material so that the back surface of the semiconductor integrated circuit chip does not have a die pad and the back surface is exposed. The semiconductor integrated circuit chips are arranged so as to be separated from each other, and the back surface thereof is exposed at the same surface position as the back surface of the semiconductor integrated circuit chip. That is sealed to the Pakkeiji material to a semiconductor integrated circuit device according to claim.
面から変位した位置にダイパッドを接着する工程、上記
ダイパッドに半導体集積回路チップを接着する工程、パ
ッケイジ材による封止工程の後、上記ダイパッドを除去
する工程を含むことを特徴とする半導体集積回路装置の
製造方法。2. A die pad is attached to a position displaced from the extending surface of the lead-out lead of the lead frame, a semiconductor integrated circuit chip is attached to the die pad, and a die material is sealed. A method of manufacturing a semiconductor integrated circuit device, comprising the step of removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311975A JPH088329B2 (en) | 1988-12-12 | 1988-12-12 | Semiconductor integrated circuit device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63311975A JPH088329B2 (en) | 1988-12-12 | 1988-12-12 | Semiconductor integrated circuit device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02158159A JPH02158159A (en) | 1990-06-18 |
| JPH088329B2 true JPH088329B2 (en) | 1996-01-29 |
Family
ID=18023692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63311975A Expired - Fee Related JPH088329B2 (en) | 1988-12-12 | 1988-12-12 | Semiconductor integrated circuit device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088329B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3088193B2 (en) * | 1992-06-05 | 2000-09-18 | 三菱電機株式会社 | Method for manufacturing semiconductor device having LOC structure and lead frame used therein |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5240062A (en) * | 1975-09-26 | 1977-03-28 | Hitachi Ltd | Process for production of semiconductor devices |
| JPS61102089A (en) * | 1984-10-25 | 1986-05-20 | 松下電工株式会社 | Mount structure of flat package ic |
| CA1238119A (en) * | 1985-04-18 | 1988-06-14 | Douglas W. Phelps, Jr. | Packaged semiconductor chip |
| JPS61182036U (en) * | 1985-05-02 | 1986-11-13 | ||
| JPS63240055A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Semiconductor device |
-
1988
- 1988-12-12 JP JP63311975A patent/JPH088329B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02158159A (en) | 1990-06-18 |
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