JPH0864857A - 光電変換半導体装置 - Google Patents

光電変換半導体装置

Info

Publication number
JPH0864857A
JPH0864857A JP6198787A JP19878794A JPH0864857A JP H0864857 A JPH0864857 A JP H0864857A JP 6198787 A JP6198787 A JP 6198787A JP 19878794 A JP19878794 A JP 19878794A JP H0864857 A JPH0864857 A JP H0864857A
Authority
JP
Japan
Prior art keywords
semiconductor device
pin photodiode
type impurity
region
impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6198787A
Other languages
English (en)
Inventor
Keiji Sato
恵二 佐藤
Yutaka Saito
豊 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP6198787A priority Critical patent/JPH0864857A/ja
Publication of JPH0864857A publication Critical patent/JPH0864857A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Light Receiving Elements (AREA)

Abstract

(57)【要約】 【目的】 高周波領域でのインピーダンスが小さく、低
周波領域でのインピーダンスが大きくて信号光以外の光
の影響をうけにくい光電変換半導体装置を実現する。 【構成】 N- 型半導体基板1の表面にはP+ 型不純物
領域2とその電極であるアノード電極5およびN+ 型不
純物領域4とその電極であるカソード電極6を持ち、外
囲器12との結線は、アノード電極5およびカソード電
極6と外囲器の導体部7および8とはそれぞれともにワ
イヤボンデング9,11により行う。

Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は光電変換半導体装置に関
するものである。
【0002】
【従来の技術】従来、光電変換半導体装置としては、図
3に図示するように、N- 型半導体基板1の第1の面
(以下表面と呼ぶ)にP+ 型不純物領域2とその電極で
あるアノード電極5および基板より高い濃度のN型であ
るN+ 型不純物領域4とその電極であるカソード電極6
を持ち、裏面には基板より高い濃度のN型である裏面の
N+型不純物領域3がありP+ −N-+ よりなるPN
接合を形成する半導体装置が知られていた。
【0003】N- 型半導体基板1の不純物濃度が1×1
12atms/cm3 から1×10 13atms/cm3
程度のものをさしてイントリンシック(intrins
ic、真性半導体)のiをとってPINと称される。こ
こでN- 、N+ 、P+ などはそれぞれの導電型不純物に
おいてNあるいはPより−は不純物濃度が低いことを、
+は高いことを意味している。
【0004】i層は濃度が低くまた厚さとしては数10
から数100μmであり、PN接合に逆バイアスを加え
た時の空乏層の伸びが大きく、検出する光や放射線のエ
ネルギーの範囲が大きく取れることや、比較的大きなバ
イアスを加えることができ、その時の接合容量が少ない
という点から高速応答に適しており広く使われている。
【0005】このPINフォトダイオードとたとえば外
囲器12との結線(すなわち導通)は、アノード電極5
と外囲器の導体部7はワイヤボンデング9により、裏面
のN + 純物領域3と外囲器の導体部8とは導電接着剤1
0により行うことによりなされていた。
【0006】このようなPINフォトダイオードは光通
信や光ディスク、リモートコントロールなどの受光素子
として利用されている。
【0007】
【発明が解決しようとする課題】PINフォトダイオー
ドをたとえばリモートコントロールの受信側の受光素子
として使用する場合、送信側の発光部以外の外部の光
が、すなわち信号光以外の外乱となる光のためたとえば
発光部のLED素子の発する波長以外の光を遮光するよ
うな工夫を施しているが十分とは言えなかった。
【0008】本発明の目的はPINフォトダイオードあ
るいはPINフォトダイオードをもとに構成される光電
変換半導体装置このような課題を解決することである。
【0009】
【課題を解決するための手段】前記課題を解決するため
本発明では高抵抗N型基板の第1の面にP型不純物領域
とN型不純物領域K各々の電極としてのアノード電極お
よびカソード電極とPINフォトダイオード外の導体部
との結線をワイヤボンディングによって行う。
【0010】
【作用】前記手段を取ることで高周波領域での直列抵抗
が減少しかつインピーダンスが低周波で増加する。外乱
は低周波部分が顕著であるためインピーダンスの増加に
より外乱の影響を除去できる。
【0011】
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図1は本発明にかかるPINフォトダイオ
ードの1実施例を示す模式的断面図である。
【0012】N- 型半導体基板1の表面にはP+ 型不純
物領域2とその電極であるアノード電極5およびN+
不純物領域4とその電極であるカソード電極6を持ち、
外囲器12との結線(すなわち導通)は、アノード電極
5およびカソード電極6と外囲器の導体部7および8と
はそれぞれともにワイヤボンデング9,11により行わ
れている。
【0013】図2はPINフォトダイオードのインピー
ダンス−周波数特性図であり、曲線21は本発明のPI
Nフォトダイオードのインピーダンス曲線であり、曲線
22は従来のPINフォトダイオードのインピーダンス
曲線である。100kHz付近をさかいに高周波領域で
は本発明のPINフォトダイオードのインピーダンスが
小さくなり、数10kHz以下では本発明のPINフォ
トダイオードのインピーダンスが急激に増加しているこ
とがわかる。
【0014】このような本発明のPINフォトダイオー
ドをリモートコントロール装置の受光部に組み込んだと
ころ、従来のPINフォトダイオードをリモートコント
ロール装置の受光部に組み込んだものより外光の影響を
受けにくかった。また同一ウェハー上に増幅回路等の他
の回路や回路素子を形成しそれらとPINフォトダイオ
ードを本発明の方法でワイヤボンデングで結線した場合
やPINフォトダイオードと実装基板上の他の回路や回
路素子とを本発明の方法での結線した場合も同様にの効
果があった。
【0015】
【発明の効果】以上説明してきたように、本発明の構成
によれば、高周波領域でのインピーダンスが小さく、低
周波領域でのインピーダンスが大きいPINフォトダイ
オードが得られ、従って低周波領域が主となる外乱の影
響の小さい光電変換半導体装置を実現できる。
【図面の簡単な説明】
【図1】本発明によるPINフォトダイオードの断面図
である。
【図2】PINフォトダイオードのインピーダンス−周
波数特性図である。
【図3】従来のPINフォトダイオードの断面図であ
る。
【符号の説明】
1 N- 型半導体基板 2 P+ 型不純物領域 3 裏面のN+ 型不純物領域 4 N+ 型不純物領域 5 アノード電極 6 カソード電極 7,8 外囲器の導体部 9,11 ワイヤボンディング 10 導電接着剤 21 本発明のPINフォトダイオードのインピーダン
ス曲線 22 従来のPINフォトダイオードのインピーダンス
曲線

Claims (1)

    【特許請求の範囲】
  1. 【請求項1】 半導体基板と第1の不純物領域と第2の
    不純物領域と電極を有する光電変換半導体装置におい
    て、第1の不純物領域に接する電極と外部接続端子間に
    ワイヤボンディングによる配線を有し、第2の不純物領
    域に接する電極と外部接続端子間にワイヤボンディング
    による配線を有することを特徴とする光電変換半導体装
    置。
JP6198787A 1994-08-23 1994-08-23 光電変換半導体装置 Pending JPH0864857A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6198787A JPH0864857A (ja) 1994-08-23 1994-08-23 光電変換半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6198787A JPH0864857A (ja) 1994-08-23 1994-08-23 光電変換半導体装置

Publications (1)

Publication Number Publication Date
JPH0864857A true JPH0864857A (ja) 1996-03-08

Family

ID=16396907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6198787A Pending JPH0864857A (ja) 1994-08-23 1994-08-23 光電変換半導体装置

Country Status (1)

Country Link
JP (1) JPH0864857A (ja)

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