JPH0836374A - Display device - Google Patents

Abstract

PURPOSE:To improve display image quality by decreasing phenomena that images look discontinuous at the time of thinning lines of video signals at a specified ratio. CONSTITUTION:A display panel 1 has plural pixels 4 which include a prescribed number of pieces of the lines per field and are arranged in matrix according to standards (for example, NTSC standards) of the existing video signals, a vertical driving circuit 5 which sequentially selects the pixels 4 for the one-line component and a horizontal driving circuit 6 which writes the one line- component of the video signals Vsig into the pixels 4 of the selected one line- component. A decoder/driver 2 is capable of inputting the specific video signals (for example, the video signals complying with PAL standards) larger in the number of pieces of the lines per field than the existing video signals into the display panel 1. A timing generator 3 timing controls the sequential selection by the vertical driving circuit 5 and thins the excess lines included in the specific video signals inputted to the display panel 1 at a prescribed ratio. At this time, a thinning sequencer 3a supplies the thinning sequence signals at every field to the timing generator 3. The timing generator 3 changes the positions of the lines to be thinned at each of the respective fields according thereto.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a display panel, a decoder / driver for supplying a video signal to the display panel, and a timing generator for controlling driving of the display panel. More specifically, the present invention relates to a display device capable of inputting a video signal according to the PAL standard to a display panel configured according to the NTSC standard.

[0002]

2. Description of the Related Art In Japan, the NTSC system is adopted, and one screen is composed of 525 lines. Therefore, the active matrix type display panel is normally NTS
It is configured in accordance with the C standard and can display a predetermined line per field. However, other methods are used in foreign countries, such as P in Europe.
AL standard and SECAM standard are mentioned. In the PAL system, one screen is composed of 625 lines. Conventionally,
When inputting a PAL system video signal to a display panel designed for the NTS system, the number of lines that can be displayed is fixed in an active matrix type liquid crystal display panel, etc. The operation of thinning the line is required.

[0003]

However, if the lines determined by a fixed ratio are simply thinned out, the information of the thinned lines is completely lost, and the displayed image looks discontinuous. However, there is a problem that deterioration of image quality is noticeable.

[0004]

Means for Solving the Problems In order to solve the above-mentioned problems of the conventional technique, the following means were taken. That is, the display device according to the present invention has, as a basic configuration, a display panel, a signal source that supplies a video signal to the display panel, and a timing unit that controls driving of the display panel. The display panel includes a plurality of pixels arranged in a matrix in accordance with a standard of a predetermined video signal including a predetermined number of lines per field, a vertical drive circuit that sequentially selects pixels for one row, and an image for pixels for one selected row. And a horizontal drive circuit for writing one line of a signal. The signal source can input a specific video signal having more lines per field than the default video signal to the display panel. Characteristically, the timing means controls timing of sequential selection by the vertical drive circuit to thin out excess lines included in a specific video signal input to the display panel at a predetermined ratio, and thin out for each field. The position of the broken line is changing.

Specifically, the display panel is, for example, 52
It has a plurality of pixels arranged in rows and columns according to the NTSC standard of a predetermined video signal consisting of five lines. On the other hand, the signal source inputs a specific video signal composed of 625 lines according to the PAL standard to the display panel. In this case, the timing means thins out the excess lines while changing the position at a ratio of one to six or one to seven. For example, the timing means can alternately change the positions of the thinned lines in the first field and the second field. Alternatively, instead of this, the timing means may cyclically shift and change the positions of the lines to be thinned by using three or more fields as a cycle. The display panel is an active matrix liquid crystal display panel including a plurality of pixels each including a pixel electrode, a counter electrode facing the pixel electrode through a gap, a liquid crystal held in the gap, and a switching element driving the pixel electrode. Can be used.

[0006]

According to the present invention, in a display panel having a fixed number of display lines, such as an active matrix type liquid crystal display panel, the lines are kept constant when, for example, a PAL system video signal is input to the NTS system display panel. By thinning out different lines for each field when thinning out at the ratio of, the phenomenon that the image looks discontinuous is reduced and the display image quality is improved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of a display device according to the present invention. As shown in the figure, this display device comprises a display panel 1, a signal source for supplying a video signal to the display panel 1, and a timing means for controlling the driving of the display panel 1. A decoder / driver 2 is used as a signal source, and a combination of a timing generator 3 and a thinning sequencer 3a is used as timing means. The display panel 1 has a plurality of pixels 4, a vertical drive circuit 5, and a horizontal drive circuit 6. The plurality of pixels 4 are
The matrix is arranged according to the standard of a predetermined video signal including a predetermined number of lines per field (for example, NTSC standard). The vertical drive circuit 5 sequentially selects pixels for one row.
The horizontal drive circuit 6 writes one line of the video signal into the selected one row of pixels. The decoder / driver 2 can input a specific video signal having more lines per field than the default video signal to the display panel 1. The timing generator 3 timing-controls sequential selection by the vertical drive circuit 5 to thin out excess lines included in a specific video signal input to the display panel at a predetermined ratio. As a feature of the present invention, the thinning sequencer 3a controls the timing generator 3 to change the position of the thinned line for each field. Specifically, the thinning-out sequencer 3a supplies a thinning-out sequence signal for specifying the positions of the lines to be thinned out for each field to the timing generator 3. The timing generator 3 receives the thinning-out sequence signal and receives the vertical drive circuit 5
The operation of the horizontal drive circuit 6 is controlled so that the corresponding line is not displayed.

In the present example, the display panel 1 has a plurality of pixels arranged in rows and columns according to the NTSC standard of a predetermined video signal composed of 525 lines. On the other hand, the decoder / driver inputs to the display panel 1 a specific video signal consisting of 625 lines according to the PAL standard. The timing generator 3 thins out excess lines at a rate of one in six or one in seven. At this time, the thinning sequencer 3a supplies a predetermined thinning sequence signal to the timing generator 3 so as to thin out the extra lines while changing the position for each field.

The function of each unit will be described in detail with reference to FIG. The display panel 1 has a screen according to the NTSC standard. Innumerable pixels 4 are arranged in a matrix on this screen. The display panel 1 performs a normal display operation when an NTSC standard video signal is input, and performs a predetermined thinning display drive when a PAL standard video signal Vsig is input. In this example, the display panel 1 is a full-color type, and receives the video signal Vsig divided for each of the RGB three primary colors. The display panel 1 includes a vertical drive circuit 5 and sequentially selects the pixels 4 for one row. In addition, the horizontal drive circuit 6 is provided, and the video signal Vs is supplied to the selected pixels 4 for one row.
Write one line of ig (one horizontal period). Note that P
When the AL standard video signal Vsig is input, the vertical drive circuit 5 performs a thinning operation and timing-controls the above-mentioned sequential selection to thin a predetermined number of extra lines from the PAL standard video signal Vsig for display.

The decoder / driver 2 has, for example, a decoder section which receives a power supply voltage of 5V and a driver section which receives a power supply voltage of 12V. The decoder unit decodes the composite video signal VIDEO input from the outside and extracts a luminance signal and a chroma signal. Also composite video signal VI
The sync signal SYNC separated from DEO is transferred to the timing generator 3 side. The driver unit divides the alternating video signal Vsig into RGB signals according to the inversion signal FRP input from the timing generator 3 and supplies them to the display panel 1 side.

The timing generator 3 has a synchronizing signal SY.
Various timing signals are created based on NC and supplied to the display panel 1 to control the timing. That is, the first timing signals (vertical start signal VST, vertical clock signals VCK1 and VCK2) are supplied to the vertical drive circuit 5 to sequentially select pixels for one row. Further, the second timing signal (horizontal start signal HST, horizontal clock signals HCK1 and HCK2) is supplied to the horizontal drive circuit 6, and the video signal Vsi is supplied to the pixels 4 of one selected row.
Write one line of g. Further, the thinning mask signal ENB is used as the third timing signal for the vertical drive circuit 5.
It is used for thinning drive. As described above, the thinning sequencer 3a supplies the timing generator 3 with the thinning sequence signal that specifies the position of the line thinned for each field. The timing generator 3 responds to the VST and H according to the thinning sequence signal.
The application timing of each timing signal such as ST and ENB to the display panel 1 is adjusted. The display panel is also supplied with the reference voltage VCOM applied to the counter electrode.

FIG. 2 is a schematic view showing an example of the thinning operation of the display device according to the present invention. In this example, the positions of the thinned lines in the first field and the second field are alternately changed. Specifically, in the first field (odd field), the second line, the eighth line, the 14th line, ... Are thinned out. As a result, the line is thinned out at a rate of one in six. In the second field (even field), the fifth line, the eleventh line, ... Are thinned out.

FIG. 3 is a schematic view showing another example of the thinning operation. In this example, the positions of the lines to be thinned are cyclically changed by shifting three or more fields as a cycle. Specifically, the positions of lines to be thinned out are cyclically changed by shifting six fields as one cycle, and thinning is performed at a ratio of one to six lines. The first field, the seventh line, the thirteenth line, ... Are thinned out in the first field, the fourth line, the tenth line, ... Are thinned out in the second field, and the second field is two. The 8th line, the 8th line, the 14th line, ... are thinned out, the 5th line, the 11th line, ... are thinned out in the fourth field, and the 3rd line, 9th in the 5th field. The second line, ... is thinned out,
In the sixth field, the sixth line, the twelfth line, ... Are thinned out. All of these decimation sequences are designated by the decimation sequence signal output from the decimation sequencer 3a.

FIG. 4 is a block diagram showing a concrete configuration example of the display panel shown in FIG. As described above, the display panel 1 is provided with the predetermined screen 11 and the pixels 4 are arranged in an innumerable matrix. In this example, for simplicity, only one pixel 4 is shown. The pixel 4 is composed of a fine liquid crystal cell LC. Further, the row-shaped gate lines X and the column-shaped signal lines Y are arranged in an intersecting manner. Individual pixels 4 are arranged at the intersections of the two. A thin film transistor Tr is also integrally formed as an element for switching and driving this. The gate electrode of the thin film transistor Tr is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to the pixel electrode located at one end of the corresponding liquid crystal cell LC. The other end of the liquid crystal cell LC is connected to the counter electrode, and the desired reference voltage VCO
M is applied. Each gate line X is connected to the vertical drive circuit 5. On the other hand, each signal line Y has a horizontal switch H
It is connected to the video line 7 via SW and receives the supply of the video signal Vsig. Each horizontal switch HSW is opened / closed by the horizontal drive circuit 6.

The vertical drive circuit 5 operates based on VST, VCK1 and VCK2 input through the level conversion circuit 8. That is, the vertical drive circuit 5 sequentially transfers the vertical start signal VST according to the vertical clock signals VCK1 and VCK2 having opposite phases, and gate pulses φ ₁ , φ ₂ ,
, Φ _N are generated and output to each gate line X. In response to the gate pulse φ, the thin film transistor Tr is opened / closed to sequentially select the pixels 4 for one row.

On the other hand, the horizontal drive circuit 6 similarly operates according to HST, HCK1 and HCK2 input via the level conversion circuit 8. That is, the horizontal drive circuit 6 sequentially transfers the horizontal start signal HST according to the horizontal clock signals HCK1 and HCK2 having opposite phases, and outputs a sampling pulse. In response to this sampling pulse, the horizontal switch HS
W is controlled to open and close, and the video signal Vsig supplied via the video line 7 is sampled to each signal line Y. The sampled video signal Vsig is written in the liquid crystal pixel 4 via the thin film transistor Tr in the conductive state. That is, the horizontal drive circuit 6 sequentially writes one horizontal period of the video signal Vsig to the selected one row of pixels 4. Further, the display panel 1 has a vertical drive circuit 5
The gate circuit 9 is provided between the gate line X and the gate line X.
The gate circuit 9 includes a 2-input 1-output AND gate element 10 provided for each stage of the gate line X. The output terminal of each AND gate element 10 is connected to the corresponding gate line X. Further, one input terminal of the AND gate element 10 is connected to the corresponding stage of the vertical drive circuit 5. The other input terminal of the AND gate element 10 receives the mask signal ENB via the level conversion circuit 8.

FIG. 5 shows a specific configuration example of the vertical drive circuit 5 shown in FIG. As shown in the figure, the vertical drive circuit 5 comprises a multi-stage connection of D-type flip-flops (DFF). In the figure, only DFFs corresponding to the A-th and A + 1-th stages are shown for easy understanding. As described above, the vertical drive circuit 5 transfers the vertical start signal for each stage according to the vertical clock signals VCK1 and VCK2, and outputs the gate pulse. In this example, the vertical drive circuit 5 and the gate line X
The gate circuit 9 is inserted between and. As described above, the gate circuit 9 is composed of the AND gate element 10 provided corresponding to each stage. A pulse is input from the corresponding DFF to one input terminal of each AND gate element 10, and the mask signal ENB is supplied to the other input terminal. The output terminal of the AND gate element 10 is connected to the corresponding gate line X.

Next, the operation of the configuration shown in FIG. 5 will be described with reference to FIG. When the vertical start signal is transferred to the AFF DFF, VCK1 and VCK2 are temporarily stopped and a pulse DA having a width of two horizontal periods (2H) is output from the AFF DFF. In synchronization with this, the low active mask signal ENB is input to the AND gate element 10.
As a result, the potential of the gate line X corresponding to the A-th stage becomes the ground level. By this operation, the vertical scanning is temporarily stopped only for the 1H period. This is the thinning period.

FIG. 7 is a timing chart showing waveforms of gate pulses sequentially output from the vertical drive circuit 5. As described above, after the gate pulse φ _A is output from the A-th stage, vertical scanning is stopped for 1H period and thinning is performed. During this period, the video signal is idle transferred and is not written in the pixel. After the thinning period has elapsed, the gate pulse φ _{A + 1 of the} next stage will be output. In this way, the video signals can be thinned by temporarily stopping the vertical scanning at a predetermined ratio.

Finally, FIG. 8 is a timing chart showing the video signal writing operation. First, in order to facilitate understanding of the present invention, a write operation in the case of the NTSC standard will be described. In this case, line thinning is not performed and normal line sequential writing is executed. After a predetermined overscanning period has elapsed, the vertical start signal VST is input from the timing generator to the vertical drive circuit. The vertical start signal VST is the vertical clock signal VCK1.
In synchronism with the above, the signals are sequentially transferred every 1H and the above-mentioned gate pulse is output. In synchronization with this, by inputting the horizontal start signal HST from the timing generator to the horizontal drive circuit every 1H, it is possible to sequentially write one line of the video signal to the pixels of one row.

On the other hand, when a video signal conforming to the PAL standard is input, thinning driving is performed according to the present invention. In the illustrated example, the fourth line is designated to be thinned out. After a predetermined overscanning period has elapsed, the vertical start signal VST is input from the timing generator to the vertical drive circuit. This vertical start signal V
ST is sequentially transferred every 1H in synchronization with the vertical clock signal VCK1, and a gate pulse is output. In synchronization with this, the horizontal start signal HST is input to the horizontal drive circuit from the timing generator every 1H, so that the first to third lines of the video signal are sequentially written to the pixels in the first to third rows. After that, VCK1 is temporarily stopped at the timing when the fourth line is output. In response to this, the mask signal ENB goes low for 1H. The vertical scanning is temporarily stopped by the above timing control. During this time, the fourth line is idle-transferred. After this, the normal operation is restored, and the fifth, sixth, seventh and eighth
The first line is sequentially written in the corresponding row of pixels.
In addition, the inversion signal FRP
Are synchronized. As a result, 1H inversion driving can be accurately performed even after thinning.

[0022]

As described above, according to the present invention, in a display panel having a fixed number of display lines such as an active matrix type liquid crystal display panel, for example, a PAL system video signal is used as an NTSC system display panel. When thinning lines at a constant rate, such as when displaying, it is possible to reduce the phenomenon that images appear discontinuous by thinning out different lines for each field and improve the display image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a display device according to the present invention.

FIG. 2 is a schematic diagram for explaining the operation of the display device according to the present invention.

FIG. 3 is a schematic diagram for explaining the operation of the display device according to the present invention.

FIG. 4 is a block diagram showing an example of a display panel incorporated in the display device shown in FIG.

FIG. 5 is a circuit diagram for explaining a thinning operation.

FIG. 6 is a waveform diagram for explaining a thinning operation.

FIG. 7 is a timing chart for explaining the thinning-out operation.

FIG. 8 is a timing chart for explaining the operation of the display device according to the present invention.

[Explanation of symbols]

 1 Display Panel 2 Decoder / Driver 3 Timing Generator 3a Decimation Sequencer 4 Pixel 5 Vertical Drive Circuit 6 Horizontal Drive Circuit

Claims (5)

[Claims] 1. A display device comprising a display panel, a signal source for supplying a video signal to the display panel, and timing means for controlling driving of the display panel, wherein the display panel has a predetermined number per field. A plurality of pixels arranged in a matrix according to the standard of a predetermined video signal including lines, and a vertical drive circuit that sequentially selects pixels for one row,
A horizontal drive circuit for writing one line of a video signal to pixels of a selected one row, and the signal source outputs a specific video signal having a larger number of lines per field than the default video signal. The timing means controls timing of sequential selection by the vertical drive circuit to thin out excess lines included in a specific video signal input to the display panel at a predetermined ratio, and each field. A display device characterized in that the position of the thinned line is changed every time. 2. The display panel has a plurality of pixels arranged in a matrix according to the NTSC standard of a predetermined video signal composed of 525 lines, and the signal source is according to the PAL standard.
A specific video signal consisting of 25 lines is input to the display panel, and the timing means is one in six or one in seven.
The display device according to claim 1, wherein the excess line is thinned while changing the position at the rate of the book. 3. The display device according to claim 1, wherein the timing means alternately changes the positions of the lines thinned out in the first field and the second field. 4. The display device according to claim 1, wherein the timing means cyclically shifts and changes the positions of thinned lines in a cycle of three or more fields. 5. The display panel includes a pixel including a pixel electrode, a counter electrode facing the pixel electrode via a gap, a liquid crystal held in the gap, and a switching element for driving the pixel electrode. The display device according to claim 1, wherein the display device is a plurality of active matrix liquid crystal display panels.