JP3384159B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. Specifically, for example, for an active matrix type liquid crystal display device having a screen conforming to a normal standard of an angle of view (aspect ratio) of 4: 3, for example, an image conforming to a wide standard of an angle of view (aspect ratio) of 16: 9 The present invention relates to a technology for displaying an image by inputting a signal. More specifically, the present invention relates to a structure for suppressing a DC offset applied to a liquid crystal when an aspect ratio conversion display is performed. 2. Description of the Related Art Active matrix liquid crystal display devices have recently been applied to a wide range of applications, and are used, for example, in viewfinders of video cameras. In recent video cameras, normal standards (eg, NTSC standard,
In some cases, an imaging angle of view according to the PAL standard or the like and an imaging angle of view according to the wide standard (eg, the HDTV standard) can be designated. On the other hand, as a view finder, an active matrix type liquid crystal display device having an angle of view according to a normal standard is generally used. When an image picked up at an angle of view of a wide standard is displayed as it is on an active matrix type liquid crystal display device having an angle of view of a normal standard, the horizontal size of the screen is relatively compressed as compared with the vertical size. Deforms as if stretched vertically. Even if it is a viewfinder of a video camera, it is preferable to display the captured wide screen as it is. However, since an active matrix type liquid crystal display device used for a monitor generally has an angle of view of a normal standard, it cannot be projected without deformation of a screen. Therefore, a technique has recently been developed in which a wide standard screen is faithfully displayed on a normal standard liquid crystal display device by performing an aspect ratio conversion. When displaying a wide-standard image on a normal-standard screen, it is necessary to compress the image in the vertical direction in order to perform aspect ratio conversion. For this reason, predetermined horizontal lines are sequentially thinned out from a video signal conforming to the wide standard. Further, when the thinning-out drive is performed, residual portions are formed above and below the normal standard screen. In order to make the whole screen easy to see, it is preferable to display a black level background in the remaining portion. An active matrix type liquid crystal display device of the normal standard has 225 horizontal lines in a half line configuration, for example.
On the other hand, when displaying an image of a wide standard, it is necessary to compress the image so that the number of horizontal lines becomes 169 according to the aspect ratio. When writing a video signal to 169 horizontal lines, it is performed at a timing of 225 lines, so that the time left for writing a black signal in the remaining portion is relatively short.
During this short time, black signals must be written to 28 × 2 = 56 horizontal lines at the top and bottom. For example, in the case of the TNSC standard, 262.5 per field
In the half-line configuration, 225 horizontal lines are allocated to the scanning lines, so that a time corresponding to 37.5 horizontal scanning lines is provided as an overscan period. When a black signal is written using this overscan period, the black signal must be written to 56 horizontal lines at the top and bottom during a time corresponding to 37.5 horizontal scanning lines. I can't afford the time. For this reason, when displaying a wide-standard image on a normal-standard screen, control is performed such that a black signal is written at a high speed to a remaining portion generated in the vertical and vertical directions. When a fixed pattern is compressed and displayed by thinning-out driving in the vertical direction, an odd field (ODD FIELD) becomes a black signal in a certain line, and an even field (EVEN FIELD) becomes a white signal in a certain line. , Video signals at different levels may be written. If video signals of different levels are continuously written to a specific line, DC offset occurs and dielectric polarization or the like occurs in the liquid crystal cell, so that an image defect called "burn-in" occurs. In particular, in the aspect ratio conversion display, since the thinning rate becomes larger than usual, this burn-in is remarkable when a fixed pattern or the like is displayed. Also, for the remaining portions at the top and bottom of the screen, the black signal
Since writing is performed by high-speed scanning in the H cycle, there is a problem that burn-in is very conspicuous when there is a fluctuation in signal level or the like. [0006] To solve the above-mentioned problems of the prior art, the following measures have been taken. That is, the liquid crystal display device according to the present invention includes a screen section including liquid crystal pixels arranged in a matrix, a vertical scanning circuit for sequentially selecting one row of liquid crystal pixels, and a signal line for the selected one row of liquid crystal pixels.
A horizontal scanning circuit for writing one horizontal period of the video signal. Further, an AC conversion circuit is provided which supplies the horizontal scanning circuit with a video signal obtained by converting the original video signal into a polarity by performing a polarity inversion process in advance every horizontal period. As a characteristic feature, a phase switching circuit for controlling the AC conversion circuit and periodically switching the phase of the AC video signal by 180 ° is provided. Further, it includes a thinning circuit for timing-controlling the sequential selection of the vertical scanning circuit and thinning out a predetermined horizontal period from the AC-converted video signal. The thinning circuit,
For example, by subtracting a predetermined number of horizontal periods from a wide-standard video signal, a wide display compressed in the vertical direction with respect to a screen part conforming to the normal standard is enabled. in addition,
This liquid crystal display device includes a high-speed circuit, and controls a horizontal scanning circuit and a vertical scanning circuit to output a black signal to a remaining portion which is left and below the screen in a vertical direction when a wide display is performed. Write faster than signal . The speed-up circuit,
At the first stage of the remaining part, black signals are sampled on all signal lines.
After that, multiple rows of liquid crystal pixels at high speed
The black signal to be written into the first stage of the remaining portion has a higher writing voltage than the black signal included in the video signal. According to the present invention, periodically at a fixed cycle,
By switching the phase of the AC video signal by 180 °,
The polarity is periodically inverted to neutralize the DC offset. As a result, burn-in, which has conventionally been a problem, can be suppressed. Such a configuration is particularly effective when thinning out a predetermined horizontal period from the AC video signal. Further, when wide display is performed using thinning-out driving, it is also effective when writing a black signal at a higher speed than a video signal in the remaining portion left and right in the vertical direction of the screen portion. Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a basic configuration of a liquid crystal display device according to the present invention. 1, the present active matrix type liquid crystal display device includes a liquid crystal panel 1, a decoder / driver 2, and a timing generator 3. The liquid crystal panel 1 is provided with a screen unit 11 according to a normal standard (angle of view 4: 3 in this example). The screen section 11 has an infinite number of liquid crystal pixels 12 arranged in rows and columns. The liquid crystal panel 1 has a wide standard (in this example, an angle of view 16:
When the video signal Vsig of 9) is input, it is possible to perform a horizontally wide display on the screen unit 11. In this example, the liquid crystal panel 1 is a full-color type, and receives a video signal Vsig divided for each of the three primary colors RGB. The liquid crystal panel 1 has a built-in vertical scanning circuit 14, and sequentially selects the liquid crystal pixels 12 for one row. In addition, a horizontal scanning circuit 15 is built in, and one horizontal period of the video signal Vsig of the wide standard is written in the selected one row of the liquid crystal pixels 12.
Further, a thinning circuit is incorporated in the vertical scanning circuit 14, and the above-described sequential selection is timing-controlled, a predetermined number of horizontal periods are thinned out from the wide-standard video signal Vsig, and a wide display compressed in the vertical direction of the screen unit 11 is displayed. Do. The decoder / driver 2 is divided into a decoder section and a driver section. The decoder unit decodes the video signal VIDEO input from the outside and extracts a luminance signal and a chroma signal. Further, the synchronization signal SYNC separated from the video signal VIDEO is transferred to the timing generator 3 side. The driver unit includes an AC conversion circuit, and inverts the polarity of the original video signal in advance every horizontal period in accordance with the inverted signal FRP input from the timing generator 3, and supplies the AC video signal Vsig to the liquid crystal panel 1 side. I do. The timing generator 3 outputs a synchronization signal SY
Various timing signals are generated based on the NC and supplied to the liquid crystal panel 1 to control the timing. That is, the vertical start signal VST and the vertical clock signals VCK1 and VCK2 having phases opposite to each other are supplied to the vertical scanning circuit 14 to sequentially select one row of liquid crystal pixels. Further, the horizontal start signal HST and the horizontal clock signals HCK1 and H
CK2 is supplied to the horizontal scanning circuit 15, and the wide-range video signal Vsig is supplied to the selected one row of the liquid crystal pixels 12.
Is written for one horizontal period. Further, the decimation signal E
NB is supplied to the vertical scanning circuit 14, and the sequential selection is timing-controlled so that a predetermined number of horizontal periods are subtracted from the wide-standard video signal Vsig to perform a wide display compressed in the vertical direction of the screen unit 11. In addition, the timing generator 3 includes a speed-up circuit, and controls the horizontal scanning circuit 15 and / or the vertical scanning circuit 14 irregularly,
When a wide display is performed, a black signal is applied to a video signal Vsig with respect to a remaining portion (blank portion) left and right in the vertical direction of the screen section 11.
Make writing faster. Further, the timing generator 3 has a built-in phase switching circuit, and controls the AC conversion circuit on the decoder / driver 2 side to periodically switch the phase of the AC video signal Vsig by 180 °. More specifically, this phase switching circuit switches the phase of the inverted signal FRP by 180 ° every several tens or hundreds of fields. As described above, by switching the phase of the inverted signal FRP by 180 ° at a certain fixed cycle, it is possible to neutralize the DC offset generated in the liquid crystal panel 1. In this embodiment, the video signal Vsig is mixed with a black signal in advance and supplied to the liquid crystal panel 1. In order to control the synthesis of the video signal VIDEO and the black signal, the timing generator 3 outputs a side black signal SBLK. SBLK is created based on the synchronization signal SYNC,
For example, it is output according to the overscanning period within one vertical period. The analog switch 4 provided on the input side of the decoder / driver 2 opens and closes according to SBLK, and alternately switches between the video signal VIDEO and the black signal and inputs the video signal VIDEO and the black signal. The timing generator 3 has a control terminal, and a wide display (WIDE)
And normal display (NORMAL) can be switched. FIG. 2 is a block diagram showing a specific configuration example of the liquid crystal panel 1 shown in FIG. As described above, the liquid crystal panel 1 includes the screen section 11, and the liquid crystal pixels 12 are arranged in an infinite number of rows and columns. In this example, for simplicity, one pixel 1
Only 2 is shown. This pixel 12 has a fine liquid crystal cell L
C. Further, the row-shaped gate lines X and the column-shaped signal lines Y are arranged crossing each other. Individual pixels 12 are arranged at the intersection of the two. A thin-film transistor Tr for switchingly driving the thin-film transistor is also integrally formed. The gate electrode of the thin film transistor Tr is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to one end of the corresponding liquid crystal cell LC. The other end of the liquid crystal cell LC is connected to a counter electrode, and a desired counter voltage (reference voltage) VCOM is applied. Each gate line X is connected to the vertical scanning circuit 14. On the other hand, each signal line Y is connected to a horizontal switch HS.
It is connected to the video line 13 via W, and receives the supply of the AC video signal Vsig. Individual horizontal switch H
SW is controlled to open and close by the horizontal scanning circuit 15. The vertical scanning circuit 14 operates based on VST, VCK1 and VCK2 input via the level conversion circuit 16. That is, the vertical scanning circuit 14 sequentially transfers the vertical start signal VST in accordance with the vertical clock signals VCK1 and VCK2 having phases opposite to each other, and selects the selection pulses φ ₁ and φ for each stage.
_2, ..., and generates a phi _N outputs to each gate line X.
The thin film transistor Tr opens and closes in response to the selection pulse (gate pulse) φ, and the pixels 12 for one row are sequentially selected. On the other hand, the horizontal scanning circuit 15 also receives HST, HCK1, HCK input through the level conversion circuit 16 as well.
It operates according to 2. That is, the horizontal scanning circuit 15 sequentially transfers the horizontal start signal HST in accordance with the horizontal clock signals HCK1 and HCK2 having phases opposite to each other, and outputs a sampling pulse. The horizontal switch HSW is controlled to open and close according to the sampling pulse, and samples the AC video signal Vsig supplied via the video line 13 to each signal line Y. Sampled video signal Vsig
Is written to the liquid crystal pixel 12 via the thin film transistor Tr in the selective conduction state. That is, the horizontal scanning circuit 15 sequentially writes one horizontal period of the video signal Vsig to the selected one row of pixels 12. In the normal display, the polarity of the alternating video signal Vsig is inverted every horizontal period, and a voltage having an opposite polarity is written for each row. The liquid crystal panel 1 has a thinning circuit 17 between the vertical scanning circuit 14 and the screen section 11. In the present example, the thinning circuit 17 includes a two-input one-output AND gate element 18 provided for each stage of the gate line X. The output terminal of each AND gate element 18 is a corresponding gate line X
It is connected to the. One input terminal of the AND gate element 18 is connected to a corresponding stage of the vertical scanning circuit 14. The other input terminal of the AND gate element 18 receives the thinning signal ENB via the level conversion circuit 16. Next, the overall operation of the active matrix type liquid crystal display device shown in FIG. 1 will be described with reference to FIG. In this example, the video signal VIDEO input from the outside to the decoder / driver 2 complies with a wide standard such as HDTV, and includes video information with an angle of view of 16: 9. In contrast, the screen section 11 provided on the liquid crystal panel 1 has an angle of view of 4: 3. Therefore, if the video signal VIDEO is decoded and then input to the liquid crystal panel as it is, an image that is stretched in the vertical direction of the screen section 11 will be displayed. In view of this point, in the present example, a predetermined number of horizontal periods are thinned out from the wide-standard video signal Vsig by the above-described thinning circuit 17 to perform wide display compressed on the screen unit 11 in the vertical direction. That is, the liquid crystal display device according to the present invention has a vertical scanning thinning function, and compresses an image by 75% in the vertical direction by thinning out, for example, one out of four horizontal lines. In the case of the PAL standard, thinning is performed at a rate of one out of three. When the image is compressed in the vertical direction, the screen unit 1
Residual portions 19 are formed above and below 1. A black signal is written in this portion by vertical high-speed scanning. For example, the screen unit 11
Has a half line configuration of the NTSC standard, it includes 225 horizontal lines. If one out of four lines is thinned out, the remaining upper and lower portions 19 will include 56 horizontal lines. Since the video signal is written to the 169 horizontal lines constituting the image at the timing assigned to 225 horizontal lines, the remaining time is short. For example, in the case of the NTSC standard, 262.5 scanning lines are included per field, but 37.5 lines are excluded from an actual video signal writing time as an overscanning period. In the overscanning period corresponding to the 37.5 lines, writing to 56 horizontal lines must be performed. In view of this point, in this example, the black signal is written to the remaining portion 19 at a higher speed than the video signal. Next, a vertical thinning operation and a high-speed writing operation of a black signal will be described with reference to FIGS. FIG. 4 illustrates a specific configuration example of the vertical scanning circuit 14 illustrated in FIG. As shown, the vertical scanning circuit 1
4 is a multi-stage connection of D-type flip-flops (DFF). In the figure, only DFFs corresponding to the A-th and A + 1-th stages are shown for easy understanding. As described above, the vertical scanning circuit 14 transfers a vertical start signal for each stage according to the vertical clock signals VCK1 and VCK2, and outputs a selection pulse. In this example, a thinning circuit 17 is inserted between the vertical scanning circuit 14 and the screen section 11. As described above, the thinning circuit 17 includes the AND gate elements 18 provided corresponding to each stage. A pulse is inputted from a corresponding DFF to one input terminal of each AND gate element 18, and a thinning signal ENB is supplied to the other input terminal. The output terminal of the AND gate element 18 is connected to the corresponding gate line X. Next, the operation of the circuit configuration shown in FIG. 4 will be described with reference to FIG. The vertical start signal is D
When transferred to the FF, VCK1 and VCK2 are temporarily stopped, and a pulse DA having a width of 2H is supplied to the A-stage DF.
Output from F. In synchronization with this, the low active thinning signal ENB is input to the AND gate element 18. As a result, the potential of the gate line X corresponding to the A-th stage becomes the ground level. With this operation, the vertical scanning is temporarily stopped for the 1H period. This is the thinning period. FIG. 6 is a timing chart showing the waveforms of the selection pulses sequentially output from the vertical scanning circuit 14. As mentioned above, only the vertical scanning 1H period after the selection pulse phi _A from A stage is output is performed thinning stops. During this time, the video signal is transferred idle and is not written on the screen. After the lapse of the thinning-out period, the next-stage selection pulse φ _{A + 1} is output. As described above, by temporarily stopping the vertical scanning at a rate of one out of four, the thinning of the video signal can be performed. FIG. 7 is a timing chart showing a video signal writing operation. First, in order to facilitate understanding of the present invention, a writing operation in normal display with a view angle of 4: 3 will be described. After a lapse of a predetermined overscanning period, a vertical start signal VST is input from the timing generator to the vertical scanning circuit. The vertical start signal VST is sequentially transferred every 1H in synchronization with the vertical clock signal VCK (actually, VCK1 and VCK2 having phases opposite to each other), and the above-described selection pulse is output. By inputting the horizontal start signal HST from the timing generator to the horizontal scanning circuit every 1H in synchronization with this,
One horizontal period of a video signal can be sequentially written to one row of pixels. On the other hand, when performing the wide display of the angle of view 16: 9, first, the input timing of the vertical start signal VST moves to the top of the overscanning period. High-speed writing of a black signal is performed during this overscanning period. In this example, a one-step write / multi-step transfer (for example, three-step transfer) method is adopted. That is, in the first stage, the black signal is sampled on all the signal lines, and thereafter, the black signal is written on a plurality of horizontal lines at a high speed in multiple stages. For this reason, in this example, VCK is quadrupled and supplied to the liquid crystal panel.
Specifically, VCK is driven at normal speed in the first 1H to perform first-stage writing, and VCK is driven at 4 × speed in the next 1H to transfer a black signal sampled to a signal line in multiple stages. Therefore, one-stage writing / multi-stage transfer is performed once in 2H. In response, HST is output every 2H. Also, the FRP is inverted by 2H so as to convert the black signal into an alternating current. In the one-stage writing / multi-stage transfer system, the horizontal scanning circuit can be driven at normal speed, while only the vertical scanning circuit needs to be temporarily driven at high speed. Originally, only the vertical scanning circuit, which is slower than the horizontal scanning circuit, needs to be speeded up, so that the load on the circuit side can be reduced. As described above, in this example, by utilizing the fact that the capacitance of the signal line formed on the liquid crystal panel is much larger than the capacitance of the pixel, the black signal is once sampled and held in the signal line. Thereafter, while the sampling is stopped, only the vertical scanning circuit is driven at a high speed, and a black signal is written to pixels of several rows. At this time, the charge accumulated in the signal line decreases as the pixel at the subsequent stage decreases, and the writing potential decreases. To compensate for this, the voltage level of the black signal is set higher in advance. In this manner, after the black signal is written to a plurality of horizontal lines every 2H and the overscanning period elapses, the video signal writing period is started, and the above-described vertical thinning drive is performed. That is, VCK is temporarily stopped once every 4H. In response to this, the thinning signal ENB becomes low level by 1H, so that the vertical scanning is temporarily stopped. During this time, the video signal for 1H is idle-transferred. The inverted signal FRP is synchronized with the thinning timing. This enables accurate 1H inversion driving even after thinning. When a fixed pattern is displayed by thinning-out driving, as shown in FIG. 8A, in a certain line, an odd field (ODD FIELD) has a black level, and an even field (EVEN FIELD) has a white level. There are things. There is a concern that image signals at different levels may be written to the same line for each field, and a DC offset will occur if this is done. This causes burn-in. Thus, as shown in FIG. 8B, the phase of the AC video signal is switched by 180 ° by inverting the polarity of the FRP under a certain period. As a result, one phase component indicated by hatching and the other phase component indicated by solid white cancel each other, thereby neutralizing the DC offset. The inversion cycle of FRP can be freely changed by external setting.
Usually, the polarity inversion of FRP is performed once every several tens to several hundred fields. In the above description, the occurrence of the DC offset in the case of performing the thinning-out drive has been a problem.
Burn-in occurs even when no thinning drive is performed. This will be briefly described with reference to FIG. (A) shows the DC offset when black display is performed at normal speed drive, and (B) shows the DC offset that appears when black display is performed at high speed drive. Normally, the black level of the video signal written to the liquid crystal panel is ± 4.0 V. However, when wide display is performed, black signals are written in the remaining portions above and below the screen portion by the one-stage writing / multi-stage transfer method as described above. For this reason, a black signal of a level of ± 4.5 V or more is required. Generally, at least ± 4.0 V is required to obtain a substantially perfect black display. If it is less than this, it will be gray level. Therefore, in the upper and lower remaining portions performing the one-stage writing / multi-stage transfer method,
In order to secure the writing voltage of the final stage at ± 4.0 V, it is necessary to set the writing signal of the first stage at ± 4.5 V in advance. Actually, by performing the high-speed multi-stage transfer, the write voltage is sequentially reduced to 4.5 V, 4.3 V, 4.1 V, and 4.0 V. As described above, since a wide display requires a writing voltage of ± 4.5 V, when a DC offset occurs at the time of writing, burn-in is more likely than in a normal black display. Note that this DC offset occurs when the center potential of the video signal and the counter potential VCOM are shifted as shown in the figure. As shown in (A) and (B), even when the DC offset is almost the same between the normal driving and the high speed driving, the burn-in is more likely to occur in the high speed driving because of the large writing voltage.
In addition, in the case of burn-in, high-speed driving is performed at, for example, a 2H cycle, so that it is more noticeable. In addition, burn-in due to variations in the writing potential during high-speed transfer may be considered. This is largely affected by variations in the write capacity of the signal line. As will be understood from the above description, burn-in occurs even when the thinning drive is not performed. However,
Black display during high-speed driving, which requires a write signal of 4.5 V or more, is more likely to burn in than black display at normal speed. When thinning is performed, a step shift occurs as described above, so that the image is further burned. That is, the DC offset due to the step shift increases. Further, in the compressed display in the present embodiment, since the thinning rate is large, burn-in becomes conspicuous. As described above, according to the present invention, the DC offset is neutralized by periodically switching the phase of the AC-converted video signal by 180 °. There is an effect that the image sticking which has been described can be suppressed. This effect is particularly remarkable when the display operation is performed by thinning the horizontal period from the video signal as needed. Also, when writing a black signal at a higher speed than the video signal to the remaining portion left and right in the vertical direction of the screen portion when wide display is performed by thinning drive, it is possible to set the voltage level of the black signal higher in advance. book
It is possible to compensate for a decrease in the writing potential .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a basic configuration of a liquid crystal display device according to the present invention. FIG. 2 is a block diagram showing an example of a liquid crystal panel incorporated in the liquid crystal display device shown in FIG. FIG. 3 is a schematic diagram for explaining the operation of the liquid crystal display device shown in FIG. 1; FIG. 4 is a circuit diagram for explaining a thinning operation. FIG. 5 is a waveform chart for explaining a thinning operation. FIG. 6 is a timing chart for explaining a thinning operation. FIG. 7 is a timing chart for explaining a high-speed writing operation of a black signal. FIG. 8 is a timing chart for explaining the operation of the AC conversion circuit and the phase switching circuit included in the liquid crystal display device according to the present invention. FIG. 9 is a waveform chart for explaining the operation of the AC conversion circuit. [Description of Signs] 1 Liquid crystal panel 2 Decoder / Driver 3 Timing generator 4 Analog switch 11 Screen section 12 Liquid crystal pixel 13 Video line 14 Vertical scanning circuit 15 Horizontal scanning circuit 16 Level conversion circuit 17 Thinning circuit 18 AND gate element

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 550

Claims (1)

(57) and Patent Claims 1] a liquid crystal pixels arranged in rows and columns screen section, a vertical scanning circuit for sequentially selecting the liquid crystal pixels of one row, the signal to the liquid crystal pixels of one row which is selected A horizontal scanning circuit for writing one horizontal period of a video signal via a line; an AC conversion circuit for supplying an AC video signal obtained by previously performing polarity inversion processing on the original video signal every horizontal period to the horizontal scanning circuit; A phase switching circuit that controls the AC conversion circuit to periodically switch the phase of the AC-converted video signal by 180 °; and a timing control of sequential selection of the vertical scanning circuit, and a predetermined timing from the AC-converted video signal. A thinning circuit for thinning out a horizontal period of the video signal, wherein the thinning circuit is vertical to a screen part according to a normal standard by thinning out a predetermined number of horizontal periods from a wide standard video signal. The horizontal scanning circuit and the vertical scanning circuit control the horizontal signal and the vertical scanning circuit for the remaining portion that is left and below the screen in the vertical direction when wide display is performed. A speed-up circuit for writing at a higher speed than the signal, wherein the speed-up circuit includes all signal lines at the first stage of the remaining portion.
The black signal is sampled in
A liquid crystal display device wherein a black signal is written to liquid crystal pixels of a plurality of rows, and a writing voltage of the black signal to be written to the first stage of the remaining portion is higher than a black signal included in a video signal.