JPH08179733A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To suppress the seizure failure of a liquid crystal display device resulted from DC offset. CONSTITUTION: This liquid crystal display device has a liquid crystal panel 1, a decoder/driver 2, and a timing generator 3. The liquid crystal panel 1 has a screen part 11 consisting of liquid crystal picture elements 12 arranged in matrix, a vertical scanning circuit 14 for successively selecting the liquid crystal picture elements for one line, and a horizontal scanning circuit 15 for writing one horizontal period of a video signal Vsig to the selected liquid crystal picture elements 12 for one line. The decoder/driver 2 is provided with an AC converting circuit to supply the video signal Vsig in which the original video signal is preliminarily subjected to polarity reversal processing every horizontal period and AC-converted to a horizontal scanning circuit 15. The timing generator 2 is provided with a phase switching circuit to control the AC converting circuit on the decoder/driver 2 side to periodically switch the phase of the AC-converted video signal Vsig. Thus, DC offset can be removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. Specifically, for example, for an active matrix type liquid crystal display device having a screen conforming to the normal standard with an angle of view (aspect ratio) of 4: 3, for example, an image conforming to a wide standard with an angle of view (aspect ratio) of 16: 9 The present invention relates to a technique for inputting a signal and displaying an image. More specifically, it relates to a structure for suppressing a DC offset applied to a liquid crystal when aspect ratio conversion display is performed.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has been widely applied in recent years and is used, for example, in a viewfinder of a video camera. In recent video cameras, normal standard (for example, NTSC standard,
There is a device in which an imaging angle of view according to the PAL standard or the like and an imaging angle of view according to the wide standard (for example, the HDTV standard) can be designated. On the other hand, as the viewfinder, an active matrix type liquid crystal display device having an angle of view according to the normal standard is generally used.

When an image captured with a wide standard angle of view is displayed as it is on an active matrix type liquid crystal display device having a normal standard angle of view, the horizontal dimension of the screen is relatively compressed as compared with the vertical dimension, so that the screen becomes smaller. It deforms as if it was stretched vertically. Even in the viewfinder of a video camera, for example, it is preferable to display the captured wide screen as it is. However, since the active matrix type liquid crystal display device used for the monitor generally has a normal standard angle of view, it cannot be displayed without the screen being deformed.

Therefore, recently, a technique has been developed in which aspect ratio conversion is performed to faithfully display a wide standard screen on a normal standard liquid crystal display device. When displaying a wide standard image on a normal standard screen, it is necessary to compress the image in the vertical direction in order to perform the aspect ratio conversion. Therefore, predetermined horizontal lines are sequentially thinned out from the video signal according to the wide standard. Further, when the thinning driving is performed, a residual portion is generated above and below the screen of the normal standard. In order to make the entire screen easier to see, it is preferable to display a black level background in this remaining portion. A normal standard active matrix type liquid crystal display device has 225 horizontal lines in the case of a half line configuration, for example.
On the other hand, when displaying a wide-standard image, it is necessary to compress the horizontal lines to 169 according to the aspect ratio. When a video signal is written to 169 horizontal lines, it is performed at a timing of 225 lines, and therefore the time left for writing a black signal in the remaining portion is relatively short.
During this short time, black signals have to be written in the upper and lower horizontal lines of 28 × 2 = 56. For example, in the case of the TNSC standard, 262.5 per field
In the half-line configuration, 225 horizontal lines are assigned to one scanning line, so that a time corresponding to 37.5 horizontal scanning lines is provided as an overscan period. When a black signal is written using this overscan period, it is necessary to write a black signal to 56 horizontal lines in the vertical direction during the time corresponding to 37.5 horizontal scanning lines. I have no time to spare. For this reason, when a wide standard image is displayed on a normal standard screen, a black signal is controlled to be written at a high speed in the remaining portion generated in the vertical and vertical directions.

[0005]

By the way, when a fixed pattern is compressed and displayed by vertical thinning driving, an odd field (ODD FIELD) becomes a black signal and an even field (EVEN FIELD) becomes a white signal in a certain line. Therefore, different levels of video signals may be written. When video signals of different levels are continuously written in a specific line, DC offset occurs and dielectric polarization or the like occurs in the liquid crystal cell, so that an image defect called "burn-in" occurs. In particular, in the case of the aspect ratio conversion display, the thinning-out rate becomes larger than usual, so that the image sticking is remarkable when a fixed pattern or the like is displayed. In addition, black signals are also applied to the remaining portions at the top and bottom of the screen, for example
Since writing is performed by high-speed scanning of H period, there is a problem that burn-in is very noticeable when there is a level change of the signal.

[0006]

Means for Solving the Problems In order to solve the above-mentioned problems of the conventional technique, the following means were taken. That is, the liquid crystal display device according to the present invention includes a screen portion including liquid crystal pixels arranged in a matrix, a vertical scanning circuit that sequentially selects liquid crystal pixels for one row, and a video signal for the selected liquid crystal pixels for one row. And a horizontal scanning circuit for writing one horizontal period.
Further, it is provided with an AC conversion circuit for supplying the horizontal scanning circuit with a video signal in which the original video signal is subjected to polarity inversion processing every horizontal period in advance and converted into an AC signal. As a characteristic matter, the phase of the AC-converted video signal is controlled to 180 by controlling the AC conversion circuit.
It has a phase switching circuit for switching. Further, it includes a thinning circuit for timing-controlling the sequential selection of the vertical scanning circuit and thinning a predetermined horizontal period from the AC-converted video signal. The thinning circuit enables a wide display compressed in the vertical direction with respect to a screen portion according to the normal standard by thinning out a predetermined number of horizontal periods from a wide standard video signal. In addition, the present liquid crystal display device includes a speed-up circuit, and controls the horizontal scanning circuit and the vertical scanning circuit for the remaining portion that is left above and below the screen portion in the vertical direction when performing wide display. Write the signal faster than the video signal.

[0007]

According to the present invention, at regular intervals, periodically,
By switching the phase of the AC video signal by 180 °,
The polarity is periodically reversed to neutralize DC offset. As a result, seizure, which has been a problem in the past, can be suppressed. Such a configuration is particularly effective when thinning out a predetermined horizontal period from the alternating video signal. Further, when wide display is performed by using the thinning drive, it is also effective when writing a black signal into the remaining portion above and below the screen portion in the vertical direction at a higher speed than the video signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of a liquid crystal display device according to the present invention. As shown in the figure, the active matrix liquid crystal display device includes a liquid crystal panel 1, a decoder / driver 2, and a timing generator 3. The liquid crystal panel 1 includes a screen section 11 conforming to the normal standard (angle of view 4: 3 in this example). Innumerable liquid crystal pixels 12 are arranged in a matrix on the screen portion 11. The liquid crystal panel 1 has a wide standard (angle of view 16:
When the video signal Vsig of 9) is input, it is possible to perform a horizontally wide display on the screen unit 11. In this example, the liquid crystal panel 1 is a full-color type, and receives the video signal Vsig divided for each of the three primary colors of RGB. The liquid crystal panel 1 has a built-in vertical scanning circuit 14 and sequentially selects one row of liquid crystal pixels 12. Further, the horizontal scanning circuit 15 is built in, and one horizontal period of the video signal Vsig of the wide standard is written to the selected liquid crystal pixels 12 of one row.
Further, a thinning circuit is incorporated in the vertical scanning circuit 14, and a predetermined number of horizontal periods are thinned out from the wide standard video signal Vsig by timing control of the above-described sequential selection to display a wide display compressed in the vertical direction of the screen unit 11. To do.

The decoder / driver 2 is divided into a decoder section and a driver section. The decoder unit decodes the video signal VIDEO input from the outside and extracts the luminance signal and the chroma signal. Further, the sync signal SYNC separated from the video signal VIDEO is transferred to the timing generator 3 side. The driver unit includes an AC conversion circuit, and performs polarity inversion processing on the original video signal in advance every horizontal period in accordance with the inversion signal FRP input from the timing generator 3, and supplies the AC conversion video signal Vsig to the liquid crystal panel 1 side. To do.

The timing generator 3 has a synchronizing signal SY.
Various timing signals are created based on NC and supplied to the liquid crystal panel 1 to control the timing. That is, the vertical start signal VST and the vertical clock signals VCK1 and VCK2 having opposite phases are supplied to the vertical scanning circuit 14 to sequentially select the liquid crystal pixels for one row. Further, the horizontal start signal HST and the horizontal clock signals HCK1 and HCK having opposite phases to each other.
CK2 is supplied to the horizontal scanning circuit 15 so that a wide-standard video signal Vsig is supplied to the selected liquid crystal pixels 12 for one row.
Write for one horizontal period. Further, the thinning signal E
The NB is supplied to the vertical scanning circuit 14, the sequential selection is timing-controlled, and a predetermined number of horizontal periods are thinned from the wide-standard video signal Vsig to perform a wide display compressed in the vertical direction of the screen unit 11. In addition, the timing generator 3 includes a speed-up circuit, and controls the horizontal scanning circuit 15 and / or the vertical scanning circuit 14 irregularly,
When a wide display is performed, a black signal is output to the video signal Vsig with respect to the remaining portion (blank portion) left and right in the vertical direction of the screen portion 11.
Write faster. Further, the timing generator 3 has a built-in phase switching circuit and controls the alternating circuit on the decoder / driver 2 side to periodically switch the phase of the alternating video signal Vsig by 180 °. Specifically, this phase switching circuit switches the phase of the inverted signal FRP by 180 ° every tens or hundreds of fields. In this way, by switching the phase of the inversion signal FRP by 180 ° in a certain fixed cycle, it becomes possible to neutralize the DC offset generated in the liquid crystal panel 1.

In this example, a black signal is mixed in advance with the video signal Vsig and is supplied to the liquid crystal panel 1. The timing generator 3 outputs the side black signal SBLK in order to control the synthesis of the video signal VIDEO and the black signal. SBLK is created based on the synchronization signal SYNC,
For example, it is output according to the overscanning period within one horizontal period. The analog switch 4 provided on the input side of the decoder / driver 2 opens and closes according to SBLK, and alternately switches the video signal VIDEO and the black signal and inputs them to the decoder / driver 2. The timing generator 3 has a control terminal, and has a wide display (WIDE).
And normal display (NORMAL) can be switched.

FIG. 2 is a block diagram showing a specific configuration example of the liquid crystal panel 1 shown in FIG. As described above, the liquid crystal panel 1 includes the screen portion 11, and the liquid crystal pixels 12 are arranged in an innumerable matrix. In this example, one pixel 1 is used for simplicity.
Only 2 is shown. This pixel 12 is a fine liquid crystal cell L
It consists of C. Further, the row-shaped gate lines X and the column-shaped signal lines Y are arranged in an intersecting manner. Individual pixels 12 are arranged at the intersections of the two. A thin film transistor Tr for switching and driving this is also formed integrally. The gate electrode of the thin film transistor Tr is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to one end of the corresponding liquid crystal cell LC. The other end of the liquid crystal cell LC is connected to the counter electrode, and a desired counter voltage (reference voltage) VCOM is applied. Each gate line X is connected to the vertical scanning circuit 14. On the other hand, each signal line Y has a horizontal switch HS.
It is connected to the video line 13 via W and receives the supply of the alternating video signal Vsig. Individual horizontal switch H
Opening and closing of the SW is controlled by the horizontal scanning circuit 15.

The vertical scanning circuit 14 operates based on VST, VCK1 and VCK2 input through the level conversion circuit 16. That is, the vertical scanning circuit 14 sequentially transfers the vertical start signal VST in accordance with the vertical clock signals VCK1 and VCK2 having opposite phases, and selects pulses φ ₁ and φ for each stage.
₂ , ..., φ _N are generated and output to each gate line X.
In response to the selection pulse (gate pulse) φ, the thin film transistor Tr is opened / closed, and the pixels 12 for one row are sequentially selected.

On the other hand, the horizontal scanning circuit 15 has HST, HCK1 and HCK input via the level conversion circuit 16 as well.
It operates according to 2. That is, the horizontal scanning circuit 15 sequentially transfers the horizontal start signal HST according to the horizontal clock signals HCK1 and HCK2 having opposite phases and outputs sampling pulses. The horizontal switch HSW is controlled to open and close according to the sampling pulse, and the alternating video signal Vsig supplied via the video line 13 is sampled on each signal line Y. Sampled video signal Vsig
Is written in the liquid crystal pixel 12 via the thin film transistor Tr in the selective conduction state. That is, the horizontal scanning circuit 15 sequentially writes one horizontal period of the video signal Vsig to the selected one row of pixels 12. In the normal display, the polarity of the alternating video signal Vsig is inverted every horizontal period, and the voltage of the opposite polarity is written in each row.

The liquid crystal panel 1 includes a thinning circuit 17 between the vertical scanning circuit 14 and the screen section 11. In this example, the thinning circuit 17 is composed of a two-input one-output AND gate element 18 provided for each stage of the gate line X. The output terminal of each AND gate element 18 has a corresponding gate line X.
It is connected to the. Further, one input terminal of the AND gate element 18 is connected to the corresponding stage of the vertical scanning circuit 14. The other input terminal of the AND gate element 18 receives the thinned-out signal ENB via the level conversion circuit 16.

Next, the overall operation of the active matrix type liquid crystal display device shown in FIG. 1 will be described with reference to FIG. In this example, the video signal VIDEO input from the outside to the decoder / driver 2 complies with a wide standard such as HDTV, and includes video information with a field angle of 16: 9. On the other hand, the screen portion 11 provided on the liquid crystal panel 1 has an angle of view of 4: 3. Therefore, if the video signal VIDEO is decoded and then input to the liquid crystal panel as it is, an image stretched in the vertical direction of the screen unit 11 is displayed. In view of this point, in the present example, the thinning circuit 17 described above thins a predetermined number of horizontal periods from the wide-standard video signal Vsig to perform wide display compressed in the vertical direction of the screen unit 11. That is, the liquid crystal display device according to the present invention has a vertical scanning thinning-out function. For example, by thinning out horizontal lines at a ratio of one in four, an image is compressed by 75% in the vertical direction. In the case of the PAL standard, one in three lines is thinned out.

When the image is compressed in the vertical direction, the screen section 1
A residual portion 19 is formed above and below 1. A black signal is written in this portion by high speed vertical scanning. For example, the screen section 11
In the case of the NTSC standard half line configuration, it includes 225 horizontal lines. If one is thinned out to four, the upper and lower residual portions 19 include 56 horizontal lines. Since the video signal is written to the 169 horizontal lines forming the image at the timing assigned to the 225 horizontal lines, the remaining time is short. For example, in the case of the NTSC standard, one field includes 262.5 scanning lines, but 37.5 lines are excluded from the actual video signal writing time as an overscanning period. Writing must be performed on 56 horizontal lines during an overscanning period corresponding to 37.5 lines. In view of this point, in this example, the black signal is written in the remaining portion 19 at a higher speed than the video signal.

Next, the vertical thinning operation and the black signal high-speed writing operation will be described with reference to FIGS. FIG. 4 shows a specific configuration example of the vertical scanning circuit 14 shown in FIG. As shown, the vertical scanning circuit 1
Reference numeral 4 is a multi-stage connection of D-type flip-flops (DFF). In the figure, only DFFs corresponding to the A-th and A + 1-th stages are shown for easy understanding. As described above, the vertical scanning circuit 14 transfers the vertical start signal for each stage according to the vertical clock signals VCK1 and VCK2 and outputs the selection pulse. In this example, a thinning circuit 17 is inserted between the vertical scanning circuit 14 and the screen section 11. As described above, the thinning circuit 17 includes the AND gate element 18 provided corresponding to each stage. A pulse is input from the corresponding DFF to one input terminal of each AND gate element 18, and the thinning-out signal ENB is supplied to the other input terminal. The output terminal of the AND gate element 18 is connected to the corresponding gate line X.

Next, the operation of the circuit configuration shown in FIG. 4 will be described with reference to FIG. The vertical start signal is D at the A stage
When transferred to the FF, VCK1 and VCK2 are temporarily stopped and the pulse DA having a width of 2H is supplied to the DF of the A stage.
Output from F. In synchronization with this, the low active thinning signal ENB is input to the AND gate element 18. As a result, the potential of the gate line X corresponding to the A-th stage becomes the ground level. By this operation, the vertical scanning is temporarily stopped only for the 1H period. This is the thinning period.

FIG. 6 is a timing chart showing the waveform of the selection pulse sequentially output from the vertical scanning circuit 14. As described above, vertical scanning is stopped and thinning is performed for a period of 1H after the selection pulse φ _A is output from the A-th stage. During this time, the video signal is idle transferred and is not written on the screen. After the thinning period elapses, the selection pulse φ _{A + 1 of the} next stage is output. Thus, by temporarily stopping the vertical scanning at a rate of one in four lines, the thinning of the video signal can be performed.

Next, FIG. 7 is a timing chart showing a video signal writing operation. First, in order to facilitate understanding of the present invention, a writing operation in a normal display with an angle of view of 4: 3 will be described. After the lapse of a predetermined overscanning period, the timing generator inputs the vertical start signal VST to the vertical scanning circuit. The vertical start signal VST is sequentially transferred every 1H in synchronization with the vertical clock signal VCK (actually VCK1 and VCK2 having opposite phases), and the above-described selection pulse is output. In synchronization with this, by inputting the horizontal start signal HST from the timing generator to the horizontal scanning circuit every 1H,
One horizontal period of the video signal can be sequentially written in the pixels of one row.

On the other hand, when performing a wide display with an angle of view of 16: 9, the input timing of the vertical start signal VST first moves to the beginning of the overscanning period. High-speed writing of a black signal is executed during this overscanning period. In this example, a one-stage write / multi-stage transfer (for example, three-stage transfer) system is adopted. That is, the black signals are sampled on all the signal lines in the first stage, and thereafter, the black signals are written in a plurality of horizontal lines in a multistage manner at high speed. For this reason, in this example, VCK is supplied to the liquid crystal panel after being quadrupled in speed.
Specifically, VCK is driven at a constant speed in the first 1H to perform the first-stage writing, and VCK is driven at a quadruple speed in the next 1H to transfer the sampled black signals to the signal lines in multiple stages. Therefore, one-stage write / multi-stage transfer is performed once at 2H. In response to this, HST is output every 2H. Further, the FRP is also inverted by 2H to make the black signal AC. In the one-stage writing / multi-stage transfer method, the horizontal scanning circuit can be driven at a constant speed, whereas only the vertical scanning circuit can be temporarily driven at a high speed. Originally, only the vertical scanning circuit, which is slower than the horizontal scanning circuit, needs to be speeded up, so that the load on the circuit side can be reduced. In this way, in this example, the fact that the capacitance of the signal line formed in the liquid crystal panel is much larger than the capacitance of the pixel is used to sample the black signal once and hold it in the signal line. After that, sampling is stopped and only the vertical scanning circuit is driven at high speed to write a black signal into pixels of several rows. At this time, the charge accumulated in the signal line decreases as the pixel becomes on the subsequent stage side, and the write potential decreases. To compensate for this, the voltage level of the black signal is set to a high level in advance.

In this way, after the black signal is written to a plurality of horizontal lines every 2H and the overscanning period elapses, the video signal writing period starts and the above-described vertical thinning driving is performed. That is, VCK is temporarily stopped every 4H. In response to this, the thinning-out signal ENB becomes low level by 1H, so that the vertical scanning is temporarily stopped. During this period, the video signal for 1H is idle-transferred. The inversion signal FRP is synchronized with the thinning timing. As a result, 1H inversion driving can be accurately performed even after thinning.

When a fixed pattern is displayed by thinning driving, as shown in FIG. 8A, the odd field (ODD FIELD) becomes a black level and the even field (EVEN FIELD) becomes a white level in a certain line. There is a thing. There is a risk that image signals of different levels will be written on the same line for each field, and DC offset occurs if this is left as it is. This causes burn-in. Therefore, as shown in FIG. 8B, the polarity of the FRP is inverted under a certain period to switch the phase of the alternating video signal by 180 °. As a result, one phase component indicated by hatching and the other phase component indicated by white solid cancel each other out, thereby neutralizing the DC offset. The FRP inversion cycle can be freely changed by external setting.
Usually, the polarity of FRP is inverted once every several tens to several hundreds of fields.

In the above description, the occurrence of DC offset when the thinning drive is performed has been a problem.
Image sticking occurs even when the thinning drive is not performed. This point will be briefly described with reference to FIG. (A) shows the DC offset when black display is performed by the normal speed drive, and (B) shows the DC offset that appears when black display is performed by the high speed drive. Normally, the black level of the video signal written in the liquid crystal panel is set to ± 4.0V. However, when the wide display is performed, the black signal is written in the remaining portions above and below the screen portion by the one-step writing / multi-step transfer method as described above. Therefore, a black signal with a level of ± 4.5 V or higher is required. In general, at least ± 4.0 V is required to obtain almost perfect black display. If it is less than this, it becomes a gray level. Therefore, in the upper and lower residual parts that perform the single-stage write / multi-stage transfer method,
In order to secure the write voltage of the last stage of ± 4.0V, it is necessary to set the write signal of the first stage to ± 4.5V in advance. In fact, by performing high-speed multi-stage transfer, the write voltage sequentially drops to 4.5V, 4.3V, 4.1V, 4.0V. As described above, since wide display requires a write voltage of ± 4.5 V, when a DC offset occurs during writing, image sticking is more likely to occur than in normal black display. The DC offset occurs when the center potential of the video signal and the counter potential VCOM deviate from each other as shown in the figure. As shown in (A) and (B), even if the DC offset is the same between the normal speed driving and the high speed driving, the higher the writing voltage is, the more easily the burn-in occurs during the high speed driving.
Further, in the case of image sticking, high speed driving is performed in a 2H cycle, for example, so that it is more noticeable. In addition, burn-in due to variations in write potential during high-speed transfer may be considered. This is largely affected by variations in the write capacity of the signal line. As can be understood from the above description, burn-in occurs even when the thinning drive is not performed. However,
Burn-in is more likely to occur in black display during high-speed driving that requires a write signal of 4.5 V or more than in black display during normal-speed driving. When the thinning is performed, since the step shift occurs as described above, the image is further burned. That is, the DC offset amount due to the step deviation increases. Further, since the compressed display in the present embodiment has a large thinning rate, the image sticking is apt to stand out.

Finally, with reference to FIG. 10, a measure for preventing burn-in of black display by high speed driving will be described. (A) shows before the countermeasure, and (B) shows after the countermeasure. As described above, VCK is driven at the normal speed at the first 1H and 4 V at the next 1H.
Double speed drive. As a result, the black level is written at high speed in the upper and lower residual portions of the liquid crystal panel shown in (C) by the one-step writing / multi-step transfer method. During this high speed writing, the black signal is inverted by 2H. If the inversion reference potential of the black signal is deviated from the counter potential VCOM, as shown in FIG.
An offset appears and causes a burn-in. Therefore,
As shown in (B), the phase of the black signal is periodically switched by 180 °. The rectangular wave with a solid line represents one phase, and the rectangular wave with a dotted line represents the other phase. Since both phase components cancel each other out, the DC offset disappears after the countermeasure shown in (B).

[0027]

As described above, according to the present invention, the DC offset is neutralized by periodically switching the phase of the alternating video signal by 180 °, and the burn-in which has been a problem in the past is eliminated. The effect is that it can be suppressed. This effect is particularly remarkable when the display operation is performed by thinning out the horizontal period from the video signal at any time. Further, even when a black signal is written at a higher speed than the video signal in the remaining portion left and right above and below the screen in the vertical direction when the wide display is performed by the thinning drive, the phase of the alternating video signal is periodically set to 180. By switching, a remarkable seizure prevention effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing an example of a liquid crystal panel incorporated in the liquid crystal display device shown in FIG.

FIG. 3 is a schematic diagram for explaining the operation of the liquid crystal display device shown in FIG.

FIG. 4 is a circuit diagram for explaining a thinning operation.

FIG. 5 is a waveform diagram for explaining a thinning operation.

FIG. 6 is a timing chart for explaining the thinning-out operation.

FIG. 7 is a timing chart provided for explaining a high speed write operation of a black signal.

FIG. 8 is a timing chart for explaining the operation of the alternating current circuit and the phase switching circuit included in the liquid crystal display device according to the present invention.

FIG. 9 is a waveform diagram similarly provided for explaining the operation of the alternating current circuit.

FIG. 10 is a waveform diagram for explaining the operation of the alternating current circuit and the phase switching circuit during high-speed writing of a black signal.

[Explanation of symbols]

 1 Liquid crystal panel 2 Decoder / driver 3 Timing generator 4 Analog switch 11 Screen part 12 Liquid crystal pixel 13 Video line 14 Vertical scanning circuit 15 Horizontal scanning circuit 16 Level conversion circuit 17 Thinning circuit 18 And gate element

Claims (4)

[Claims] 1. A screen unit composed of liquid crystal pixels arranged in rows and columns, a vertical scanning circuit for sequentially selecting liquid crystal pixels for one row, and writing one horizontal period of a video signal to the selected liquid crystal pixels for one row. A horizontal scanning circuit, an alternating circuit for supplying an original video signal to the horizontal scanning circuit by performing polarity inversion processing on the original video signal in advance every horizontal period, and controlling the alternating circuit to periodically A liquid crystal display device comprising a phase switching circuit for switching the phase of an alternating video signal by 180 °. 2. The liquid crystal display device according to claim 1, further comprising a thinning circuit for timing-controlling the sequential selection of the vertical scanning circuit and thinning a predetermined horizontal period from the AC-converted video signal. 3. The thinning circuit enables a wide display compressed in a vertical direction with respect to a screen portion according to the normal standard by thinning out a predetermined number of horizontal periods from a wide standard video signal. Liquid crystal display device. 4. A speed-up circuit for writing a black signal at a higher speed than a video signal by controlling the horizontal scanning circuit and the vertical scanning circuit with respect to the remaining portions vertically above and below the screen portion when wide display is performed. The liquid crystal display device according to claim 3, comprising: