JPH0273788A - Plane display device - Google Patents

Abstract

PURPOSE:To obtain a compact vertical scanning circuit by providing a circuit generating plural clock pulses for each horizontal period and a circuit selecting the vertical scanning start pulse timing in a specific combination for each vertical scanning. CONSTITUTION:An output of a shift register is shifted by one stage with respect to the input of one shift clock pulse. With two shift clocks CPV inputted, since the output is shifted by 2 stages, when two shift clocks CPV are inputted for each horizontal scanning, the shift register of one system only is used and the panel is able to be scanned from the vertical upper to the lower part in one field scanning period in the case of a display panel having, e.g., 480 scanning electrodes. In this case, it is possible to drive the scanning electrodes for two each or at an interval of one electrode for each horizontal scanning by controlling the provision of a start pulse STV in this case. Thus, a compact vertical scanning circuit is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to display devices for flat displays such as liquid crystals and plasma displays, and in particular, a vertical display device suitable for easily realizing interlaced scanning and improving resolution. Regarding the direction drive device.

[Conventional technology]

The flat display has an LCD: (Lzqatd -Crystal-
L)*5play,,,LCD)ECD: (Ela
ctro -L"hromic -L)izplay
) and other light-receiving displays and PDP: (Plasma-1)isplay
-Panel)ELD: (Elgctro
-Lurninezcgnce -Display
) L E D : (Light -E
There are light-emitting displays such as mittvn, tl-0ioclez).

Image display is performed by driving scanning electrodes (row electrodes) formed by horizontally connecting display pixels f' arranged in an IJ box shape and signal electrodes (column electrodes) formed by vertically connecting them. do. That is, by applying a voltage to the scanning electrode, the display pixels arranged in the horizontal direction are simultaneously brought into a displayable state (ON state),
By applying a signal according to an image signal to the signal electrode, the display pixels at the intersection of the scanning electrode and the signal electrode are driven and displayed.

Considering the correspondence with television display, the row lines formed by horizontally lining up display pixels 7 arranged in a matrix correspond to the scanning lines of the television. For example, in a display panel where display pixels are arranged in a matrix with 648 pixels in the horizontal direction and 480 pixels in the vertical direction, the number of row lines is 480, so a TV with 480 effective scanning lines can be used. Images can be displayed.

Television images based on the NTS C system have 5 scanning lines.
The number of effective scanning lines that can be used for image display is approximately 485, since approximately 8 sections of the 5-frame scanning period are vertical retrace periods. 1. Therefore, if the number of pixels in the vertical direction is, for example, about 480, it is possible to display about 99 pixels of an image that can be effectively displayed using the NTSC system, which is a sufficient number of pixels.

However, in the NTSC system, 525 scanning lines are not sequentially scanned. In other words, interlaced scanning is performed,
One complete screen is completed by two vertical scans.
The scan required to display this complete screen is called a frame scan, and the first vertical scan of the frame scan, which is made up of two vertical scans, is the 1st field scan (odd field scan), and the next vertical scan is the 2nd field scan. This will be called scanning (even field scanning). Frame scanning completes a complete screen with 525 scanning lines, so one field scanning (vertical scanning) completes a complete screen with 525 scanning lines.
It will display a grainy screen consisting of the scan lines of the book. If the number of pixels in the vertical direction of the display panel is 480, -
Since a coarse screen consisting of 240 scanning lines is displayed on the entire panel in one vertical scan, one field scan depends on whether the scanning electrodes are driven one by one in interlaced scanning or two at a time. You will need to devise a way to scan from the top of the panel to the bottom on hills.

In a flat display, vertical scanning is performed on the j-small side by sequentially driving scan electrodes using a shift register. A shift register is a circuit in which the output is shifted by one stage for a fixed output.For this reason, conventionally a two-stage shift register was used, as described in Japanese Patent Laid-Open No. 59-225,585. By using them in parallel or by switching the output of one stage of shift registers using a switch, interlaced driving of scanning electrodes or simultaneous driving of two scanning electrodes was realized.

However, the general-purpose vertical scan IC2 consists of a single stage shift register, and in order to use two stages of shift registers in parallel, a new vertical scan IC that combines two stages of shift registers was developed. Otherwise, special measures are required, such as alternately drawing out every other scanning electrode and connecting them to separate shift registers. In order to switch using switches and switches, it is impossible to put all the switches externally to the vertical scanning IC in terms of circuit scale and cost, so a new vertical scanning IC is used. IC must be developed.

[Problem to be solved by the invention]

Such special measures in the prior art not only result in an increase in the circuit scale, but also in that the scanning circuit board is thick and thick, which not only prevents compaction of the section shape but also increases costs.
〇In particular, it is important to make flat displays compact, and even though it is for interlaced scanning, it is difficult to arrange two or more vertical scanning ICs on both sides of the display panel for compactness. accompany.

Furthermore, developing a dedicated vertical scanning IC can be used for a specific purpose, but lacks versatility, leading to an increase in cost and creating problems in practical application.

An object of the present invention is to use a minimum driving method in which vertical scanning electrodes drawn out from one side of an element panel are driven by a single shift register, and to easily perform two simultaneous selective scanning or interlaced scanning in a compact and economical manner. The purpose is to provide a complete vertical scanning circuit to realize this.

[Means to solve the problem]

The above purpose is to generate a pulse that shifts the output of the shift register multiple times for each horizontal scan, and to control the timing of the start pulse for each field. This is accomplished by providing a circuit that changes the timing.

[Effect]

The output of the shift register is shifted by one step for each shift pulse pulse. If two shift clocks are input, the output will be shifted by two steps, so if two shift clocks are input for each horizontal scan, 1
By using only the system shift register, it is possible to scan from the vertical top to the bottom of the panel within one field scanning period even with display pulses having, for example, 480 scanning electrodes.

At this time, by fully restricting the way the start pulse is given, two scan electrodes or one scan electrode can be used for each horizontal scan.
It can be driven to skip over every other book. moreover,
By changing the timing of this start pulse between odd and even fields, it is possible to change the scanning electrodes selected between odd and even fields, making it possible, for example, to perform interlaced scanning similar to NTSC TV images. .

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 shows a Brolik diagram of an embodiment of a flat display driving device according to the present invention. There are no particular restrictions as a flat display, but IJC is currently the most advanced in practical use.
D (LiqtLid-Crystal-Displ
An embodiment using a (hereinafter referred to as a liquid crystal display or simply liquid crystal) panel will be described.

The program diagram shown in FIG. 1 includes an input terminal 1 for a composite video signal represented by a television image signal, a synchronization separation circuit 2, a synchronization control circuit 5, a double clock circuit 4, a vertical scanning circuit 5, a horizontal scanning circuit 6, A video signal processing circuit 7, an l correction circuit 8, a polarity switching circuit 9 that switches the polarity of the video signal written to the liquid crystal (primary color signal in the case of color image reproduction, luminance signal in the case of black and white) at regular intervals, and a liquid crystal display panel. (Liquid crystal panel) Consists of 10.

The configuration shown in Figure 1 is particularly suitable for driving an active matrix liquid crystal panel (described later).
``When driving an I-shiba type liquid crystal panel, for example, the polarity switching circuit 9 is replaced with an A/D converter (AI).
Instead, this ADC converts the video signal into a digital signal, and after that, this digital signal is input to the horizontal scanning circuit 6. In this case, polarity switching of the signal written to the liquid crystal is performed in the horizontal scanning circuit 6. Regardless of whether the liquid crystal panel 10 shown in FIG. 1 is of the active type or the Vavship type, the basic configuration of the double clov circuit 4, which is the core of the present invention, remains the same. The explanation will be given assuming that the panel 10 is driven.〇The operation of the circuit shown in Fig. 1 is as follows.〇A composite video signal is input to input terminal 1.
Then, the vertical synchronization signal and horizontal synchronization signal included in the input composite video signal are separated. Based on these vertical synchronization signals and horizontal synchronization signals, control signals such as kiss pulses and start pulses necessary for horizontal and vertical scanning are generated in the synchronization control circuit 3. However, the embodiment of the present invention For the sake of explanation, the double clock circuit 4, which is a circuit for generating start and shift clock pulses necessary for vertical scanning, is shown separately from the synchronization control circuit 5.The vertical scanning circuit 5 and the horizontal scanning circuit 6 are The liquid crystal panel 10 is scanned based on control signals supplied from the synchronization control circuit 3 and the double clock circuit 4.

On the other hand, the video signal processing circuit 7 processes the ska composite video signal to form all primary color signals. This formation method is the same as that used in shadow mask type color televisions. The primary color signal formed by the video signal processing circuit 7 is CP T (C'olor
-PictLLra-Tabg) is used to perform the r correction in accordance with the color image reproduction, so it is also necessary to apply the 9l correction again to the liquid J in accordance with the applied voltage vs. brightness characteristic of the panel 10. This is performed by the 7 correction circuit 8. Furthermore, if a DC voltage is applied for a long period of time, the alignment film of the liquid crystal will deteriorate due to adsorption of impurities, or in severe cases, the liquid crystal itself will vaporize and the alignment will be destroyed. It is necessary to apply primary color signals with switched polarities to the liquid crystal panel. The polarity switching circuit 9 inputs the primary color signal to the liquid crystal panel 1o through the sample field circuit included in the horizontal scanning circuit 6. do.

Hereinafter, the operation and construction of each main part of the BO+7 shown in FIG. 1 will be fully explained.

As an example of the liquid crystal panel 1D, an active matrix system is used, and FIG. 82 shows the entire configuration thereof. In Figure 2,
T++, TI2...T45 is a thin 'II FET (Ftgld -fp, ffe
ce -TrarLzirttrr ) 6) Pixel transistor Ti1 (i, , i = 1.2
．． ), then chiru. Each pixel transistor i”i
The north terminal of 7 is connected to the liquid crystal LCz7 f connection (17, these are the - group display pixels (Z, , +) specified by the row number L and column number F of the matrix column. 5 The pixel specified by the row number M. The gate terminals of the transistors 'I゛su(): 1, 2...) are drawn out with a common electrode, and f''L is called the set meal*pole Yi.Generally, the number of scanning electrodes is equal to the number of display pixels in the vertical direction. Yes, the pixel transistor Ti specified by the column number
)' (L=1.2...) is drawn out by a common electrode, and f'1 is called a signal electrode X). The number of signal poles is generally equal to the number of display pixels in the horizontal direction.

The pixel transistor T is switched by switching the gate voltage. Normally, the gate-off voltage VQOFF? is set so that each constraint transistor Ti) is in the OFF state. Scanning electrode Y
1. Next, at a predetermined time, the gate-on voltage VGO is set so that the pixel transistor T is turned on.
N is applied to the scan electrode Yi. At this time, a series of pixel transistors TsCj=+, 2, . . . are designated by the row number t.
) is ON at the same time, and the image signal is transmitted through the signal electrode X) to the liquid crystal LC connected to each pixel transistor T1.
The image is displayed in correspondence with the scanning lines of the TV image.

5 and 4 show the start pulse S formed by the double-clamp circuit 4 in an embodiment in which all two scanning poles are driven.
TV, shift black, and CPVtDjX imming chart are all shown. The double klovk CPv is synchronized with the input composite video signal, and in this embodiment is composed of two pulse trains for each horizontal opening period.

In a composite video signal, the signal period separated by the horizontal synchronization signal is one horizontal scanning period, and this one horizontal scanning period is one horizontal scanning period.
Corresponds to the scanning lines of a book. The horizontal scanning period during which an image is first displayed using this composite video signal is defined as the jrt line, and the following 1
Number all serially in chronological order within the frame period.

FIG. 5 is a timing chart during the 1st field scanning period. Two shift clocks A and B forming the double clock and CPV correspond to the 1st line scan, and C is used for the 'lnd line below.

E and F correspond to the 5th line. On the other hand, in this embodiment, the start pulse s'rv is applied so as to be High at the rising edge of the A and B pulses.

FIG. 4 is a timing chart during the 2nd field scanning period. The 2ntl field is half of the image signal of the 265rd line (this is temporarily called the 265rd line)
The line starts from the 265th line. This 265'rd
A and B shift clocks correspond to the lines, and the following 26
C and 1) correspond to the ath line, E and F, etc. correspond to the 265th line. On the other hand, in this embodiment, the start pulse STv is applied so that it is equal to the rising edge of the pulses B' and C'.

FIG. 5 shows the configuration of the vertical scanning circuit 5 in a block diagram. This circuit is the same as the vertical scanning Tc and is commonly sold. For example, Hitachi HA 6110
5 corresponds to this. Terminals 51 and 52 are input terminals for the start pulse STV and shift clock CPv, respectively. 551-55m are shift registers, 9,54
+~54m are connected to terminals 58Q, 58h, 58c, 5 according to the shift register 551~55m (7) output.
8d and t voltage (V+, V6. V5. respectively).
This is a liquid crystal drive circuit that selectively outputs V2). terminal 5
91-59m are output terminals of liquid crystal drive circuits 541-54m. The terminal 57 is connected to the terminals 58α, 5Bh, 5
Bc, applied to 58d, respectively v1≧v6≧v5
This is a control # terminal that determines whether to select and output all the voltages of the chair voltage among the voltages ≧v2. For example, terminal 57 is high (M=
+), V4. V
A voltage that selects one of the two is output, and the voltage is output from the terminal 57.
When is Low (M=0), a voltage that is either Vs or V+ is output. In the first embodiment, the terminal 57f is fixed and used (O).
In the figure, gate-on voltage application terminal 55 is connected to terminal 58α, gate-off voltage application terminal 56 is connected to all terminals 58/l,
Connect to 58C and 58d. When the terminals 55° and 56 are connected to VnoN and VGOFF @EE'fc is applied, respectively, then the following is true. Furthermore, the terminal 57 is grounded to GND (1,
ow ), M=0, so the output terminals 59 to 59 are connected according to the outputs of the shift registers 551 to 55m.
77L Karaha v() ON, v0 OFF noise voltage is output.

The start pulse STv shown in FIG. 5.4 and the shift clock CPv are input to the input terminal 51 of the vertical scanning circuit 5 shown in FIG.
is applied to 52. At this time, the vertical drive voltages 01 to 0 conductors output from the output terminals 591 to 59 are STV, (,
'This is shown in the timing chart of Figure 6.7 along with PV.

FIG. 6 is a timing chart for 1st field scanning. Since the start pulse is Ht at the rising edge of shift clocks A and B, output terminal 59. output 0
1 becomes VGON in synchronization with the rise of clock A, and the following clock B is also VGON, and becomes a pulse that returns to VGOFF in synchronization with the rise of the next clock C.

Hereinafter, the pulse waveform similar to this pulse is included in the shift clock 8TV.For each pulse input, it is shifted to the next stage output terminal 592, resulting in an fC timing chart as shown in Fig. 6. . At this time, for example, Sytlining) 1tu+ :'j! , M are sampled and held in the horizontal scanning circuit 6, and the interference period O shown in FIG.
At E1, the signals are simultaneously applied to the signal electrodes X()=1, 2, . . . The liquid crystal that can be written during the OE1 period is the liquid crystal on the scan electrodes Y1 and Y2 selected by the vertical drive voltages 01 and 02. Therefore, in the first field scanning period, the image signal of the 19t line is displayed by two rows of display pixels designated by row numbers 1 and 2. Similarly, for the write period OE 2 K of the 2yLd line, the vertical i[! lb't
'Ef:05tOa.

Since the timing of vertical drive voltages 05 and 06 matches the writing period OB5 of the 5rcL line, the image signal of the 2rLd line is displayed by two rows of display pixels designated by row numbers 5 and 4, and the image signal of the 5rd line is displayed with two lines of display pixels designated by line numbers 5 and 6. Hereinafter, the same explanation will be repeated for the 1zt field scan until the final line.

FIG. 7 is a timing chart for 2rLti field scanning. In 2nd field scanning, the start pulse becomes Hi at the rising edge of shift clocks B' and d! 1
Since it is a human, the vertical drive voltage 01 of the output terminal 59α becomes VGON in synchronization with the rising edge of clock B, and becomes VGOFF in synchronization with the rising edge of clock D. This vertical drive voltage 01
As in FIG. 6, a pulse waveform similar to the pulse of is shifted to the output terminal of the next stage every shift clock. As a result, the timing chart shown in FIG. 7 is obtained.

Similarly to the explanation in Fig. 6, the 265rα line's Kazuka Baiku? In the write period of 0E265, the image signal of the 265th line is applied to the signal electrode X during the write period of the image signal 'fOE264 of the 264th line, and in the write period of 0E265. At this time, the vertical drive voltage is 01. 02 and 05 for OB 264. Og
Since the timing of 04 and 06 matches 265,
The image signal of the 265τd line is 1 specified by the line number 1.
The image signal of the 264th line is displayed by the display pixels of the 264th line specified by the row numbers 2 and 5, and the image signal of the 265th line is displayed by the display pixels of the 2 lines specified by the line numbers 4 and 5. The image is displayed using display pixels, and the same process is repeated thereafter.

FIG. 8.9 shows the vertical scanning state of the liquid crystal panel 10 under the above driving conditions. In Figure 8.9, LCD panel 1
0 is assumed to be composed of display pixels arranged in m rows and x l columns (m2 even numbers). X1 to Xn are signal electrodes, Y1 to Ym are scanning electrodes, and pixel transistors and liquid crystals are omitted from the figure and are circled.

FIG. 8 shows the vertical scanning state in the 1st field scanning. 1. In 1't field scanning, the image signal of the 1st line is displayed on the two lines selected by the scanning electrodes Yl and Yl, and the image signal of the 2rLd line is selected by the scanning electrodes )'5 and Y4. It is displayed on two lines, and below, ? With t scanning electrodes, one scanning line is displayed in each of two rows. In this way, the image signal of the first line becomes Ym
The image continues until the two lines selected by the -+ and Ym scanning electrodes are displayed, and an image consisting of four scanning lines is displayed on the liquid crystal panel 10.

FIG. 9 shows the vertical scanning state in 2rLd field scanning. In 02rLd field scanning, 265 rd
Image signals for half of the lines (tentatively referred to as image signals for the 2651-d line) are displayed in one line selected by the Yl scanning electrode, and image signals for the 264th line are displayed in the 2nd line selected by the Y2 and Ys scanning electrodes. Hereinafter, one scanning line in each of the two rows selected by two scanning electrodes will be displayed. In this way, the image signal of the line (265-+---1)tA is displayed on the two lines selected by the scanning electrodes Ym-2 and Ym-1, and since m is set to an even number, finally (
265+-) This continues until the image signal of the th line is displayed in one line selected by the Ym scanning electrode, and an image composed of 1+1 scanning lines is displayed on the liquid crystal panel 10.

Comparing FIG. 8.9, the companion scanning lines displayed on the liquid crystal panel 10 are interlaced, with half of the first field and half of the second field overlapping each other. Such a scanning method in which the scanning lines overlap in the first field and the second field has the disadvantage that the vertical resolution is worse than in the case where the interlacing is complete. It is effective in some cases. The reason for this is shown in Figure 8.
As can be seen from ゜9, since each scanning electrode is selectively driven for each field scan, signals are also written to each liquid crystal pixel constituting the liquid crystal panel 10 at field intervals (referred to as field-by-field polarity inversion driving). This is because deterioration of the liquid crystal material and flicker are reduced compared to a method of driving the liquid crystal pixels at frame intervals (polarity inversion drive every frame). Of course, from the viewpoint of resolution, etc., polarity inversion driving may be performed for each frame, and this driving method will be explained in a later embodiment.

FIG. 10 shows a specific circuit configuration example of the double clock circuit 4 in field-by-field polarity inversion and driving according to the first embodiment. The circuit is a synchronous 4-bit binary counter with 10
5, D type flip flow 9b ([)-F F ) 106
, Analog Suita Sen (S'vV) 107. +o
s, inverter 1o';', application of a voltage VDT) (
Support) child 100, ground terminal 105, clock Q for counter 105 CLOCK input i child 101, LOADW input terminal 102.5 TAFLT signal input terminal 11Q%0D
E) Signal signal terminal 111 and output terminal 112 of start pulse STV for vertical scanning state 5 and shift clock 1 (,
'Consists of PV output terminal 104 1)-FF106
and S W 107.

108 constitutes one selector 115.

The operation of the circuit shown in FIG. 10 will be explained using the timing chart shown in FIG. 11. The input signals of the circuit shown in Figure 10 are CLOCK, LOAD, 8TA, OD and
There are four D. These include, for example, P L that oscillates at several MHz in synchronization with the vertical and horizontal synchronization signals of the composite video signal.
L (PAayg - Locked Loop) It can be formed by dividing the output of the circuit and has the timing shown in FIG. 11. 5TAI-tT is, for example, 9. of the Izt line. Rising within the image signal, TH/2(
Horizontal 8'! A pulse of half of tATH; it is a single pulse that falls in black, and is given only once for each field scan.LOAD is one pulse that repeats in synchronization with To,
The rising edge is shifted by 2TH/4 with respect to the rising edge of 5TART. That is, L at the center of 5 TART pulses.
OAL) starts up. CLOCK&! For example, 560KHz
The frequency of CLOCK is set so that the vertical scanning state 5 operates sufficiently for the output CKV obtained by dividing the frequency of CLOCKf2, and the interval between two pulses in the double cloak that is not included in CKV is ignored. Set. OD D is a synchronization pulse with a frame period of 9 times low for each field.For example, when the field is constant at 1zt, it is low (01

In the 2nd field scan, it becomes HiyA(tl).

The counter 105 has a brisset terminal A to start counting.
, B, C, D (A side is the lower bit), and the binary count value of CLOCK applied to the clock input terminal CK is input to the terminals Q, QB, Q○, QD (the QΔ side is the lower bit).
Output from. As a specific example of this counter 105, 7
411C165 is mentioned. Terminal A.

C0011] data for B, C, and D (lower bit is on the left,
yt, so A=B=O, C=D=1) is applied,
In the initial state of LOAD:O, the preset data is Φ, Q
A3. Output from QC and QD. Then LOAD=1
Counting starts in synchronization with the rising edge of CLOCK (time 1.). QA, Qa, Qo with CLOCK
.

At time t5 when the output of QD is counted from brisevt data [0011] to 4 counts, the output is [000].
Return to 0]. Since the upper bit output QD is connected to the enable terminal P, time 1. If Qn=O then P=o
Then, the count stops. Since CLOCK is counted by 4 and then stopped, two pulses obtained by dividing CLOCK by 2 are outputted from Qs, and 11 pulses obtained by dividing CLOCK by 4 are outputted from Qs, and the counting operation is stopped.

When the state of LOAD=0 again, the brisert data changes to QA, Q, B, Qa, in synchronization with the rising edge of CLOCK.
It is output from QD, but Q
A and QB remain at 0.

In this way, when LOAL)=t is reached again, the dowel operation is started at time t5, two pulses are output from QA and one pulse is output from QB, and the above synchronization is repeated every horizontal period TH. The CPV output from the terminal 104 is the same as the small one, and the CPV shown in Figures 5.4 and 6.7
becomes.

The following is the circuit part that forms the STV U-F
The output QB of the counter 105 is input to the close terminal CK of F106, and 5TART is input to the data terminal. 5TART becomes HiyA at 1zt line in 1zt fumered scan, and 26 in 2nd field scan.
This is a single pulse with a pulse width TH/2 that is repeated every field scan such that the pulse width becomes Hsh on the 5.5th line. At time t2, the output QB of the counter 105 rises, and this QB
Make sure that 5TAtLT is Hi and qA at the start-up stage. At this time, the output Q of L)-FF+06
becomes High in synchronization with the rise of Qn at time t2. At the following rising edge ψ at time t6, ST'ART is L6W, and the output Q of D-FF1[+6 goes low in synchronization with the rising edge of QB at time t6.
becomes. IJ-FF+06 repeats field scanning, especially this operation.

Furthermore, 5TART is connected to 5W107, and D-F
The output Q of F 106 applies a signal to selector 115 to connect to 5W 108. Here selector 115
In ODD20 state, 5W107 is ON and 5W
10B is OFF and 5W107 in 0DD=1 state
Selector 11 so that 5W108 is ON while OFF
5. ODD is 0 for 1st field scan
In the 2nd field scan, it is 1, so in the 1zt field scan, 5TART is selected p, and in the 2rLd field scan, the output Q of D-FF10 (S is selected. From the terminal 112, in the Izt field scan, 5TART is selected.
TART, D-FF10 for 2nd field scanning
A pulse is output that switches to the output 0 of the 5th.
This is the same as the start pulse STV shown in 4.6.7.

As described above, when the circuit configuration shown in FIG. 10 is used, it is possible to perform interlaced scanning by driving the scanning electrodes two by two using only one system of vertical scanning circuits. Of course, two scan electrodes are used. aL.

The method of giving vertical scanning crotuff pulses and start pulses for interlaced scanning is not limited to the above explanation. For example, in the scanning state shown in FIG. 8.9 of this embodiment, 1zt
In field scanning, a line is displayed every two lines selected by two scan electrodes Y1 and Y2, and in 2rLd field scanning, a line is first displayed in one line selected by scanning electrode Y1, and then every two lines. Line display is performed. 1 for this! In the t field scan, a line is first displayed in one row selected by the scan electrode Y1, and then every second row is displayed, and in the 2rLd field scan, a line is displayed in every two rows selected by the two scan electrodes Y1 and Y2. Interlaced scanning in which line display is performed is also possible. The latter scanning method can be realized by simultaneously shifting the timing of the start pulse by an odd number of clocks in odd field scanning and even field scanning.

Although the structure of the double clock circuit is slightly different, the scanning method for both is essentially the same in that two clocks are used for each horizontal period.

Furthermore, it is not essential which line of video signal the display starts from. In the following second embodiment, only a typical scanning method will be explained, and essentially the same scanning method will not be mentioned.

Hereinafter, a second embodiment will be described in which only one system of vertical scanning circuit 5 is used to drive every other scanning electrode to perform interlaced scanning.

In the second embodiment as well, the flat display driving device has the same circuit block configuration as the block diagram shown in FIG. 1. However, the timing of the vertical scanning start signal output from the double clock circuit 4 is different from that of the STV in the first embodiment, and this signal is referred to as STV. shift black l
This is the same CPV as in the first embodiment.

Figures 12 and 15 show STV and CPV, , jtl, ,
Output signal 01 from the vertical scanning circuit 5 using...
・A timing chart of the new control signal BUVK is shown. CPV is exactly the same as in Figures 5.4 and 6.7. BLNK is a pulse that rises in synchronization with the rising edge of the first pulse and falls in synchronization with the rising edge of the next pulse among two closely spaced pulse trains constituting the CPV. For example, CPv rises in synchronization with the rise of pulse A, D falls in synchronization with the rise of pulse B, and the same applies to pulse trains such as C, E and F, etc.

In order to explain the output signals 01 to 05 in FIGS. 12 and 15, the reference numbers in the drawings intersect, but FIG. 14 will be explained. FIG. 14 is a block diagram showing the configuration of the vertical scanning circuit 5 in the second embodiment. ! 14
The vertical scanning circuit 5 shown in the figure includes input terminals 51.52, shift registers 551-55. , liquid crystal drive circuit 54. ~5-
, gate voltage application terminals 55, 56, control terminal 57, selection voltage application terminals 58 (Z, 58h, 58c,
5Bd and output terminal 59. ~59. ．． The functions of each terminal and the vertical scanning circuit 5 shown in FIG.
is exactly the same. However, in FIG. 14, a newly formed BLNK is applied to the control terminal 57, and the usage is different from that in FIG. 5, where the control terminal 57 is grounded to GND. That is, terminals 58α and 58b.

The voltage applied to 5f3c and 5Bd is v1, respectively.
≧v6≧v5≧v2 Tosult, IIJ Miko 57kaHt
! qA (M21) (D (!: output terminal 591
~591 to V6. A voltage obtained by selecting one of V2 is output, and when the voltage is Low (M=O), the voltage is output from the output terminal 59. ~59. A voltage selected from either Vs or ν゛1 is output. Figure 5 and total <1'1
lr1, the gate-on voltage terminal 55 is connected to the terminal 58α, and the gate-off voltage terminal 56 is connected to the terminals 585 and 580.
．． Since it is connected to 5Bd, equation (1) also holds true in FIG.

Using this equation (1), in FIG. 14, depending on the state of the control terminal 57, the output terminals 591 to 59. It can be seen that the output voltage from I changes. That is, when M=o, output 7H
? ! Child 59+ -59, Kara Its Vs = Vnor
r, V+: The voltage of VGON (゛zuneka) is output, whereas M=1(7)(!: *&!ffj power terminal 59+ ~59,7)'u&1V6=Vz=VGO
Only the FF voltage is output. That is, when M=t, only the gate-off voltage VGOFF is output 1, and the scanning electrodes Y, .about.Y1 of the driven liquid crystal are not selected.

FIG. 12 is a timing chart for 1'' t field scanning. STV differs from the 8TV shown in Fig. 5 and No. 6, in that it has two pulse trains A, ! :B (7) HtyA is only found in the rising process of B. Therefore, the voltage output from the output terminal 591 of the vertical scanning circuit 5, that is, the vertical drive voltage 01, becomes VGON in synchronization with the rising edge of clock pulse B, and at the subsequent clock pulse C, it becomes ST.
Since V is Lovuf, 7, it becomes VGOFF at the rising edge of pulse C. At the same time, the output is shifted from the shift register 551 to the shift register 532 in the vertical scanning circuit 5 by the clock pulse C;
The BLNK signal applied to is High (ig, M =
1), the drive voltage 02 remains at VG OFF. Of course, strictly speaking, the rising edge or falling edge of %BLNC and the rising edge of CPv are the same,
There is a possibility that an uncertain voltage may be generated near this edge.

However, the generated uncertain voltage is in the form of an extremely narrow pulse, and since writing to the liquid crystal is not performed with respect to such a narrow pulse, the generation of this pulse can be substantially ignored. If necessary, the pulse width of BLNK can be expanded, so this embodiment will be described in which every other scanning electrode is driven by the BLNK.

In this way, at the rise of the next pulse D, the vertical drive bottom pressure 02 remains at VGOPF, and the vertical drive voltage 05 becomes VGON.
become. Since the vertical drive voltage is outputted in the same manner repeatedly, 1. r! In field scanning, vertical drive bottom pressure 01,
05. ...0n-t becomes VGON, but 02
, 04. ...Om remains VGOFF.

FIG. 15 is a timing chart for 'lndln-old scanning. The STV is H-ring only in the S-rise construction shown in Figures 4 and 7. Therefore, the vertical drive bottom pressure 01 is synchronized with the rise of the clock pulse C, but since the BLNK applied to the control #J terminal 57 is 11 h, the voltage remains VGOFF and does not change.餘〈pulse［
), the vertical drive voltage 01 remains VOOFF, and the vertical drive voltage 02 becomes VGON. With the next pulse E, the vertical drive bottom pressure 02 becomes V(IOFF), and the vertical drive voltage 05 remains VGOFF.
In field scanning, the vertical drive voltage is 01.05. -0n-
1 remains VGOFF, but 02゜04,...0
However, it becomes VGON.

FIG. 15 shows the vertical scanning state of the liquid crystal panel 10 in the second embodiment. As shown in Fig. 8.9 and l18i1, the liquid crystal panel 10 is composed of display pixels arranged in one dedicated column (7L: even number), X1 to XrL are signal electrodes, Y1
~Ym is a scanning electrode, and pixel transistors and liquid crystals are omitted from the figure.

The scanning electrodes Y1 to Ym are output terminals 59 of the vertical scanning circuit 5.
,~59. connected to the vertical drive respectively.
L@ is applied. 1. ft field scanning, vertical drive bottom pressure 01, 05. . . . Q, -+ become VGON, so scanning electrode Y1. Y5. ...1st, 2rLd, 5rd for each row selected by Yn-+
...The line image signal is displayed. Vertical drive bottom pressure 02, ()a, , OmkaV with 2D field scanning
GnN tonal t7) f, running ik'l 4)'2
, Y4.

・・・264 t for each row selected by Y.
A, 265th line image signal is displayed.

As a result, it can be seen that the liquid crystal panel 10'l can display images that have been completely interlaced scanned. This one
In the driving method, each scan electrode Y1 to Y is selectively driven for each frame scan, so signals are written to each liquid crystal pixel constituting the liquid crystal panel 10 at frame intervals (polarity inversion drive for each frame). ). It is said that frame-by-frame polarity reversal driving causes a large amount of deterioration of the liquid crystal material and a large frictional force, but this is a drawback peculiar to liquid crystals, and does not negate the effect of this embodiment. In this embodiment, one system of vertical scanning is used. This is an explanation of how to perform all ideal interlaced scanning using a circuit. Compared to the first embodiment, the second embodiment has the advantage of better vertical resolution, and if the disadvantages of frame-by-frame polarity inversion driving can be reduced by improving the characteristics of the liquid crystal, the second embodiment may be a more ideal driving method. be.

FIG. 16 shows the start pulse ST in the second embodiment.
A circuit forming V is shown. The circuit is 8 TV input terminals 161
, CPV input'ltp child 162. Ia t<-11
65, L) -F F164, AND165. ST
V output terminal 166fllllffll,,, terminal 161
1c input, 7'c8TVID-FF161 (Df-
CPV 1fr in/<- applied to one input of the AND 165 and input to the terminal 162, applied to the Krovk terminal CK of the D-FF 164 through the
) - Apply the output Q of FF' 164 to the other input of AND 165, and apply the ANL) output of STv and Q to i child 166
Color 8 TV and remove it.

FIG. 17 shows 1.1 of the circuit shown in FIG. 5 is a timing chart for explaining the operation in ft field scanning. CPv is connected to D-FF via inverter 165
Since the voltage is applied to the black terminal CK of 164, D-F
F 164 is synchronized to the falling edge of CPV. Since the STV applied to the D-FF 164 notator terminal at the falling edge of pulse A of CPv is Hsh, Q=1. Even in pulse B, STV is H, so Q = 1, and at the falling edge of pulse C, STV is (, ow, so Sagi = 0. This is a single pulse that becomes H and becomes LOW at the falling edge of STV.

FIG. 18 is a timing chart for explaining the operation of the circuit shown in FIG. 16 in 2nd field scanning. 'lndln-STV in the field scan is 5TA)t in FIG.
Strictly speaking, the rise of STv at 9 is later than the rise of Qa. Falling edge of pulse A and counter 1
Since the rise of output Qa of 05 is the same, the rise of STV lags behind the fall of pulse A in actual circuit operation. The STV can also be delayed by a predetermined amount if desired.

By the way, in FIG. 18, the falling edge of pulse A and the rising edge of STV are aligned, but there is no problem in assuming that S'rv is I, ow at the falling edge of Noculus A. That is, Noculus B
Since STv is High at the falling edge of , Q=1. Similarly, at the falling edge of pulse (:), considering that the falling edge of STV is slightly delayed and b, Q:1, and the falling edge of pulse [) becomes Q2. STV, which is the AND) output of STV and Q, becomes H at the falling edge of pulse B, and S'I'
It is a single pulse that becomes Lova at the falling edge of V.

The STV shown in FIG. 47.18 becomes H only at the rising edge of pulse B in 1 x i field scanning, and becomes High only at the rising edge of pulse C in 2 r Ld field scanning.

This is exactly the same as the STV shown in Figure 12.15.

FIG. 19 shows an example of a circuit for forming the control signal BLNK in the second embodiment. The circuit includes a terminal 191 that scans the output Q and a of the counter 105 shown in FIG.
cpv Os, 7] Jj child 192, 47 HaI
'95.

It consists of a D-FF 194 and a BLNK output terminal 195, and the Qs input to the terminal 191 is applied to the data terminal of the D-FF 194 via the input terminal 19, and the CPv input to the terminal 192 is applied to the D-FF 194. -Apply to the clovk terminal CK of FF 194, and output Q of D-FF 194 to BL.
It is obtained from terminal 195 as NK.

FIG. 20 is a timing chart for explaining the operation of the circuit shown in FIG. 19. QB is infielder 19
5 to the data terminal of 0-FF 194. Therefore, at the rise of the curve A of CPv, Qa is Law, that is, D is H, so 1) -FF
The output Q of 194 is Q:1. Next, at the rising edge of pulse B, QB is High, that is, D is L6w, so Q=o. Take the following two nokuru examples C, E and F.
Repeat the same action for... The pulse of Q that is formed is exactly the same as the BLNK pulse shown in FIG. 12.15.

In addition, two pulse trains are used for each horizontal opening period as shift clocks for vertical scanning, and the timing of the weight start pulse is changed between the first field scan and the second field scan. In the second embodiment, interlaced scanning is performed in which the scanning electrodes are sequentially driven two trees at a time, and increment scanning is performed in which the scanning electrodes are interlacedly driven one by one.In both embodiments, there is only one system of vertical scanning circuits. The circuit used was only a general-purpose scanning IC.

In interlaced scanning as typified by the NTSC system as described above, two pulse trains may be used as shift clocks. Even if it is necessary to realize more complex scanning,
By increasing the number of pulse trains, a single system of vertical scanning circuit using a general-purpose IC can suffice. For example, if one frame is to be interlaced scanned with five fields, which is not present in the current television system, the pulse train is divided into five pulses each. In the conventional example, it is necessary to use 5 systems of vertical scanning circuits or to switch the output with a switch.
It is becoming increasingly difficult to draw out electrodes in the system and provide vertical scanning circuits for each, or SWs require complicated switching.
Problems arise, such as the need to develop a special vertical scanning IC with a built-in device. According to the present invention, this can be easily achieved using only one system of vertical scanning circuits.

〔Effect of the invention〕

According to the present invention, the scan electrodes of the flat display are sequentially driven by using a pulse train consisting of a plurality of pulses for each horizontal scan as a shift clock for the vertical scan, and by changing the timing of the scan start pulse every time the vertical scan starts. With 10,000 vertical scanning circuits designed to Field scanning refers to sequential scanning while selecting a typical combination of scanning electrodes one by one, or field scanning refers to interlaced scanning while selecting typical scanning lines one by one, and consists of multiple fields. Since image-faithful scanning can be easily realized, for example, an NTSC television picture can be reproduced in high quality using an inexpensive and simple circuit.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram for explaining an example of a flat display driving device according to the present invention, and Fig. 2 is a block diagram of an IJ type liquid crystal flat display used in the embodiment shown in Fig. 1. , FIG. 5 shows the first NTSC system for explaining the output of the double clock circuit shown in FIG.
A timing chart for field scanning. Figure 4 is a timing chart for the second field scanning of the NTSC system, which shows the output of the double clock circuit shown in Figure 1. Figure 5 is a timing chart for vertical scanning shown in Figure 1. A circuit configuration block diagram for explaining the operation of the circuit, FIG.
An input/output signal timing chart in the first field scan for explaining the operation of the vertical scanning circuit shown in the figure, FIG. 7 is an input/output signal timing chart diagram in the second field scanning of the vertical scanning circuit shown in FIG. Figure 8 shows f
FIG. 9 is a display panel scan electrode arrangement diagram for explaining the panel display state in the g1 field scan, FIG. 9 is a display panel scan electrode arrangement diagram for explaining the panel display state in the second field scan, and FIG. A circuit diagram illustrating a specific configuration example of the double clock circuit shown in FIG.
The figure is an input/output signal timing chart for explaining the operation of the circuit shown in FIG. 10, and FIG. 12 is a timing chart for the first field scan for explaining the input/output signals of the vertical scanning circuit in the second embodiment. Chart, Figure 15 is the second
The timing chart in the second field scanning for explaining the input/output signals of the vertical scanning circuit in the embodiment, the first
FIG. 4 is a circuit configuration block diagram for explaining the operation of the vertical scanning circuit in the second embodiment, and FIG. 15 is a display panel scanning diagram for explaining the panel display state in the 1.2 field scan in the second embodiment. An electrode arrangement diagram, FIG. 16 is a circuit diagram showing a specific circuit configuration example for changing the timing of the vertical start pulse formed by the double clock circuit in the second embodiment, and FIG. 17 is an operation of the circuit shown in FIG. 16. FIG. 18 is an input/output signal timing chart for the second field scan to explain the operation of the circuit shown in FIG. 16, and FIG. 19 is an input/output signal timing chart for the second field scan. FIG. 20 is an input/output signal timing chart for explaining the operation of the circuit shown in FIG. 19. . DESCRIPTION OF SYMBOLS 1...Composite video signal input terminal, 2...Synchronization separation circuit, 5...Synchronization control circuit, 4...Double clock circuit, 5...Vertical scanning circuit, 6...Horizontal scanning circuit, 7... Video signal processing circuit, 8... r correction circuit, 9... polarity inversion circuit, 10... liquid crystal panel. Atsushi O 2nd figure 2nd figure 2nd figure Figure number 1 hanging

Claims (1)

[Claims] 1. A flat display in which display pixels are arranged in a matrix, a scanning electrode in which pixel electrodes for driving the pixels are connected in the row direction, a signal electrode in which the pixel electrodes are connected in the column direction, and A vertical scanning circuit that drives the vertical scanning electrode, a horizontal scanning circuit that drives the signal electrode, a control circuit that controls the vertical scanning circuit and the horizontal scanning circuit in synchronization with an input video signal, and a control circuit that controls the vertical scanning circuit and the horizontal scanning circuit in synchronization with an input video signal. In a display device that includes a video signal processing circuit that supplies display signals to a flat display, a circuit that generates a clock consisting of a plurality of pulses in each horizontal period as a signal to control the vertical scanning circuit, and a 1. A flat display device comprising a circuit for controlling the timing of a scanning start pulse to match a set of clocks selected in a specific combination.