JPH06202597A - Active-matrix liquid-crystal display device - Google Patents

Abstract

PURPOSE: To prevent an occurrence of flicker and luminance at the time of interlacing scanning in an active matrix liquid crystal display device. CONSTITUTION: Two adjacent row lines of matrix cells are interlace scanned during one horizontal scanning period in a pair. First two row lines is set to be a pair in an odd field and final and first row lines to be a pair in an even field, and scanning is started from these pairs. Pixels on odd row lines and even row lines are displaced by a half cycle and pixels 1 and 2 and pixels 3 and 4 are arranged in a staggered form. Since positive (up) and negative (down) polarity is inverted alternatively in the odd row lines and the even row lines, a potential difference between the terminals of thin film transistors arranged for the respective pixels can be reduced. Thus, leak current reduces and the occurrence of flicker and ununiform luminance can be reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an active matrix liquid crystal display device.

[Prior art]

A typical prior art active matrix liquid crystal display device is shown in FIG. 1, in which 1a is a thin film transistor (TFT), 1b is a liquid crystal storage capacitor and 2b is a scan driver. This scan driver sends out scan signals G1, G2, G3, etc. which are gradually delayed as shown in FIG. These scan signals are sent to the different row (row lines that are rows) conductors of the active matrix. Each row conductor is
It is connected to the gates of the TFTs in a row. Block 3
c is an output buffer constituting a data driver,
As a result, the sampled data (sample data) signals are transmitted to the column conductors D of different active matrices
1, D2, ..., Dn are sequentially sent. Each column conductor is connected to the source of the TFT 1a forming a column. When the scanning signal and the sample data signal match at the cross point, the TFT
Is turned on and the data driver has column conductors D1, D
2, ..., Dn and through the turned-on TFT, send the data signal sampled / held during the previous horizontal scan to the storage capacitor of the LCD.

When such a liquid crystal display device is used for conventional 480-line interlaced scanning,
The scan signals G1, G3, G5, ... Are sent during the odd numbered fields of one frame, and the scan signals G2, G4, G
6, ... are sent during the even numbered fields. NTS
In the C system, each field has a frequency of 60 Hz. In a particular TFT, the frequency of intermittent energization is 30 Hz. Since the liquid crystal capacitor lb has to be driven by the AC voltage, the voltage polarity of the driving voltage has to be inverted every other field.
Therefore, the driving frequency of the liquid crystal is 15 Hz. Such low frequencies cause flicker in the displayed image. By applying to the column conductors Dr (D1, D2, ..., Dn) a sampled data voltage of the opposite polarity to the voltage held by the LCD capacitor, the polarity is normally set to the last scan line (ie 480th). line)
Every other frame at the end of (ie 2 fields)
It is reversed every time. Therefore, the opposite polarity voltage is applied to the TFT
Appearing at both ends of the, the TFT at the bottom of the image at the 480th line produces a long duration. Since the off resistance of the TFT is not infinite, such a large potential difference may cause a leak current.

When a leak current occurs, the electric charge stored in the LCD is discharged. This situation is shown in FIG. Dr indicates the polarity of the data voltage that is inverted every other frame. G1 represents the scan signal (although not on the correct scale). V _LCD-1 indicates the signal voltage stored in the LCD of the first column. G480 indicates the scan voltage of the last scan line, which is the positive voltage V _LCD of the LCD in the last row as shown in FIG. 3 when the polarity of the data voltage indicated by Dr is inverted. _Occurs just before storing _-480 . After the polarity of Dr is reversed, the polarity in the TFT is reversed and the voltage difference between drain and source is greatly increased. This increase in drain-source voltage increases the leakage current and reduces the charge stored in the LCD capacitor because the off resistance of the TFT is not infinite, as shown in V _{LCD-1LCD-4 80} in FIG. Resulting in a non-uniform luminance with a relatively dark bottom. In U.S. Pat. No. 4,842,371,
Yasuda and Takafuji disclose a scheme that overcomes the above disadvantages. In this method, two video signals are provided on two adjacent lines. These two video signals are displaced by a half cycle period.
Scan signals are provided to a pair of odd and even scan lines. Two adjacent pixels are displaced by one half cycle in the scan direction so that adjacent odd and even scan lines can be scanned. Therefore, the flicker effect is reduced.

[0005]

However, the method of Yasuda and Takafuji described above has some drawbacks. Flicker can still occur because the same pair of lines is scanned in odd fields and the same adjacent pair of lines is scanned in even fields.
In addition, the timing of the sampling pulses for these two video signals may not overlap because the two video signals are presented to pixels on two adjacent lines out of phase. In such a case, the brightness of the image is gentle from the top to the bottom. Circuits that produce non-overlapping (two-phase) clocks are much more complex than the generation of overlapping (single-phase) clocks. It is an object of the present invention to realize an flicker-free active matrix liquid crystal display device. Another object of the present invention is to provide an apparatus for interlace scanning the scan lines of an active matrix liquid crystal display device. Yet another object of the invention is to simplify the clocking of interlaced signals so that overlapping clock signals can be used. Yet another object of the invention is to prevent non-uniform brightness in the image.

[0006]

These objects are achieved by the novel scanning scheme of the present invention. That is, two adjacent gate lines are simultaneously scanned in one horizontal scanning period and pairing starts from the first two lines while in odd numbered fields, but paired while in even numbered fields. Starts from the last line and the first line. Such a novel scanning method provides the advantages of interlaced scanning, eliminating the need for non-overlapping clocks for video signals. A novel overlapping sampling method is also proposed in the present invention.

[0007]

EXAMPLE A schematic diagram of the present invention is shown in FIG. 4 and 8, identical components are designated by identical reference numerals. In these figures, 201, 20
3, 205 and 207 are the first video signal lines,
Reference numerals 202, 204, 206 and 208 represent second video signal lines, and 215 represents a scanning signal circuit. The pixels in the matrix array 100 in FIG. 8 are the same as the pixel arrangement of the box 100 in FIG. 4, and in the array 100, as shown in FIG. 4, 216 to 223 receive the first video signal. The second pixel electrodes 224 to 231 represent the second pixel electrodes to which the second video signal is applied, and the reference numerals 232 to 247 represent the thin film transistors. Further, 248 to 263 are the first pixel electrodes 216 to 223 and the second pixel electrodes 224.
~ 231 represent counter electrodes arranged in a face-to-face relationship, all counter electrodes being connected together. Reference numerals 264 and 266 represent first and second liquid crystal cells corresponding to the first pixel electrodes 216 and 220, respectively, and 265 and 267 represent second pixel electrodes 22.
4 and 228 correspond to the third and fourth liquid crystal cells.

The first video signals are transmitted to the TFT 23, respectively.
The first pixel electrodes 216 to 219 through the second to 235
To the first pixel electrodes 220 to 223 through the TFTs 240 to 243. The second video signal is transmitted through the TFTs 236 to 239 to the second pixel electrodes 224 to 227, and the TFTs 244 to 247, respectively.
To the second pixel electrodes 228 to 231 via. In the scanning sequence, the scanning signal is supplied to the scanning signal supply circuit 215 for each odd numbered field (odd numbered field).
From the TFTs 232 to 212 to the scanning lines 211 and 212.
239 is turned on, and the first video signal is applied to the first pixel electrodes 216 to 219 and the second video signal is applied to the second pixel electrodes 224 to 227. After that, the scan signal is supplied from the scan signal supply circuit 215 to the scan line 21.
3 and 214 to turn on the TFTs 240 to 247, and thereby the first video signal is transmitted to the pixel electrode 22.
0-223 and the second pixel electrodes 228-231.
Applied to. The scanning is then performed in the manner described above.

FIG. 5 shows pixels arranged in a manner consistent with the arrangement of pixels. In the figure, R, G, B represent the three additive primary colors, namely red, green and blue, with the pixels in each odd numbered line displaced by a half cycle period with respect to the pixels in each even numbered line. Figure 6
When the composite video signal used in the NTSC television system is applied to the liquid crystal display device in the Yasuda and Takafuji systems, the horizontal sync signal in each odd numbered field, the first and second sampling pulses, and the composite It represents a video signal. The composite video signal is sampled by the first and second sampling pulses, the first sampling pulse being the scan line 21 of each odd numbered row.
1 and 213 and corresponding first pixel electrodes 216-
223 is a sampling pulse for the first video signal applied to H.223 and the second sampling pulse is
Sampling pulses for a second video signal applied to the second pixel electrodes 224-231 corresponding to the scan lines 212 and 214 of each even-numbered row. The first and second sampling pulses are displaced from each other by a half cycle period.

During the normal line interlaced scanning procedure, scan lines 211, 213 in each odd numbered row and scan lines 212, 214 in each even numbered row are scanned during the odd and even numbered fields, respectively. . In the method of Yasuda and Takafuji, an odd-numbered scan line 211 and a next adjacent even-numbered scan line 212 are paired for scanning, and a subsequent odd-numbered scan line 213 and a next adjacent even-numbered scan line 213 are paired. The scanning line 214 is paired. Therefore, the composite video signal shown in FIG. 6 is for an odd number field, which does not include a signal for an even number field, but the midpoint between each point for the sampled odd number field is compensated by interpolation. So that a second video signal can be obtained by sampling this midpoint.

FIG. 7 shows the first, second, third and fourth LCD cells 264, 26 in interlaced scanning.
5 shows a timing diagram showing the operation of Nos. 5, 266 and 267. In (a), one image frame has 381 and 382.
The vertical synchronizing signal in each of the odd-numbered and even-numbered fields for reproducing an image having a frequency of 60 Hz, which is composed of 30 Hz in between. (B) and (c)
Represents scan synchronization signals for the scanning lines 211 and 212, and (d) and (e) represent scan synchronization signals for the scanning lines 211 and 212. (F) is a liquid crystal cell 2
An example of the sample / hold signal corresponding to the video signal voltage which is supplied to 64 and is output from the first video signal supply circuit is shown. (G) to (j) represent each model of the sample / hold signal similar to the sample / hold signal, and (g) is the first model supplied to the liquid crystal cell 264.
Represents the polarity of the video signal of the liquid crystal cell 266.
Represents the polarity of the second video signal supplied to (i)
Represents the polarity of the first video signal supplied to the liquid crystal cell 266, and (j) represents the polarity of the second video signal supplied to the second liquid crystal cell 267.

As shown in FIG. 7, during the period of each of the odd-numbered and even-numbered fields, the first and second video signals (g) and (h) are supplied to the scan lines 211, respectively.
It is output from the first and second video signal supply circuits in synchronization with the scan synchronization signals (b) and (c) for 212. Thereafter, the first and second video signals (i) and (j) in which the polarities of the first and second video signals are respectively inverted are synchronized with the scanning lines 213 and 214, respectively, and the first and second video signals are outputted. It is output from the supply circuit. At this time, the first video signal has a phase shift of 180 °, that is, a half cycle period, with respect to the second video signal. In FIG. 7, the first, second, third and fourth liquid crystal cells 264,
Although only 265, 266 and 267 are shown, the first liquid crystal cell has the same polarity as the row of the second liquid crystal cell 265 and the corresponding row of the first pixel electrode corresponding to the third liquid crystal cell 266 is the fourth row. Has the same polarity as the row of the fourth pixel electrode corresponding to the liquid crystal cell 267 of FIG. Therefore, the difference between the analog data signals of the adjacent odd-numbered field and even-numbered field is small, and the arrangement of the pixel electrodes is such that the first pixel electrode is aligned with the scanning direction from the second pixel electrode by a half cycle period. The average optical response spectrum of the liquid crystal panel is half of the field frequency, that is, 30 Hz because it is displaced.

Yasu described with reference to FIGS.
It should be noted that in the da and Takafuji systems, the same two lines are always paired together. For example, line 211 is always paired with line 212 and line 2
13 is always paired with line 214. Such fixed pattern pairing does not constitute interlacing, which is a desirable mechanism for reducing flicker. Also,
Also note that the first video signal provided to a liquid crystal cell, such as H.264, must be out of phase with the first video signal provided to the liquid crystal cell 266 adjacent cell 265 in the adjacent pair of lines. Should. Two video sampling pulses (ie, first and second)
Sampling pulse) does not overlap.
Such schemes require fast sampling rates and much more complex video switching circuitry, resulting in difficult and complex circuit designs. The present invention eliminates the drawbacks of the conventional example, and a schematic diagram of the present invention is shown in FIG. The same reference numerals are used for the same parts as in FIG. The present invention is characterized by a circuit that supplies first and second video signals.

The arrangement of pixels for the three primary colors is shown in FIG.
As shown in (a), the red (R), green (G) and blue (B) pixels are arranged in a triangular array. While in the first field, the polarity of the video signal alternates every other line as shown in FIG. 9 (b). While in the second field, the polarity of the video signal is inverted as shown in Figure 9 (c). It can be seen that two adjacent lines alternate their polarities. In this way, the voltage difference across the TFT can be reduced, and the adverse effects of flicker in the vertical direction and uneven brightness can be reduced. As an example, take the TFT in the line of FIG. When these TFTs are turned off, the voltages at the drain and source do not always have opposite polarities in the same field. Rather, the polarities alternate while in the same field. Therefore, the leak current at both ends of the TFT is reduced.

Such potential reversal is realized by the horizontal scanning circuit 1 of FIG. 8 in the present invention. Circuit 1
Then, sampling clocks Q1, Q2, Q3, Q4
And Q1 ', Q2', Q3 ', Q4' are generated. Two
Is a sample / hold control circuit which produces alternating signals S1 and S2 in response to control signals H1 and H2. The signals S1 and S2 are connected to the switches WA1 and WB.
Multiple samples / via 1, WA2 and WB2 etc.
It is sent to the hold circuit. SAn and SBn (n = 1
4) are analog switches associated with the operation of switches WAn and WBn. When the clocks Q1 to Qn and Q1 'to Qn' are sequentially supplied to sample the R, G and B video signals, the switch WAn is turned on, the switch SAn is turned off and the switch SBn is turned on and sampled. Data collected before sample /
It is output via the voltage follower 11 together with the held data. Switch WBn is on and switch S
The same operation is performed when Bn is off.

In the vertical scanning driver 215, two lines are simultaneously scanned during the horizontal scanning. However, the pair configuration is different for odd and even numbered fields. Therefore, the paired configuration is interlaced. When the NTSC video signal is interlaced in this manner, each field has a horizontal scanning period of 262.5. The 263rd horizontal scanning period is paired with the first horizontal scanning period or more, and the 264th horizontal scanning period is set to be the first horizontal scanning period or less. Therefore, 263 horizontal scanning periods constitute the first line of the even numbered field of the video signal, and 264th horizontal scanning period, as shown in FIG. Make up the third line of the image frame. As shown in FIG. 10, when two pixel lines are scanned in one horizontal scanning period, the driving frequency for each pixel is 60 Hz. Due to the polarity inversion of the drive signal, the effective drive frequency is 30 Hz as described above. At 30 Hz, the flicker effect is blocked.

The relationship between the "read" and "write" operations for the scan signals G1, G2, G3 and G4 in the sample / hold circuit is shown in FIG. In the figure, SH-A includes WAn + 5 + SAn, and SH-B includes WBn ++ SBn (n = 1, 2,
3, ...). From the waveform diagram of the upper portion of FIG. 12 associated with odd numbered frames, it can be seen that there is a set of up and down (positive and negative polarities) samplings at every horizontal scan period. For example, in the scan cycle 1 of FIG. 12, the sample / hold circuit SH-A
Generate a (W) positive signal RA + and a negative signal BA- written to the sample / hold circuit (W (RA +,
BA-)). Next, in scanning cycle 2, these 2
The two signals are read out as signals G1 and G2, respectively (R (RA +, BA-)). The operation on the pair of signals G1, G2 provided by the circuit SH-B is:
Alternate to the operation for G4, ie in scan cycle 2,
Positive signal RA + and negative signal BA- are written into separate sample / hold circuits and read as signals G3 and G4 generated in scanning cycle 3. As shown in the waveform diagram in the lower part of FIG. 12, during even-numbered fields,
The polarity of the signal is inverted on BA + and RA- and read /
Write pairs are interlaced.

The sampling rate is reduced by the overlapping sampling method. The sampling sequence for the pixel arrangement shown at the top of FIG. 13 is shown at the bottom of FIG. Since pixels 3 and 4 are displaced with respect to pixels 1 and 2, the timing between pixel 1 and pixel 2 is twice the timing between these pixels 1 and 2 and pixel 3.

[0019]

Since the present invention is configured as described above, when the resolution in the horizontal direction is, for example, about 640, the sampling frequency of about 12 MHz is conventionally required, but the overlapping sampling according to the present invention is performed. With clock and staggered up / down sampling, the sampling rate is reduced to half of 640 / 53us = 12 MHz or 6 MHz for the same 640 resolution. The reduced sampling rate makes the sample / hold circuit easier to design and less expensive. In addition, power consumption is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional active matrix liquid crystal display device.

FIG. 2 is a waveform diagram showing the video signal and associated turn-on time of the LCD of different scan lines for a conventional LCD display device.

FIG. 3 is a waveform diagram showing the effect of polarity reversal on signal voltage leakage for a relatively low portion of the image.

FIG. 4 Ya in US Pat. No. 4,482,371.
FIG. 3 is a block diagram showing a conventional technique disclosed by Suda and Takafuji.

FIG. 5 is an explanatory diagram showing a pixel array for three primary colors.

FIG. 6 shows sampling timing signals for the Yasuda and Takafuji systems.

FIG. 7 is a waveform diagram showing pairing of synchronization signals for four scanning lines.

FIG. 8 is a schematic block diagram showing the present invention.

9A is a diagram showing a matrix arrangement of the present invention for three primary colors, FIG. 9B is a diagram showing polarities of an LCD array in a first field, and FIG. 9C is a diagram showing
It is a figure which shows the polarity of the LCD array in a 2nd field.

FIG. 10 is a waveform chart showing timings of different scanning lines in the device of the present invention.

FIG. 11 is an explanatory diagram of scanning timing for an odd (number) field and an even (number) field in the present invention.

FIG. 12 is a waveform chart showing the timing of sampled / held signals in the present invention.

FIG. 13 is an explanatory diagram showing timings of sampling clocks in the present invention.

Claims (9)

[Claims] 1. A column of video signal lines and a row of scan lines arranged in a matrix and arranged at each intersection between the rows and columns to receive a video signal via an active element. An active matrix liquid crystal display device including a pixel electrode for scanning, the liquid crystal display device being scanned by an interlaced scanning method by a signal supplied through the scan line, wherein two adjacent rows in a matrix are provided. And a means for scanning each set with an interlaced scan signal during an odd numbered field, and an odd numbered source line each connected to one row of each set. An even numbered source line connected to the other row in each set,
An even-numbered source line is connected to the one row of each of the sets and an odd-numbered source line is connected to the other row of each of the sets during an even-numbered field. An active matrix liquid crystal display device characterized in that 2. The active matrix liquid crystal display device according to claim 1, wherein the active elements to be switched are thin film transistors. 3. The active matrix of claim 1, wherein the odd numbered source lines are connected to a first video signal source and the even numbered source lines are connected to a second video signal source. Liquid crystal display device. 4. The active matrix liquid crystal display device according to claim 2, wherein the liquid crystal cells in the odd numbered rows are displaced from the liquid crystal cells in the even numbered rows by a half cycle period. 5. The active matrix liquid crystal display device according to claim 4, wherein the pixels for the three primary colors of red, green and blue are arranged in a triangular shape. 6. The polarity of the video signal applied to each liquid crystal cell is inverted for odd-numbered fields and even-numbered fields.
An active matrix liquid crystal display device as described. 7. The first video signal is sampled / held while scanning every other liquid crystal cell,
Then, while scanning the remaining liquid crystal cells, the second video signal is output to each pixel electrode, sampled / held, and then output at a time interval associated with the first video signal. The active matrix liquid crystal display device according to claim 2. 8. The sampling clock cycle is 1
2 during the period of scanning one liquid crystal cell along one scanning line
8. An active matrix liquid crystal display device as claimed in claim 7, characterized in that it is equal to twice. 9. The active matrix liquid crystal display device according to claim 8, wherein the sampling clock for one liquid crystal cell overlaps with the clock for sampling the next liquid crystal cell to be scanned.