JPH06301007A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To solve problems of flickering, degradation in contrast and degradation of dynamic resolution. CONSTITUTION:Pixels already inputted with image signals before termination of a specified period (for example, one field period) are refreshed by applying a refresh potential VD or VD thereto, by which the image holding period of the pixels is shortened at the time of making display by inputting image signals to the pixels of the pixel columns selected by selective scanning of the pixel columns at a specified period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a liquid crystal display device having a plurality of pixel columns having a plurality of pixels.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have come to be widely used as flat displays used in small televisions, personal computers, word processors and the like.

A black and white CRT has been used as a viewfinder for video cameras.
An example of using a liquid crystal color viewfinder using a color liquid crystal display device has been seen and is gradually becoming popular.

A viewfinder using a liquid crystal display device (liquid crystal viewfinder) is smaller than a cathode ray tube system, is easy to handle, and is easy to colorize. However, there are some points to be improved in terms of display characteristics.

For example, the liquid crystal display device has a problem that the resolution is not sufficient as compared with the cathode ray tube system, flicker is more likely to occur, and afterimages often occur.

FIG. 6 is a schematic configuration diagram for explaining an example of the configuration of a typical liquid crystal display device when the liquid crystal display device is used as a television.

In FIG. 6, 10 is a vertical shift register, 20 is a horizontal shift register, 22 is a switching transistor, 24 is a common signal line, 30 is a signal inverting circuit,
40 is a clock oscillation circuit, 100 is a liquid crystal panel, V ₁ ,
V ₂ , ..., V _m-1 , V _m are address signal lines, D ₁ , respectively
D _2, ···, D _n are each vertical data signal line, S is the output signal signal, S 'is having an image information output from the signal inversion circuit 30 having an image information.

The vertical data signal lines D _{1 to} D _n are respectively connected to the signal line 24 via the switching transistor 22, and the signal from the horizontal shift register 20 is supplied to the clock oscillation circuit 40 at the gate of the switching transistor 22.
A signal is provided based on the signal from. The signal from the clock oscillation circuit 40 is also supplied to the vertical shift register 10, and in synchronization with the signal S, the address signal lines V _{1 to} V _m are sequentially driven. Further, the signal from the clock oscillation circuit 40 is input to the signal inverting circuit 30, and the signal S is inverted in synchronization with the signal S. The clock oscillation circuit 40 is normally synchronized with the signal S by inputting a synchronization signal (not shown) generated by using the signal S having image information.

That is, the vertical shift register 10, the horizontal shift register 20, and the signal inversion circuit 30 perform the required television scanning by the pulse generated by the clock generator 40.

In the liquid crystal panel 100, pixel columns are selected by the address signal lines V _{1 to} V _m from the vertical shift register 10 and the driving pulses H _{1 to} H _{m of the} horizontal shift register 20 are selected.
Then, the switching transistors 22 are sequentially driven to select the vertical data signal lines D _{1 to} D _n , and the image signal is input to each pixel.

As described above, the input side of the switching transistor 22 is connected to the signal inverting circuit 3 via the common signal line 24.
It is connected to 0. The signal inversion circuit 30 is a circuit for converting an input image signal into an AC drive signal in order to prevent deterioration of liquid crystal characteristics. For AC drive of liquid crystal, frame inversion, field inversion, 1H (horizontal scanning period)
Inversion and bit (pixel by pixel) inversion are known.

FIG. 7 is an equivalent circuit for explaining the liquid crystal panel 100 shown in FIG. In FIG. 7, nine pixel portions driven by the data signal lines D _{1 to} D ₃ and the address signal lines V _{1 to} V ₃ of the liquid crystal panel 100 are extracted and shown.

In FIG. 7, 5 is a liquid crystal pixel, 7 is a switching transistor provided for each pixel, 8 is a common electrode line, and 9 is an additional capacitor. One of the electrodes of the liquid crystal pixel 5 and the additional capacitor 9 is electrically connected to the output side of the switching transistor 7, and the other is connected to the common electrode line 8. The input side of the switching transistor 7 is electrically connected to the data signal lines D _{1 to} D ₃ for each pixel in the vertical direction. The address signal lines V _{1 to} V ₃ are electrically connected to the gate of the switching transistor 7 commonly to the horizontal pixel column.

An example of a method of driving the liquid crystal panel shown in FIG. 7 will be described with reference to FIGS. 8 to 11.

FIG. 8 is a diagram for explaining the outline of the interlaced scanning, in which the odd-numbered pixel rows V ₁ , V ₃ , V ₅ , ... Are driven in the odd field and the even-numbered pixel row is driven in the even field. Pixel rows V ₂ , V ₄ , V ₆ , ...
.. indicates that selective driving is performed.

FIG. 9 is a timing chart for explaining the drive pulse of the horizontal shift register 20. As shown in FIG. 9, drive pulses H ₁ , H ₂ ... H _n (H _n is not shown) corresponding to the number of horizontal pixels n are output during 1H period, and each pixel of the selected pixel row is output. A signal (image signal) having image information is input to each.

FIG. 10 is a timing chart for explaining an example of the output signal S'from the signal inverting circuit 30. Figure 1
In 0, the output signal S'is inverted in one frame period.

This signal inversion is performed in order to prevent deterioration of the liquid crystal due to driving as described above, and the liquid crystal is AC-driven, but in the case of interlaced scanning, signal inversion is performed at a cycle of one frame as shown in FIG. Known to do.

However, due to the rising and falling characteristics of the brightness of the pixel with respect to the applied voltage of the liquid crystal, that is, the time required for the falling to rise is long, the holding voltage is lowered due to the leakage of the switching transistor, and the time constant of the drive line is used. Due to the influence of signal delay or the like, the brightness of the pixel may change every frame period, which may cause a problem that a flicker or a difference in contrast between the top and bottom of the screen is conspicuous.

Therefore, as shown in FIG. 10, the signal can be inverted every 1H to spatially integrate the flicker and contrast differences between adjacent pixel columns to reduce the flicker and contrast differences. Are known.

That is, as shown in FIG. 10, when the inverted signals are compared in the same pixel column, the signals are inverted every frame, and when the adjacent pixel columns are compared, the signal is inverted every 1H, thereby suppressing the deterioration of the liquid crystal. It is known to perform better image display.

[0022]

However, as shown in FIG.
By performing the 1H inversion as shown in, the flicker and the contrast difference due to the temporal difference between the odd field and the even field are reduced, but from the viewpoint of performing a better image display, the flicker and the contrast difference are still present. Was insufficiently reduced.

Because the flicker and the contrast difference are conspicuous to human eyes with a change of several% of the brightness, 1H
This is because it is necessary to match the signal potential and the signal level of the inverted signal even in the inversion method. That is, in order to reduce the flicker that greatly occurs during one frame, it is necessary to make further fine adjustment.

FIG. 11 is a timing chart for explaining the signal voltage holding period of the liquid crystal pixels in the odd field and the even field.

In interlaced scanning, signals of the same pixel are rewritten every frame. The video input is typically a field store signal. Therefore, the so-called dynamic resolution of a moving object is lowered by holding the signal voltage of the liquid crystal for one frame. Therefore, there is a problem that the dynamic resolution is further reduced together with the afterimage characteristics of the liquid crystal.

The present invention has been made in view of the above problems, and an object thereof is to provide a driving method of a high-quality liquid crystal display device having low flicker, uniform contrast over the entire screen, and good dynamic resolution. To do.

[0027]

The above object is to scan a pixel array of a liquid crystal element having a plurality of pixel arrays having a plurality of pixels at a desired cycle, input an image signal to each pixel, and perform display. In the method of driving a liquid crystal display device, the method is achieved by resetting pixels to which image signals have already been input.

As a result, it is possible to solve the flicker, the decrease in the contrast, and the decrease in the dynamic resolution that have occurred up to now, and to perform extremely excellent display.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A driving method of the present invention for solving the above problems will be described below with reference to the drawings.

The present invention solves the above-mentioned problems by resetting each pixel during a certain period of image input to shorten the image holding period.

FIG. 1 shows an image voltage holding period of the liquid crystal display device of the present invention when interlaced scanning is taken as an example.

In FIG. 1, V ₁ , V _3, ... Are odd-numbered pixel columns as described above, and V ₂ , V ₄ , ... Are similarly even-numbered pixel columns. Also, V ₁ ′, ..., V ₂ ′ indicate scanning in the next frame.

As shown in FIG. 1, in the present invention, after the display is held for one field period, the pixel is reset and a voltage corresponding to a substantially black image for about one field period until the next image writing is performed. Held in.

By performing such driving, the problems caused by the long fall characteristic of the liquid crystal and the problems caused by the reduction of the holding voltage due to the leakage of the switching transistor are positively solved, and as a result, the flicker and the contrast are reduced. The difference can be reduced.

Further, by shortening the sampling time of the signal having the image information, it is possible to substantially improve the deterioration of the dynamic resolution.

Next, FIG. 2 shows a structural example of a liquid crystal display device for implementing the driving method of the present invention, and FIG. 3 shows a timing chart thereof.

In FIG. 2, a switching transistor is an interlacing switch for selecting an address line of a pixel column, and a switching transistor 22 is a switch for resetting each pixel. Transistor odd address lines V ₁ corresponding to the connected and .phi.V _A to each drive pulse .phi.V _A and .phi.V _B to the switching transistor for interlaced control, V _3, the transistors corresponding to .phi.V _B even address lines V ₂ is connected to V _4, in the odd field image input is performed in the pixel column is connected to V _1, V _3, is connected to the pixel columns V _2, V ₄ reset input is performed. In even fields,
The image input and the reset input are opposite to the above description.

The switching transistor 22 inputs the reset voltage to the pixels of the pixel column which is controlled and selected corresponding to the horizontal blanking period (H, BLK).

In the odd field as shown in FIG. 3, the switching transistor 12-a is activated during the horizontal effective period.
After that, the pulse φA becomes “H” so that the pixel switching transistors 7 of the address lines V ₁ and V ₃ are turned on and the image signal is input.

At this time, φB is the horizontal blanking period (H,
BLK) becomes “H” and the pixel switching transistors 7 of the address lines V ₂ and V ₄ are turned on, and a reset signal is input.

The pulse φT connected to the gate line of the pixel reset control switching transistor 22 is a pixel reset φB (φ) within the horizontal blanking period (H, BLK).
It becomes "H" corresponding to A). In FIG. 3, V _DD ′ is a reset voltage, and this reset voltage is inverted every 1H and every field so as to correspond to the inverted signal. V _D
Is a reset potential (black image) when a negative potential signal is applied to the common electrode potential V _LC , and V _D ′ is a reset potential when a positive potential signal is applied.

Another embodiment of the present invention will be described with reference to FIGS.

In the case of this embodiment, the method of supplying the reset potential is different from that of the previous embodiments.

FIG. 4 is a configuration diagram for explaining the configuration of the liquid crystal display device of the present embodiment, and FIG. 5 is a part of the timing diagram thereof, in which φT is replaced by φT in the timing diagram shown in FIG.
1, φT2. In addition, the reset potential V
_DD 'is fixed to V _D or V _D '.

As shown in FIG. 4, the reset control transistor 22-A is provided separately from the V _D' transistor 22-B.
Reset potential V _D or V _D 'is supplied as necessary to each pixel by -B.

Therefore, in this case, the transistor 22-
Reset control pulse φT supplied to A and 22-B
1 and φT2 are pulses for every 1H as shown in FIG.

In the above-described embodiment of the present invention, an example of resetting every field has been shown, but the present invention is not limited to this embodiment.

For example, the vertical shift register may be divided into an odd field and an even field so that the image potential holding time is 1/2 field or 3/2 field, and the horizontal pixels are not collectively reset, but the data lines are not reset. May be separately provided and reset in accordance with the scanning of the horizontal shift register.

The present invention can also be applied to a liquid crystal display device of the type in which a storage capacitor for accumulating an image signal for 1H is provided and the image signals are collectively transferred to the data line.

Further, even in the case of a field scanning type having pixels for fields, the image voltage holding time may be controlled as in the gist of the present invention.

[0051]

As described above, according to the present invention, since the image voltage holding period is shortened, the occurrence of flicker can be reduced and the dynamic resolution can be remarkably improved.

[Brief description of drawings]

FIG. 1 is a timing diagram for explaining a voltage holding period of a liquid crystal display device of the present invention.

FIG. 2 is a configuration diagram for explaining an example of a liquid crystal display device of the present invention.

FIG. 3 is a timing diagram of drive pulses of the liquid crystal display device shown in FIG.

FIG. 4 is a configuration diagram for explaining an example of a liquid crystal display device of the present invention.

5 is a timing diagram showing a part of a drive pulse of the liquid crystal display device of FIG.

FIG. 6 is a schematic configuration diagram of a liquid crystal display device.

7 is an equivalent circuit of the liquid crystal display device shown in FIG.

FIG. 8 is a diagram illustrating interlaced scanning.

FIG. 9 is a timing diagram for explaining drive pulses of the horizontal shift register.

FIG. 10 is a timing chart for explaining an output signal from the signal inverting circuit.

FIG. 11 is a timing chart for explaining a signal voltage holding period of a liquid crystal pixel.

[Explanation of symbols]

 10 Vertical shift register 20 Horizontal shift register 22 Switching transistor 22-A Switching transistor 22-B Switching transistor 30 Signal inversion circuit 40 Clock oscillation circuit 100 Liquid crystal panel

Claims (3)

[Claims] 1. A method for driving a liquid crystal display device, comprising: scanning a pixel row of a liquid crystal element having a plurality of pixel rows having a plurality of pixels at a desired cycle to input an image signal to each pixel for display. A method for driving a liquid crystal display device, which comprises resetting pixels to which an image signal has already been input in the middle of the cycle. 2. The method of driving a liquid crystal display device according to claim 1, wherein the period is one field period. 3. The method of driving a liquid crystal display device according to claim 1, wherein the period is 1/2 or 3/2 field period.