KR100256974B1 - Multi-scan apparatus - Google Patents

Abstract

PURPOSE: A multi scanner is provided to shrink a screen in case that the number of vertical lines of an LCD panel is larger than that of vertical lines of a video source in displaying a video signal different in a display format. CONSTITUTION: A multi scanner is equipped with a flip/flop(26) of a shift register, a switch controller(28) connected to the first flip/flop(26), switches(S1, S2, S'1, S'2) connected to the switch controller(28), capacitors(Qa1, Qa2, Qb1, Qb2) commonly connected to a GND and 3 state buffers(30) which connect to the switches(S1, S2, S'1, S'2) and have a control terminal in order to provide a control signal. In case that a horizontal start pulse is provided to the first flip-flop(26), and a horizontal pixel shift clock is provided to all flip-flops connected to the first flip-flop(26). A driving signal of the first flip-flop(26) is provided to the switch controller(28). The switch controller(28) drives the capacitor charge switches(S1, S2, S'1, S'2).

Description

Multi-Scan Apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display such as a liquid crystal display, and more particularly, in a flat panel of a matrix type such as a liquid crystal display, in which the number of vertical lines of the display screen and the number of vertical lines of the video source screen differ so as to be bonded to the display screen. A multi-scan device for displaying a video source screen.

Recently, video media have tended to display video signals as digital video signals that can easily compress information instead of analog video signals in order to provide high-resolution images to viewers. Accordingly, a type of image display device that displays a video signal as a digital image signal can be thinned and has excellent resolution. Recently, a liquid crystal display (LCD), which has been developed for business or home use, is commercially available. As a thin film transistor ("TFT") is used as a switching device, research and development is being accelerated.

FIG. 1 shows a TFT LCD which emerged by this development effort.

In FIG. 1, the sample / hold section 6 and the shift register 8 will be described in detail with reference to FIG.

As shown in FIG. 1, a conventional TFT LCD is connected to the gate driving circuit 4 for driving the gate lines of the liquid crystal display panel 2 and the source lines of the liquid crystal display panel 2 to drive the source lines. A sample / hold section 6, a shift register 8 connected to the sample / hold section 6, and a plurality of flip / flops 12 are cascaded, a gate driving circuit 4 and a shift register. An LCD timing controller 10 connected in common to (8) is provided. In the liquid crystal display panel 2, TFTs (not shown) are formed as switching elements at intersections of the gate lines and the source lines. The LCD timing controller 10 includes a horizontal start pulse (HST), a horizontal pixel shift clock (HCK), a vertical start pulse (VST), and a vertical pixel shift clock for driving the gate driving circuit 4 and the shift register 8. VCK) is generated. When the horizontal start pulse (HST) signal is applied to the first flip / flop 12 of the shift register 8 and the horizontal pixel shift clock (HCK) is applied to the shift register 8, the video is transmitted to the sample / hold part 6. The data is supplied. Then, when the horizontal pixel shift clock HCK is raised after the horizontal start pulse HST is applied, two pixels that receive video data one pixel and charge and discharge one line of data by the controller 14 are controlled. It is stored in the sample / hold section 6 composed of capacitors Qa1 and Qa2. The stored signal outputs one line of data to the liquid crystal display panel 2 at the same time when the gate driving circuit 4 is driven by the vertical start pulse VST and the vertical pixel shift clock VCK. This operation is repeated from line 1 to the last line and back to the first line to display.

The TFT LCD can be supplied with a video source signal of various modes. In this case, since the source line of the liquid crystal display panel 2 is limited, the video source signal cannot be properly displayed on the liquid crystal display panel 2. In the case where the number of vertical lines of the liquid crystal display panel 2 is larger than the number of vertical lines of the video source, many related technologies have been developed to display by performing a zoom process. On the other hand, when the number of vertical lines of the liquid crystal display panel 2 is smaller than the number of vertical lines of the video source, related technologies that can be shrunk and displayed are still insufficient, and even published technologies have complicated structures and costs. The synergistic effect is causing the problem. An example of a related art for displaying by performing a shrink or double speed process will be described with reference to FIG. 3, in particular, when the number of vertical lines of the liquid crystal display panel 2 is different from the screen of a video source to be displayed. When the number of vertical lines of the panel 2 is smaller than the number of video source lines, conventionally, a memory clock is used to convert an input video source to a display format of an LCD to digitally convert a signal to a read clock suitable for the format of an LCD. The screen is displayed by shrunk using.

In this case, a line signal from the analog-to-digital converter (hereinafter referred to as "A / D converter") 16 and the A / D converter 16 that converts RGB image data in analog form to digital form is output. A digital-to-analog converter (hereinafter referred to as a "D / A converter") which converts a digital signal from the image memory 18 and the image memory 18 to be stored into an analog form and supplies it to the LCD driving circuit 22. 20 and a memory / controller 24 for supplying and controlling the horizontal and vertical synchronizing signals Hsync and Vsync are connected.

As described above, when the number of vertical lines of the liquid crystal display panel 2 is smaller than the number of vertical lines of the video source to be displayed, the configuration is not only complicated in the related art, but also raises the cost and causes problems of utility and practicality. have.

Accordingly, an object of the present invention is to provide a multi-scan apparatus that allows screens to be shrunk when the number of vertical lines of the liquid crystal display panel is smaller than the number of vertical lines of the video source in displaying video signals having different display formats.

It is another object of the present invention to provide a multi-scan apparatus which displays a video signal having a different format with a simple configuration.

It is still another object of the present invention to provide a multitude scan device which minimizes the difference in resolution of a displayed video signal when a screen is shrunk and displayed.

1 is a block diagram schematically showing a conventional liquid crystal display device.

FIG. 2 is a detailed circuit diagram showing in detail the sample / hold section and the shift register in FIG.

3 is a schematic block diagram showing a conventional double speed processing apparatus.

4 is a circuit diagram showing the configuration of a sample / hold circuit for driving one pixel in a multi-scan device according to an embodiment of the present invention.

5 is a timing diagram showing the driving procedure of the multi-standby apparatus and method according to the first embodiment of the present invention step by step.

6 is a view showing a display screen in FIG.

7 is a timing diagram showing step by step driving procedures of the multi-scan apparatus and method according to the second embodiment of the present invention.

8 is a view showing a display screen in FIG.

* Explanation of symbols for main parts of the drawings

2: liquid crystal display panel 4: gate driving circuit

6: Sample / Hold Part 8: Shift Register

10: LCD timing controller 12, 26: flip / flop

14 controller 16 analog-to-digital converter

18: Picture Memory 20: Digital / Analog Converter

22: LCD driving circuit 24: memory / controller

28: switch controller 30: 3 status buffer

S1, S2, S'1, S'2: Switch Qal, Qa2, Qb1, Qb2: Capacitor

In order to achieve the above object, the multi-scan apparatus of the present invention provides a liquid crystal display panel in which pixel cells are arranged at intersections of a plurality of source lines and a plurality of gate lines, and a shift to which a start pulse and a horizontal pixel shift clock are supplied. As the register and the shift register are driven, a video signal is stored to alternately delete some lines of the video signal at random intervals in the odd and even frames to supply the source lines of the LCD panel. And a gate driving circuit connected to the gate lines to drive the gate lines as the vertical pixel shift clock is supplied.

The multi-scanning apparatus of the present invention includes a liquid crystal display panel in which pixel cells are arranged at intersections of a plurality of source lines and a plurality of gate lines, a shift register supplied with a start pulse and a horizontal pixel shift clock, and a source line. The video signal is stored as the shift register is driven to supply the average value of some lines of the video signal to the source lines of the liquid crystal display panel at arbitrary intervals, and the vertical pixels connected to the gate lines. And a gate driving circuit for driving the gate lines as the shift clock is supplied.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8.

4 shows a configuration of a sample / hold circuit for driving one pixel in a multi-scan apparatus according to an embodiment of the present invention.

In the configuration of Fig. 4, the multi-scan apparatus of the present invention for driving one pixel includes a switch controller 28 connected to a flip / flop 26 of a shift register, a first flip / flop 26, and a switch controller. A capacitor commonly connected to the switches S1, S2, S'1, S'2 connected to the 28, the switches S1, S2, S'1, S'2 and the ground voltage source GND. 3 state buffers (hereinafter referred to as "buffers") that are connected to the fields Qa1, Qa2, Qb1, Qb2 and the switches S1, S2, S'1, S'2 and have a control terminal for supplying a control signal. (30).

The sample / hold portion, which consists of capacitors Qa1, Qa2, Qb1, and Qb2, which is configured for two charges and two discharges, is line-at-a-time when an image is displayed on the liquid crystal display panel 2 after one line. Line at a time). The shift register has a horizontal pixel shift clock (HST) supplied to the first flip / flop 26 and is common to all flip / flops 26 connected to the first flip / flop 26 dependently. HCK) is driven when supplied. The driving signal of the first flip / flop 26 is supplied to the switch controller 28, and the switch controller 28 drives the capacitor charging switches S1, S2, S'1, and S'2. The capacitors Qa1, Qa2, Qb1, and Qb2 are driven by the switches S1, S2, S'1, and S'2, and charge the video signal when the first node N1 is connected to the second node N2. On the contrary, when the first node N1 is transferred to the second node N2, the first node N1 discharges to supply the video signal charged toward the buffer 30. At this time, the charging of the capacitors Qa1, Qa2, Qb1, and Qb2 is performed for one pixel time and the discharge is performed for one line time. The buffer 30 is driven when the output control signals A1, A2, B1, and B2 supplied thereto are applied to supply the video signals from the first node N1 to the source lines of the liquid crystal display panel 2. Done.

5 is a timing diagram showing step by step the driving procedure of the multi-scanning apparatus according to the first embodiment of the present invention.

The example of the figure shows a case where a four-line video source is displayed on an LCD of three lines. As shown in FIG. 6, the multi-scan apparatus of the present invention adopts a method in which odd-numbered frames and even-numbered frames compress signals of lines different from each other.

Accordingly, first, the operation of the odd frame will be described step by step. In the odd frame, the display of lines 1 and 2 of the liquid crystal display panel 2 is displayed between the rising edge and the rising edge in the vertical pixel shift clock (VCK), i. In the case of displaying 3.4 lines of the video source, the third and fourth of the horizontal sync signal (Hsync) with one period of the vertical pixel shift clock (VCK) being twice as long as when displaying one or two lines. In the two periods of the first period, only three lines are displayed, in which the three or four lines of the video source should be displayed. In the output control circuit, when the first line of the liquid crystal display panel 2 is displayed, the first output control signal A1 is enabled and the first buffer 30 is driven so that the voltage charged in the first capacitor Qal becomes liquid crystal. It is supplied toward the display panel 2. At this time, only the second switch S2 is driven so that only the second capacitor Qa2 charges the video signal for one pixel time. When displaying two lines, the second output control signal A2 is enabled and the second buffer 30 is driven so that the voltage charged in the second capacitor Qa2 is supplied toward the liquid crystal display panel 2. At this time, the first and third switches S1 and S'1 are driven so that the first and third capacitors Qa1 and Qb1 charge the video signal. When displaying three lines, the third line of the video source in the third and fourth two periods of the horizontal sync signal (Hsync), doubling the time that is normally twice the line, that is, the timing of one period of the vertical pixel shift clock (VCK). Is supplied to the liquid crystal display panel 2. In such a conventional configuration, since the discharge time is long, a leakage current is generated, and flicker appears in three lines on the screen of the liquid crystal display panel 2. In order to overcome such a flicker phenomenon, the first output control signal A1 is enabled during the half cycle of the vertical pixel shift clock VCK in three lines so that the voltage charged in the first capacitor Qa1 is converted into the liquid crystal display pattern 2. ), And during the next half cycle, the third output control signal B1 is enabled, and the voltage charged in the third capacitor Qb1 is discharged toward the liquid crystal display panel 2. This display method solves the flicker problem. 5 to 7 lines are displayed similarly to the display method of 1 to 3 lines.

The display of lines 5 and 6 is displayed in one cycle of the horizontal sync signal Hsync in the same manner as in lines 1 and 2, i.e. conventionally, but in the 7 lines of the liquid crystal display panel 7, In the case of displaying 8 lines, the timing of one cycle of the vertical pixel shift clock (VCK) is doubled so that only 7 lines of the 7 to 8 lines of the video source should be displayed in the two periods of the horizontal sync signal Hsync0. When the fifth line is displayed, the first output control signal A1 is enabled and the first buffer 30 is driven to supply the voltage charged in the first capacitor Qa1 toward the liquid crystal display panel 2. At this time, only the second switch S2 is driven so that only the second capacitor Qa2 charges the video signal When displaying 6 lines, the second output control signal A2 is enabled and the second buffer 30 is activated. Is driven so that the voltage charged in the second capacitor Qa2 The first and third switches S1 and S'1 are driven so that the first and third capacitors Qa1 and Qb1 charge the video signal. During display, the first output control signal A1 is enabled during the half cycle of the vertical pixel shift clock VCK of seven lines to discharge the voltage charged in the first capacitor Qa1 to the liquid crystal display panel 2. During the next half cycle, the third output control signal B1 is enabled so that the voltage charged in the third capacitor Qb1 is discharged toward the liquid crystal display panel 2.

Operation of the even-numbered frame will be described step by step with reference to the timing chart of the even-numbered frame shown in the lower half of FIG. The display of one line and four lines of the liquid crystal display panel 2 is displayed in one cycle of the horizontal synchronization signal Hsync as in the prior art, but two or three lines of the video source are displayed on two lines of the liquid crystal display panel 2. In this case, the timing of one cycle of the vertical pixel shift clock (VCK) is doubled, so that two or three lines of the video source should be displayed in two cycles of the second and third cycles of the horizontal sync signal (Hsync). Only lines are displayed. In the output control circuit, when the first line of the liquid crystal display panel 2 is displayed, the first output control signal A1 is enabled and the first buffer 30 is driven so that the voltage charged in the first capacitor Qa1 becomes liquid crystal. It is supplied toward the display panel 2. At this time, the second and fourth switches S2 and S'2 are driven so that the second and fourth capacitors Qa2 and Qb2 charge the video signal. When displaying two lines, the liquid crystal display panel is divided into two, three, and two periods of the horizontal synchronization signal Hsync by doubling the time of one line, that is, one cycle timing of the vertical pixel shift clock (VCK). ) Will feed two lines of video source. In order to overcome the flicker phenomenon, the second output control signal A2 is enabled during the half cycle of two lines to discharge the voltage charged in the second capacitor Qa2 to the liquid crystal display panel 2, and during the next half cycle. The fourth output control signal B2 is enabled to discharge the voltage charged in the fourth capacitor Qb2 toward the liquid crystal display panel 2. When displaying four lines, the third output control signal B1 is enabled and the second buffer 30 is driven so that the voltage charged in the third capacitor Qb1 is supplied to the liquid crystal display panel 2. At this time, the first switch S1 is driven so that the first capacitor Qa1 charges the video signal. In the display method of 5 to 8 lines, video source data is shrunk and displayed on the liquid crystal display panel 2 in the same manner as 1 to 4 lines. 6 shows the lines of the screen to be displayed.

As described above, the first embodiment of the present invention can overcome the problem of erasing the lines of the screen of the character or the picture by differently deleting the lines of the odd frame and the even frame. It can be minimized.

7 is a timing diagram showing step by step driving levels of the multi-scanning apparatus according to the second embodiment of the present invention. 8 shows a display screen of the second embodiment of the present invention.

In the second embodiment of the present invention, the signal of one of two lines of the video source is not omitted, but an intermediate value (or an average value) is displayed. The example of the figure shows a case where a four-line video source is displayed on an LCD of three lines.

The driving of one line is performed by the second and fourth capacitors Qa2 and Qb2 when the first capacitor Qa1 charged in the previous line is discharged to one line of the liquid crystal display panel 2 during the lifetime. The switches S2 and S'2 are driven and turned on to charge for one pixel time. When displayed on the liquid crystal display panel 2 of two lines of the video source, during the half period of the vertical pixel shift clock VCK, the voltage charged in the second capacitor Qa2 is discharged toward the liquid crystal display panel 2 and then the half period. During this time, the voltage stored in the fourth capacitor Qb2 is discharged toward the liquid crystal display panel 2. At this time, one period of the vertical pixel shift clock VCK is twice as long as one line. During the first half cycle, the first switch S1 is driven to charge three lines of video signals to the first capacitor Qa1, and during the next half cycle, the third switch S'1 is driven to drive the third capacitor Qb1. 4 lines of video signal will be charged. When the next vertical pixel shift clock VCK is entered, the liquid crystal display panel 2 simultaneously displays three lines of video signals charged in the first capacitor Qa1 and four lines of video signals charged in the third capacitor Qb1. The average value is discharged to the liquid crystal display panel 2 while being output to. The video signals of 5 to 8 lines are displayed on the liquid crystal display panel in the same manner as 1 to 4 lines, but the driving of the switches is different. That is, the driving of five lines is performed by the first and third capacitors Qa1 and Qb1 at the moment when the second capacitor Qa2 charged in the four lines is discharged for the line time, and the first and third switches S1 and S'1. Is driven and turned on to charge for one pixel time. When six lines of the video source are displayed on the liquid crystal display panel 2, during the half period of the vertical pixel shift clock VCK, the voltage charged in the first capacitor Qa1 is discharged toward the liquid crystal display panel 2 and then the half period. During this time, the voltage stored in the third capacitor Qb1 is discharged toward the liquid crystal display panel 2. In this case, the seventh line is charged with the second capacitor Qa2 by driving the second switch S2 during the first half cycle and the fourth capacitor S'2 is driven during the next half cycle. The video signal of 8 lines is charged to Qb2. When the next vertical pixel shift clock VCK is input, the liquid crystal display panel 2 simultaneously displays the seven lines of video signals charged in the second capacitor Qa2 and the eight lines of video signals charged in the fourth capacitor Qb2. The average value is discharged to the liquid crystal display panel 2 while being output to.

As described above, the multi-scan apparatus of the present invention may shrink and display a screen when the number of vertical lines of the liquid crystal display panel is smaller than the number of vertical lines of the video source in displaying video signals having different display formats.

The multi-scan apparatus of the present invention can display video signals of different formats with a simple configuration.

The multi-scanning apparatus of the present invention can minimize the difference in resolution of the displayed video signal when the screen is shrunk and displayed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A liquid crystal display panel in which pixel cells are arranged at intersections of a plurality of source lines and a plurality of gate lines, a shift register supplied with a start pulse and a horizontal pixel shift clock, and a video signal stored as the shift register is driven. A sample / hold part which alternately deletes some lines of the video signal at random intervals in the odd and even frames and supplies them to the source lines of the liquid crystal display panel; And a gate driving circuit for driving the gate lines as a pixel shift clock is supplied. The multi-scan apparatus of claim 1, wherein the shift register comprises at least one flip / flop connected in a cascade manner. 2. The apparatus of claim 1, wherein the sample / hold unit comprises: a switch control unit connected to the shift register; first switching means connected to the switch control unit and switching a signal path according to a control unit of the switch control unit; A capacitor connected to a voltage source in common and charged for charging the video signal for one pixel time and discharging for one line time under control of the switching means, and second switching means for supplying the video signal to the liquid crystal display panel. Multi-scan device, characterized in that. The multi-scan apparatus according to claim 1, wherein the sample / hold unit alternately supplies some lines of the video signal to the liquid crystal display panel alternately in half periods during one period of the vertical pixel shift clock. The multi-scan apparatus according to claim 1, wherein the sample / hold unit displays an image on the LCD panel one line after the video signal. The multi-scan apparatus according to claim 1 or 3, wherein the sample / hold unit comprises four switching means to alternately supply some lines of the video signal to the liquid crystal display panel. A liquid crystal display panel in which pixel cells are arranged at intersections of a plurality of source lines and a plurality of gate lines, a shift register to which start pulses and a horizontal pixel shift clock are supplied, and the shift register is connected to the source lines. As driving, a video signal is stored to supply an average value of some lines of the video signal to source lines of the liquid crystal display panel at random intervals, and a vertical pixel shift clock connected to the gate lines. And a gate driving circuit for driving the gate lines in response to the supply thereof. The multi-scan apparatus of claim 7, wherein the sample / hold unit supplies some lines of the video signal to the liquid crystal display panel as an average value during one period of the vertical pixel shift clock. The multi-scan apparatus according to claim 7, wherein the sample / hold unit comprises four switching means for supplying some lines of the video signal to the liquid crystal display panel with an average value.

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