JPH08306919A - Manufacture of field effect type semiconductor device - Google Patents

Abstract

PURPOSE: To manufacture a miniaturized high-speed field-effect semiconductor while suppressing the short-channel effect. CONSTITUTION: Protons 23 are implanted in a polycrystalline Si film 22 wherein boron is diffused from a polycrystalline Si film 13 to be turned into a porous Si film 24 which is oxidized to be an SiO2 film 25. Next, the SiO2 film 25 is removed to ion-implant BF2 <+> 26 into the polycrystalline Si layer 22 and an Si substrate 11 to form a source/drain electrode and a shallow diffused layer 27. Through these procedures, the source/drain electrode may be isolated in self- aligned manner. Furthermore, a contact hole can be eliminated to decrease the contact resistance while narrowing the area of the diffused layer 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect semiconductor device having source / drain electrodes and gate electrodes.

[0002]

2. Description of the Related Art In a conventional method of manufacturing a field effect semiconductor device, after forming a gate electrode, a source / drain diffusion layer, etc., an interlayer insulating film is formed, and a contact hole reaching the source / drain diffusion layer is interlayer insulated. A source / drain electrode is formed on the film or the like and is in contact with the source / drain diffusion layer through the contact hole.

[0003]

However, when the contact holes for the source / drain electrodes are formed, not only the area of the contact holes themselves but also the alignment margin of the contact holes with respect to the gate electrode or the like is taken into consideration. Must be included in. Therefore, it is necessary to increase the area of the source / drain diffusion layer by that amount, and it is difficult to manufacture a fine field effect semiconductor device by the above-mentioned conventional method.

On the other hand, if the area of the contact hole is reduced,
The area of the source / drain diffusion layer can be reduced, but the contact resistance, which is a parasitic resistance, increases. Therefore, according to the above-mentioned conventional method, it is difficult to manufacture a field-effect semiconductor device which is fine but operates at high speed.

[0005]

According to a first aspect of the present invention, there is provided a method of manufacturing a field effect semiconductor device, which comprises a step of forming a gate electrode containing a p-type impurity and having an insulating side wall on a semiconductor substrate. Forming a polycrystalline Si film containing no impurities on the gate electrode, the sidewalls and the semiconductor substrate; and forming a portion of the polycrystalline Si film on the gate electrode from the gate electrode to the p-type impurity. And a step of injecting protons into the polycrystalline Si film to make a portion of the polycrystalline Si film in which the p-type impurities are diffused into a porous Si film. Si oxide film
A step of forming a film, a step of removing the Si oxide film, and a step of forming a portion of the polycrystalline Si film in which the p-type impurities are diffused into the porous Si film, Introducing impurities into the semiconductor substrate to form source / drain electrodes and source / drain diffusion layers.

A method of manufacturing a field effect semiconductor device according to a second aspect is the method of manufacturing a field effect semiconductor device according to the first aspect, wherein the impurities for forming the source / drain diffusion layers are p-type impurities. It is characterized by being.

A method of manufacturing a field effect semiconductor device according to a third aspect is the method of manufacturing a field effect semiconductor device according to the first aspect, wherein the impurity for forming the source / drain diffusion layer is an n-type impurity. It is characterized by being.

[0008]

In the method of manufacturing a field effect type semiconductor device according to the present invention, a portion of the polycrystalline Si film in which p-type impurities are diffused from the gate electrode is formed into a porous Si film and further converted into an oxidized Si film, which is then removed. Therefore, the source electrode and the drain electrode can be separated from each other on the gate electrode in a self-aligned manner. Further, since the side wall can be formed in self alignment with the gate electrode, the source / drain electrode and the gate electrode can be separated from each other in self alignment by the side wall.

Further, since the source / drain electrodes and the source / drain diffusion layers are formed by introducing impurities into the polycrystalline Si film and the semiconductor substrate, the source / drain electrodes are self-aligned on the entire surface of the source / drain diffusion layers. To contact you. Therefore, it is possible to reduce the contact resistance of the source / drain electrode, which is a parasitic resistance, while reducing the area of the source / drain diffusion layer by making the area of the contact hole for the source / drain electrode unnecessary.

Further, since the source / drain electrodes and the source / drain diffusion layers are formed by introducing impurities into the polycrystalline Si film and the semiconductor substrate, the depth is shallower than in the case where impurities are directly introduced into the semiconductor substrate. A source / drain diffusion layer can be formed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of a pMOS transistor having an LDD structure and having ap ⁺ type gate electrode will be described below with reference to FIGS.

In this embodiment, as shown in FIG.
Si is formed on the surface of the element isolation region of the i substrate 11 by the LOCOS method.
After forming an O ₂ film (not shown), 850 ° C., H ₂ / O
The SiO ₂ film 12 as a gate oxide film having a film thickness of 8 nm is formed on the surface of the element active region by pyrogenic oxidation with ₂ = 1.0. And 900 in N ₂ atmosphere
Annealing is performed at 10 ° C. for 10 minutes to improve the quality of the SiO ₂ film 12.

Thereafter, a polycrystalline Si film 13 having a film thickness of 80 nm and containing no impurities is deposited, and the polycrystalline Si film 13 is accelerated with an acceleration energy of 10 keV and a dose amount of 5 × 10 ¹⁵ cm ^−2.
B ⁺ 14 is ion-implanted into the film 13 to form a polycrystalline Si film 13
Be a p ⁺ type. The acceleration energy in the ion implantation at this time is a condition that B ⁺ 14 does not penetrate the SiO ₂ film 12, and the dose amount is a condition that the polycrystalline Si film 13 is degenerated.

Next, as shown in FIG. 1B, polycrystalline Si
A resist 15 is processed into a gate electrode pattern on the film 13, and the resist 15 is used as a mask to form a polycrystalline Si film 13
Anisotropically etch. Then, using the resist 15 as a mask, an acceleration energy of 20 keV and 2.0 × 1
BF ₂ ⁺ 16 is ion-implanted into the Si substrate 11 with a dose amount of 0 ¹³ cm ⁻² to form the p ⁻ type diffusion layer 17 for the LDD structure.

After that, the resist 15 is ashed and peeled off, and H ₂ SO ₄ + H ₂ O is added in order to remove metal ions.
₂ Wash with solution for 10 minutes. Further, in order to remove various particles such as dust and organic substances, NH ₄ OH
Washing with + H ₂ O ₂ solution and HCl + H ₂ O ₂ solution for 10 minutes each.

Next, as shown in FIG. 1C, atmospheric pressure CVD is performed.
The insulating film such as the SiO ₂ film 21 by the method of 100 to 120 n
Then, the entire surface of the SiO ₂ film 21 is anisotropically etched back to form side walls of the SiO ₂ film 21 on the side surfaces of the polycrystalline Si film 13 or the like.

Next, as shown in FIG. 1D, the film thickness is 80
A polycrystalline Si film 22 containing no impurities is deposited. Then, annealing is performed at 900 ° C. for 1 hour in an N ₂ atmosphere to diffuse the boron in the polycrystalline Si film 13 into the polycrystalline Si film 22. Only the upper portion and a portion slightly on the SiO ₂ film 21 side from this portion are made p ⁺ -type in a self-aligning manner.

Next, as shown in FIG. 2A, polycrystalline Si
Although the protons 23 are injected into the entire surface of the film 22, the protons 23 have a function of changing the p-type polycrystalline Si film into a porous Si film. Only the upper portion and a portion on the SiO ₂ film 21 side from this portion are changed to the porous Si film 24.

After that, oxidation is performed. Porous Si has an oxidation rate 10 to 20 times higher than that of single crystal Si, and the oxidation rate is faster than that of polycrystalline Si. Therefore, by adjusting the oxidation time, the polycrystalline Si film 22 is not substantially oxidized and only the porous Si film 24 is changed to the SiO ₂ film 25.

Next, as shown in FIG. 2B, the SiO ₂ film 25 is removed with dilute hydrofluoric acid to separate the polycrystalline Si films 22 on both sides of the polycrystalline Si film 13. The SiO ₂ film 2
1, the polycrystalline Si film 22 is also separated from the polycrystalline Si film 13 in a self-aligned manner.

Next, as shown in FIG. 2C, 30 keV
Source / drain with a polycrystalline Si film 22 and the Si substrate 11 at a dose of acceleration energy and 4 × 10 ¹⁵ cm ^-2 by ion implantation of BF ₂ ⁺ 26, the polycrystalline Si film 22 in the p ⁺ -type The p ⁺ -type diffusion layer 27 as the diffusion layer is set to S
It is formed on the i-substrate 11. After that, the polycrystalline Si film 22 is processed into a pattern of source / drain electrodes, and further, through known steps, the pMOS transistor is completed.

In the above embodiment, the polycrystalline Si film 1 is used.
B ⁺ 14 is ion-implanted in order to make 3 into the p ⁺ -type, and BF ₂ ⁺ 16 is ion-implanted while leaving the resist 15 remaining to form a diffusion layer 17, and a SiO ₂ film 21 is formed by a low pressure CVD method. The side wall of the crystalline Si film 13 is formed.

However, in order to make the polycrystalline Si film 13 into p ⁺ type, BF ₂ ⁺ is ion-implanted, the resist 15 is peeled off, and then BF ₂ ⁺ 16 is ion-implanted to form the diffusion layer 17, and the pressure is reduced. The side wall of the polycrystalline Si film 13 may be formed by an insulating film other than the SiO ₂ film 21 formed by the CVD method.

In addition, although the present invention is applied to the manufacture of the pMOS transistor in the above embodiments, for example, B
As ⁺ is ion-implanted at an acceleration energy of 25 keV instead of F ₂ ⁺ 16 and a dose amount of 1.0 × 10 ¹⁴ cm ^-2 to form an n ⁻ -type diffusion layer, and 20 keV is formed instead of BF ₂ ⁺ 26. As ⁺ is ion-implanted at an acceleration energy of 3 × 10 ¹⁵ cm ^-2 and a polycrystalline Si film 22 is made into an n ⁺ -type and an n ⁺ -type diffusion layer is formed.
An OS transistor can also be formed. Furthermore, MO
The present invention can be applied to the manufacture of field effect semiconductor devices other than S transistors.

[0025]

According to the method of manufacturing a field effect semiconductor device of the present invention, the source electrode, the drain electrode, and the source / drain electrode
Since the drain electrode and the gate electrode can be separated from each other in a self-aligned manner and the area of the source / drain diffusion layer can be reduced, a fine field effect semiconductor device can be manufactured.

Further, since the shallow source / drain diffusion layer can be formed, it is possible to manufacture a field effect type semiconductor device in which the short channel effect is suppressed although it is fine. Further, since the contact resistance of the source / drain electrodes, which is a parasitic resistance, can be reduced, it is possible to manufacture a field-effect semiconductor device which is fine but operates at high speed.

[Brief description of drawings]

FIG. 1 is a side sectional view showing the first half of one embodiment of the present invention for manufacturing a pMOS transistor in process order.

FIG. 2 is a side sectional view showing the latter half of one embodiment in process order.

[Explanation of symbols]

11 Si substrate 13 Polycrystalline Si film 14 B ⁺ 21 SiO ₂ film 22 Polycrystalline Si film 23 Proton 24 Porous Si film 25 SiO ₂ film 26 BF ₂ ⁺ 27 Diffusion layer

Claims (3)

[Claims] 1. A step of forming, on a semiconductor substrate, a gate electrode containing p-type impurities and having insulating side walls, and a polycrystalline Si film containing no impurities is formed on the gate electrodes, the side walls and the semiconductor. A step of forming on the substrate, a step of diffusing the p-type impurity from the gate electrode to a portion of the polycrystalline Si film on the gate electrode, and a step of implanting protons into the polycrystalline Si film, A portion of the polycrystalline Si film in which the p-type impurity is diffused is made of porous S.
an i film, a step of converting the porous Si film into a Si oxide film, a step of removing the Si oxide film, and a portion of the polycrystalline Si film in which the p-type impurity is diffused. After forming the porous Si film, the polycrystalline Si
A step of introducing impurities into the film and the semiconductor substrate to form a source / drain electrode and a source / drain diffusion layer. 2. The method for manufacturing a field effect semiconductor device according to claim 1, wherein the impurities for forming the source / drain diffusion layers are p-type impurities. 3. The method for manufacturing a field effect semiconductor device according to claim 1, wherein the impurity for forming the source / drain diffusion layer is an n-type impurity.