JPH083006Y2 - 半導体装置の実装構造 - Google Patents

半導体装置の実装構造

Info

Publication number
JPH083006Y2
JPH083006Y2 JP1990025766U JP2576690U JPH083006Y2 JP H083006 Y2 JPH083006 Y2 JP H083006Y2 JP 1990025766 U JP1990025766 U JP 1990025766U JP 2576690 U JP2576690 U JP 2576690U JP H083006 Y2 JPH083006 Y2 JP H083006Y2
Authority
JP
Japan
Prior art keywords
chip
chips
mounting structure
circuit board
pressing plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1990025766U
Other languages
English (en)
Japanese (ja)
Other versions
JPH03116034U (en, 2012
Inventor
稔 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP1990025766U priority Critical patent/JPH083006Y2/ja
Publication of JPH03116034U publication Critical patent/JPH03116034U/ja
Application granted granted Critical
Publication of JPH083006Y2 publication Critical patent/JPH083006Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)
JP1990025766U 1990-03-14 1990-03-14 半導体装置の実装構造 Expired - Fee Related JPH083006Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990025766U JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990025766U JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Publications (2)

Publication Number Publication Date
JPH03116034U JPH03116034U (en, 2012) 1991-12-02
JPH083006Y2 true JPH083006Y2 (ja) 1996-01-29

Family

ID=31528689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990025766U Expired - Fee Related JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Country Status (1)

Country Link
JP (1) JPH083006Y2 (en, 2012)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008029802A (ja) * 2006-06-29 2008-02-14 Sadao Kiyomiya 遊技媒体数量表示システム、並びに遊技媒体数量測定装置及び同方法

Also Published As

Publication number Publication date
JPH03116034U (en, 2012) 1991-12-02

Similar Documents

Publication Publication Date Title
US5631191A (en) Method for connecting a die to electrically conductive traces on a flexible lead-frame
TW498516B (en) Manufacturing method for semiconductor package with heat sink
KR100762208B1 (ko) 반도체 장치 및 반도체 장치의 제조 방법과 반도체 장치의 실장 방법
JP4757398B2 (ja) 半導体装置の製造方法
JP2547895B2 (ja) 半導体装置の実装方法
JP6931311B2 (ja) 異方性導電膜またはペーストを用いて高さの異なる複数のチップを可撓性基板上に同時に接着する方法
JPH11307592A (ja) 半導体装置およびその製造方法
JPH07335695A (ja) Ｉｃチップモジュール組立体及びそれに用いられる付勢部材
JPH083006Y2 (ja) 半導体装置の実装構造
JPH02278740A (ja) 半導体装置のパッケージング方法
TW480686B (en) Intersecting stacked type dual die package structure and manufacturing process
JPH10173007A (ja) ベアチップ搭載装置
CN101853817A (zh) 封装结构及其制造方法
JPH03241847A (ja) 半導体装置の実装構造
JP3022910B2 (ja) 半導体装置の製造方法
JP3594120B2 (ja) 半導体装置の製造方法及びボンディング用加圧治具
KR200155176Y1 (ko) 반도체 패키지
JP2001189553A (ja) 基板の接合装置及びその装置を用いた基板の接合方法
JP3487991B2 (ja) 半導体装置
JP4002220B2 (ja) 半導体装置の製造方法
JP2599509B2 (ja) 半導体装置の実装構造
JPH056919A (ja) フリツプチツプボンデイング方法
JP2797732B2 (ja) Ｉｃパッケージ
JPH0642502B2 (ja) 半導体装置の製造方法および装置
KR940004787A (ko) 반도체 패키지 제조방법

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees