JPH08235849A - Memory access method and memory device - Google Patents

Abstract

PURPOSE: To increase the speed of input output and to reduce the amount of power consumption by writing each memory with the period which is n times the period T of input data and reading each memory with the period which is n times the period t of output data. CONSTITUTION: In first to third single port SRAM 23a to 23c, a series of operations constituted by precharge, data reading and data writing operations are executed whenever corresponding address data ADR 1 to ADR 3 are inputted, i.e., at a period 3T. Therefore, in the port SRAM 23a, every two other data are written as 12, 15... and in the port SRAM 23b, every two other data are written as 13, 16.... Note that these data are successively read in the order as 12, 13, 14... by reading signals ϕ2 , ϕ5 and ϕ8 from these SRAMs. The read data are latched by any one of corresponding latching circuits 23a to 23c during a fall of a reading signal, selected by an output selector circuit 21b and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method and a memory device suitable for implementing the same, and more particularly to a memory access method and a memory device that can be used for a data delay circuit or the like in a video system. .

[0002]

2. Description of the Related Art For example, when it is desired to delay data in a video system or the like, this can be achieved by an operation of accessing the memory by writing the data in the memory once and then reading the data. This is a single port static ram (S
When using RAM), there is a method described below with reference to FIGS. 8 and 9. In response to the reset signal RT, the address counter 11 counts up and outputs address data AD to the address decoder 13. The address decoder 13 decodes the address data AD and sequentially inputs the result to the SRAM 15 at a cycle of 2T. The precharge signal φ ₁ , the read signal φ _2, and the write signal φ ₃ are input to the SRAM 15 in this order during 2T. The data currently written in the SRAM 15 is read according to the read signal φ ₂ (for example, t _{1 in} FIG. 9), and the next read data is sent to the address where the data has been read according to the write signal φ _3. It is written (for example, t _{2 in} FIG. 9). In this method, data is read and written within one cycle. Moreover, the data is delayed in the memory for a time corresponding to the cycle of the reset signal. There is also a method of delaying data using a dual port SRAM. Dual port SR
Read address data is given to AM at cycle T and this SRA
Reading data from M and writing write address data to this SRAM at a cycle T and writing data to this SRAM are performed such that read and write operations for the same address are deviated in time (this SRA
This is a method of delaying the data by making a time shift depending on how much the data is delayed by M).

[0003]

By the way, there is a demand for an image memory such as a video memory which has a large capacity and operates at a high speed. On the other hand, for example, (1).
The problem is that it becomes difficult to operate the memory at high speed because the wiring capacity and wiring resistance increase as the device becomes finer due to the increase in capacity, and (2) even if high-speed operation can be realized. There arises a problem that power consumption increases. In such a case, any of the conventional methods described above is a method of accessing the memory at the same cycle as the cycle of the input data, that is, a method that requires high-speed access to the memory. It is greatly affected by the problems of (2) and.

[0004]

Therefore, according to the first invention of this application, in a memory access method of writing data to a memory at a cycle T and reading data from the memory at a cycle t, n is used as a memory. Number of memories, input data of the cycle T is input to the n memories in parallel, and a data write signal is sequentially applied to the n memories at the cycle nT; On the other hand, a process of sequentially applying the data read signal at the cycle nt is included. However, n is an arbitrary integer of 2 or more. Further, there may be a case where t = T.

Further, according to the memory device of the second invention of this application, in the memory device for inputting / outputting data to / from the memory at the cycle T, the n number of memories to which the input data of the cycle T is inputted in parallel. A means for sequentially applying a data write signal to the n memories at a cycle nT, a means for sequentially applying a data read signal to the n memories at a cycle nT, and an address data of the memory. It is characterized by comprising address data generating means for sequentially generating and addressing means for applying the address data to each of the n memories by shifting the address data by time T for each generated address data without duplication. . However, n is an arbitrary integer of 2 or more.

Further, in the second aspect of the invention, the data may be read and written separately. Therefore, in a memory device that writes data to a memory at a cycle T and reads data from the memory at a cycle t, input data of a cycle T is input in parallel.
Number of memories, means for sequentially applying a data write signal to the n memories at a cycle nT, and means for sequentially applying a data read signal to the n memories at a cycle nt,
Write address data generation means for sequentially generating write address data of the memory, and write address designation for applying the write address data to the n memories without duplication by shifting the write address data by time T for each of the generated write address data. Means and a read address data generating means for sequentially generating read address data of the memory, and a read operation for applying the read address data to the n memories by shifting the read address data by time t for each of the generated read address data. A memory device comprising addressing means is also claimed. However, n is an arbitrary integer of 2 or more. Further, there may be a case where t = T.

[0007]

According to the structure of the first invention, the input data of the cycle T is allocated to n memories and sequentially written in these memories. Further, data is sequentially read from the n memories and becomes output data of a cycle t (t = T may occur). Then, the write operation in the memory is achieved by accessing each memory at a cycle n times as long as the cycle T of the input data (that is, at a speed of 1 / n when accessing at the cycle T). Further, the read operation is achieved by accessing each memory at a cycle n times as long as the cycle t of the output data (that is, at a speed of 1 / n when accessing at the cycle t).

Further, according to the structure of the second invention, the first invention can be easily implemented. Further, the address designation of n memories (when writing and reading data separately, designation of write address and read address of n memories) can be simplified.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the memory access method and the memory device of this application will be described below with reference to the drawings. However, all the drawings are shown schematically so that these inventions can be understood. Further, in each drawing used for the explanation, the same numbers are given to the similar components,
The overlapping description may be omitted.

[0010] 1. First Embodiment FIGS. 1 and 2 are timing charts when the access method of the first invention is implemented by using three single-port SRAMs 23a to 23c as n memories, and FIG. 3 implements this access method. Suitable memory device 20
FIG. 3 is a diagram showing the configuration of FIG. However, it should be understood that FIG. 1 and FIG. 2 are the divided timing charts of successive timing charts. Further, the signals indicated by symbols such as C, IN, and RS shown in the timing chart represent the respective signals described in Appendix 1.

First, the configuration of the memory device 20 will be described mainly with reference to FIG. The memory device 20 includes an input / output unit 21 for inputting input data IN having a cycle T and outputting output data 0UT, and an input data I having a cycle T.
First to third three single-port SRAMs 23a to 23c to which N is input in parallel, and data are sequentially supplied to these first to third single-port SRAMs 23a to 23c at a cycle nT (n = 3 in this case). Means 25 for applying a write signal, and these first to third single-port SRAMs 2
3a to 23c, a means 27 for sequentially applying a data read signal at a cycle nT, an address data generating means 29 for sequentially generating address data of the memory, and a time interval for generating the address data for each generated address data. First to third single-port SRAM 23a by shifting by T
23c and addressing means 31 for applying the same to 23c. Note that in FIG. 3, 23aa, 23ba, and 23ca are respectively the first to third SRAMs 23a to 2a.
3 shows a latch circuit for latching the data output from 3c. 33 is a corresponding single port SR
Precharge signals φ ₁ and φ ₄ for AMs 23a to 23c
Alternatively, a means for applying φ ₇ is shown.

Here, the input / output unit 21 takes in the input data IN of the cycle T and receives the first to third single ports S.
Input buffer 2 sent in parallel to each of RAMs 23a-23c
1a and first to third single port SRAMs 23a to
Output data OU by selecting the data read from 23c
And an output select circuit 21b for outputting T. The input buffer 21a is a known one, and
The output select circuit 21b can be composed of, for example, a known one having a select counter.

The first to third single port SRAs
Each of M23a to 23c is composed of a single-port SRAM array having a capacity of (h / n) × m bits. However, h is an arbitrary positive integer determined according to the buffer capacity (preferably an integer divisible by n), n is the same number as the number of memories n, and in this embodiment, 3 and m are arbitrary determined by the constituent bits of one word. Is a positive integer.

Means 25 for applying a data write signal
In this case, a data write signal φ ₃ having a period of nT and a pulse width of, for example, T is supplied to the first single-port SRAM 23a, and a data write signal φ having a period of nT and a pulse width of, for example, T is supplied to the second single-port SRAM 23b.
₆ for the third single-port SRAM 23c with a period nT and a pulse width of T, for example, a data write signal φ ₉
Are applied so that the signals φ ₃ , φ ₆ and φ ₉ are out of phase with each other by a time T. Since such a means 25 can be realized by a known pulse generation technique, its details are omitted.

A means 27 for applying a data read signal.
In this case, the data read signal φ having a pulse width of, for example, T and a cycle of nT with respect to the first single-port SRAM 23a.
₂ , a data read signal φ ₅ having a pulse width of, for example, T at a cycle nT to the second single-port SRAM 23b, and a data read signal φ ₈ having a pulse width of, for example, T at a cycle nT for the third single-port SRAM 23c. , The signals φ ₂ , φ _5, and φ ₈ are applied so that their phases are shifted by the time T. Of course, these data read signals φ ₂ , φ ₅ and φ ₈ are applied faster than the corresponding data write signals φ ₃ , φ ₆ and φ _{9 by the} time T. Since such a means 27 can be realized by a known pulse generation technique, details thereof will be omitted.

Means 3 for applying a precharge signal
3 is the first single-port SRAM 23a in this case.
In contrast, the first precharge signal φ ₁ having a pulse width of, for example, T at the cycle nT is supplied to the second single-port SRAM 23b.
In contrast, the second precharge signal φ ₄ having a pulse width of, for example, T at the cycle nT is supplied to the third single-port SRAM 23c.
On the other hand, a third precharge signal φ ₇ having a pulse width of, for example, T at a period nT is applied so that the phases thereof are shifted by the time T between these signals φ ₁ , φ ₄ and φ ₇ . Of course, these first to third precharge signals φ ₁ ,
φ ₄ and φ ₇ are set to the corresponding data read signals φ ₂ and φ
₅ and φ ₈ are applied faster than time T. Since such means 33 can be realized by a known pulse generation technique, details thereof will be omitted.

Therefore, in the case of the memory device 20 of the first embodiment, the first precharge signal φ is supplied to the first single-port SRAM 23a every nT (3T in this case). ₁ , data read signal φ ₂
And the data write signal φ ₃ can be applied in this order for each T time, and the second precharge signal φ ₃ can be applied to the second single-port SRAM 23b every nT time.
₄ , data read signal φ ₅ and data write signal φ ₆
3rd single port SR
For the AM 23b, the third value is set every nT time.
Precharge signal φ ₇ , data read signal φ ₈ and data write signal φ ₉ can be applied in this order for T time. The reason why the precharge signal, the data read signal, and the data write signal are applied every T time is mainly because the timing with the input data of the cycle T is easily taken. The application time of each of the precharge signal, the data read signal, and the data write signal is not limited to T, of course.

Further, in this embodiment, the address data generating means 29 is an address counter which is initialized by the reset signal RS and performs a cant-up operation until the next reset signal is input to output the address data ADR. It is composed of.

In this embodiment, the address designating means 31 uses the address data ADR generated by the address generating means 19 as it is as the first address data ADR1.
As the first address data AD
Second address data ADR2 obtained by delaying R1 by time T
And third address data ADR delayed by 2T
It is also composed of an address decoder which outputs 3 as well. Such an address designating means 31 can be constituted by, for example, a group including a D-type flip-flop group 31a using two stages of arrays each having the same number of D-type flip-flops as the number of bits forming the address data in parallel. The first address data ADR1 (that is, ADR itself) is input to the first stage of the flip-flop group 31a having the two-stage configuration, and the output of the first stage is used as the second address data ADR.
2 and the output of the second stage is the third address data ADR
By setting 3, the first to third address data AD
R1 to ADR3 are obtained.

Next, a method of accessing the memory in the memory device 20 will be described. First, the address counter 29 responds to the reset signal RS (see FIG. 1) until the next reset signal arrives.
The R is sequentially output to the addressing means 31 in a cycle of 3T. As described above, the address designating means 31 is the first to third address data ADR1 to ADR3 that designate the same address on the basis of the address data ADR.
The first to third address data ADR1 to ADR3 including the delayed second address data ADR2 and the third address data ADR3 are output. Therefore,
The first address data ADR1 is applied to the first single-port SRAM 23a in the cycle 3T, and the first address data AD is applied to the second single-port SRAM 23b.
The second address data ADR2, which is out of phase with the time T with respect to R1, is applied in the cycle 3T, and the third address, which is out of phase with the first address data ADR1 by the time 2T, is applied to the third single-port SRAM 23c. Data A
DR3 is applied with a period of 3T. Further, in the state where the first to third address data ADR1 to ADR3 are applied to the single port SRAMs 23a to 23c in this way, the first single port SRAM 23a is
Precharge signal φ ₁ , data read signal φ ₂ and data write signal φ ₃ are sequentially applied. Further, the precharge signal φ ₄ , the data read signal φ _5, and the data write signal φ ₆ are sequentially supplied to the second single-port SRAM 23b because of the phase delay by the time T compared to the first single-port SRAM 23a. Applied to. Furthermore, the third
The single-port SRAM 23c has a precharge signal φ ₇ and a data read-out signal φ ₈ due to a phase delay of 2T compared to the first single-port SRAM 23a.
And the data write signal φ ₉ is sequentially applied. Also,
Input data IN is input in parallel to the data input terminals of each of the first to third single port SRAMs 23a to 23c.

Therefore, in each of the first to third single port SRAMs 23a to 23c, the precharge operation,
A series of operations including a data read operation and a data write operation corresponds to corresponding address data ADR1 to ADR1.
Every time ADR3 is input, that is, in this case, cycle 3T
Then, it will be done. This will be described in more detail with reference to the examples of FIGS. 1 and 2.

The precharge operation of the first single-port SRAM 23a is performed from the rising of the first precharge signal φ ₁ (t _{1 in} FIG. ₁ ). Address data A
The data currently stored at the address designated by DR1 is read from the rising edge of the read signal φ ₂ applied after a time T from the first precharge signal φ ₁ (t _{2 in} FIG. 1). Further, the data I is stored in the address specified by the address data ADR1 in the SRAM 23a.
2 is written from the rising edge of the write signal φ ₃ applied with a time delay of 2T from the first precharge signal φ ₁ (t _{3 in} FIG. 1). Also, a second single port SRAM
23b, the first single-port SRAM2 described above.
A series of operations similar to 3a is performed by the first single port SR.
Compared to the case of the AM 23a, the time is shifted by the time T. In the third single-port SRAM 23c, the above-mentioned first
A series of operations similar to those of the single port SRAM 23a described above is performed with a time difference of 2T compared to the case of the first single port SRAM 23a. Therefore, I2, I5, ..., I are stored in the first single-port SRAM 23a.
Data is sequentially written every other two such as 14, ..., And I is written in the second single-port SRAM 23b.
, I6, ..., I12 ,.
In the RAM 23c, data is written in sequence every two, such as I4, I7, ..., I13 ,. However, even if the data is written in the three SRAMs in an irregular manner, the read signals φ ₂ , φ are read from these SRAMs.
_{By 5} and φ ₈ , these data will later be converted to I2, I
3, I4, ... Are read out in order (for example, time t _{A to} t _{C in} FIG. 2). Thus read data is in this case (see latch output LO _a ~LO _c in FIG. 2) that latch circuit 23aa~23ca noise or are latched in corresponding to the falling edge of the read signal. After that, the output OU selected by the output selector circuit 21b is selected.
It is output as T (see OUT in FIG. 2).

According to the memory access method of the first embodiment, the first to third single port SRAMs 23a ...
Although 23c is operated at a cycle three times the cycle of the input data, that is, one-third the speed of the input data, data can be input / output at the original speed (speed of cycle T). Therefore, the memory access speed can be increased and the power consumption can be reduced. Further, in the memory device of the first embodiment, the memory access method of the first invention can be easily implemented. Moreover, since the first to third address data ADR1 to ADR3 can be generated by a simple circuit including one address counter and a D-type flip-flop group without using three address counters, the circuit cost can be reduced. Can be achieved.

2. Second Embodiment FIG. 4 to FIG. 6 are timing charts when the access method of the first invention is implemented using two dual port SRAMs 23x and 23y as n memories, and FIG. It is a figure showing the composition of memory device 40 suitable for doing. However, it should be understood that FIG. 4 to FIG. 6 are diagrams showing continuous timing charts by dividing them. In addition, C shown in the timing chart,
Among the signals represented by symbols such as IN and RS, the signals not described in Appendix 1 represent the signals described in Appendix 2.

First, regarding the structure of the memory device 40,
Differences from the memory device 20 shown in the figure will be described mainly with reference to FIG. 7.

Each of the first dual-port SRAM 23x and the second dual-port SRAM 23y is a known dual-port SRAM, and is (h / n) × m.
It is composed of a dual port SRAM array having a bit capacity. However, h is an arbitrary positive integer determined according to the buffer capacity (preferably an integer divisible by n), n is the same number as the number of memories n, and in this embodiment, 2 and m are arbitrary determined by the constituent bits of one word. Is a positive integer. These first and second dual port SRAMs 23x, 2
Input data IN having a cycle T is input in parallel to the respective data input terminals of 3y.

The means 41 for applying the data write signal in the second embodiment is the first dual port SRAM.
23x, a data write signal φ _B with a pulse width of, for example, T at a cycle of nT (2T in this case), and a data write signal φ _D with a pulse width of, for example, T at a cycle of nT for the second dual port SRAM 23y. The signals are applied such that the signals φ _B and φ _D are out of phase with each other by a time T. Since such a means 41 can be realized by a known pulse generation technique, details thereof will be omitted.

Further, the means 43 for applying the data read signal in the second embodiment is the first dual port SRAM.
23x, a data read signal θ _B having a period nt (2t in this case) and a pulse width of, for example, t, and a second dual-port SRAM 23y having a period nT and a pulse width of, for example, t.
The data read signal θ _D is applied such that the phase is shifted by the time t between these signals θ _B and θ _D. Since such means 43 can be realized by a known pulse generation technique, details thereof will be omitted.

Note that the period of the data read signal is set to t with respect to the period T of the data write signal because this second embodiment uses the dual port SRAM as the memory. This is because it means that the timing can be arbitrary (the same applies to the following write / read precharge signal). Therefore, it is of course possible to have the case of t = T (the same applies to the following write / read precharge signal).

Further, in this case, the means for applying the precharge signal comprises two means, a means 45 for applying the write precharge signal and a means 47 for applying the read precharge signal. The means 45 for applying the write precharge signal supplies the first dual-port SRAM 23x with the first write-precharge signal φ _A having a period nT and a pulse width of, for example, T with respect to the first dual-port SRAM 23x.
A second write precharge signal φ _C having a pulse width of, for example, T at a cycle of nT with respect to y is applied such that the phase shifts by a time T between these signals φ _A and φ _C. Naturally, these first and second write precharge signals φ _A and φ _C are changed to the corresponding data write signal φ _B.
And φ _D are applied faster than time T. Also, means 4 for applying a read precharge signal
Reference numeral 7 denotes a first read precharge signal θ _A having a period nt and a pulse width of, for example, t for the first dual-port SRAM 23x, and a second read precharge signal θ _A having a period nt and a pulse width of, for example, t for the second dual-port SRAM 23y. The read precharge signal θ _C is applied such that the phase is shifted by the time t between these signals θ _A and θ _C.
Of course, these first and second read precharge signals θ _A and θ _C are applied earlier than the corresponding data read signals θ _B and θ _D by time t.
Since each of such means 45 and 47 can be realized by a known pulse generation technique, details thereof will be omitted.

Therefore, in the case of the memory device 40 of the second embodiment, when performing the data write operation, the next nT is successively applied to the first dual port SRAM 23x.
The first write precharge signal φ _A and the data write signal φ _B can be applied in this order for T time each time (2T in this case), and the second dual port SRAM 23y can be applied.
On the other hand, the second write precharge signal φ _C and the data write signal φ _D can be applied in this order for each T time within each successive nT time. Further, when the data read operation is performed, the first read precharge signal θ _A and the data read signal θ _B are supplied to the first dual-port SRAM 23x at intervals of nt (2t in this case). Second dual port SRA that can be applied in this order by time
With respect to M23y, the second read precharge signal θ _C and the data read signal θ _D are set to t at every nt time.
It can be applied for each time in this order.

Further, in the second embodiment, since the data writing and the data reading can be performed separately, the write address data generating means 29x, the write address designating means 31x, and the read address data generating means 31x.
And read address designating means 31y.

Write address data generating means 29x
In this embodiment, the write address data WA is initialized by the write reset signal WRS and a cant up operation is performed until the next reset signal is input.
It is composed of an address counter that outputs DR.

Further, write address designating means 31x
In the case of this embodiment, is the write address generation means 29.
The write address data WADR generated by x is directly output as the first write address data WADR1, and the first write address data WADR is output.
It is composed of an address decoder which also outputs the second write address data WADR2 obtained by delaying DR1 by time T. Such a write address designating means 31x is
For example, it can be configured by including the same number of D-type flip-flop groups 31z as the number of bits forming the address data. The output of the flip-flop group 31z may be used as the second write address data WADR2.

Further, the read address designating means 31y.
In this embodiment, read address generating means 29
The read address data RADR generated by y is directly output as the first read address data RADR1, and the first read address data RADR is also output.
It is composed of an address decoder which also outputs the second read address data RADR2 obtained by delaying DR1 by time t. Such a read address designating means 31y is
For example, like the write address designating means 31x, the write address designating means 31x can be configured by including the same number of D-type flip-flop groups 31z as the number of bits forming the address data.

Next, a method of accessing the memory in the memory device 40 will be described. First, the data write operation will be described. Write reset signal WRS
Write address counter 29x according to (see FIG. 4)
Outputs the write address data WADR to the write address designating means 31x in a cycle of 2T until the next reset signal arrives. As described above, the write address designating means 31x designates the same address as the first and second write address data WADR1, based on the write address data WADR,
WADR2, but the first and second write address data WADR1, which are out of phase with each other by time T,
Output WADR2. Therefore, the first write address data WADR1 is applied to the first dual-port SRAM 23x in the cycle 2T, and the first write address data WDR is applied to the second dual-port SRAM 23y.
The second write address data WADR2, which is out of phase with the time T with respect to ADR1, is applied in a cycle 2T. In addition, the first and second write address data WA are stored in the dual port SRAMs 23x and 23y in this manner.
While DR1 and WADR2 are being applied, the first write precharge signal φ _A and the data write signal φ _B are sequentially applied to the first dual port SRAM 23x. In addition, a second dual port SRAM
The second write precharge signal φ _C and the data write signal φ _D are sequentially applied to the circuit 23y in a relationship that the phase is delayed by the time T as compared with the second dual port SRAM 23x. Also, the first and second dual port SRs
Input data IN is input in parallel to the data input terminals of the AMs 23x and 23y.

Therefore, in each of the first and second dual-port SRAMs 23x and 23y, a series of operations consisting of the write precharge operation and the data write operation corresponds to the corresponding write address data WADR1 and WADR1.
Every time WADR2 is input, that is, in this case, cycle 2
It will be done at T. As a result, in the first dual-port SRAM 23x, I1, I3, ..., I
Every other data is sequentially written such as 17, ..., And I is written in the second dual port SRAM 23y.
2, I4, ..., I16, ... Every other data is sequentially written (WD in FIGS. 4 to 6).
_23x , WD _23y waveform chart).

On the other hand, the data read operation is performed as follows. The read address counter 29y responds to the read reset signal RRS (see FIG. 4) until the next reset signal arrives.
The R is sequentially output to the read address designating means 31y in a cycle 2t. As described above, the read address specifying means 31y is the first and second read address data RADR1 and RADR2 that specify the same address based on the read address data RADR, but the phases are shifted from each other by the time t. The first and second read address data RADR1 and RADR2 are output. Therefore, the first dual-port SRAM 23x
The first read address data RADR1 is in cycle 2
The second read address data RA applied at t and shifted in phase from the first read address data RADR1 by the time t with respect to the second dual port SRAM 23y.
DR2 is applied with a period of 2t. In addition, the first and second read address data RADR1 and RADR2 are stored in the dual port SRAMs 23x and 23y in this manner.
Is applied to the first dual-port SRAM 23x, the first read precharge signal θ
_A and the data read signal θ _B are sequentially applied. Furthermore, the second read precharge signal θ _C and the data read signal θ _D are sequentially applied to the second dual-port SRAM 23 y in a phase delay by the time t as compared with the second dual-port SRAM 23 x. It

Therefore, in each of the first and second dual port SRAMs 23x and 23y, a series of operations consisting of the read precharge operation and the data read operation corresponds to the corresponding read address data RADR1 and RADR1.
Every time RADR2 is input, that is, in this case, cycle 2
will be performed at t. As a result, from the first dual port SRAM 23x, I1, I3, ...
Every other data is sequentially read out, such as I17, ..., And every other data is sequentially read from the second dual-port SRAM 23y, such as I2, I4 ,. Read out (O in FIGS. 5 and 6)
_23x , O _23y waveform chart). In this case, the data read in this way is latched in either of the corresponding latch circuits 23xa and 23ya at the fall of the corresponding read signals θ _B and θ _D (latch output LO _{a in} FIG. 2). , L
See O _b). After that, it is selected by the output selector circuit 21b and is output as the output OUT (O in FIGS. 5 and 6).
UT).

According to the memory access method of the second embodiment, the first and second dual port SRAM 23 are provided.
Although x and 23y are operated at a cycle 2T that is twice the cycle T of the input data, that is, a speed that is half the speed of the input data, the data is stored at the original speed (speed of the cycle T). Can be entered in. Further, the first and second dual-port SRAMs 23x and 23y are provided with a cycle 2t which is twice the cycle t of the output data, that is, a speed of the output data is 2
Despite operating at one-half speed, data can be output from the memory at the original speed (speed of cycle t). Therefore, the memory access speed can be increased and the power consumption can be reduced. Further, in the memory device of the second embodiment, the memory access method of the first invention can be easily implemented. Moreover, the first and second write address data WADR1 and WADR2 can be generated by a simple circuit including one address counter and a D-type flip-flop group without using two address counters. And generation of the second read address data RADR1 and RADR2,
Since a simple circuit including one address counter and a D-type flip-flop group can be used without using two address counters, the circuit cost can be reduced.

Although the embodiments of the first and second inventions have been described above, the inventions are not limited to the above-mentioned embodiments. For example, in the above-described first embodiment, the example in which the number of memories is 3 is described, and in the second embodiment, the example in which the number of memories is 2 is described. However, the number n of memories depends on the design. It can be any number. For example, the number of memories n may be 4 or 5, and the operation speed of the memories may be 1/4 or 1/5. In the case where the number n of memories is another number, the number and timing of each of the write signal, the read signal and the address data are adjusted according to the number. Further, although the circuit example including the D-type flip-flop group is shown as the address specifying means, the structure of the address specifying means may be any other structure.
In the above example, the written data is read out sequentially (I1, I2, ..., 10, ...), but at random (for example, I5, I
2, I10, ...) For example, reading may be performed.

Further, by adding a precharge signal generating circuit to the constituent elements in the memory device of the second invention, a video line memory or the like can be easily constructed by the memory device of the second invention.

[0043]

[Table 1]

[0044]

[Table 2]

[0045]

As is apparent from the above description, according to the memory access method of the first aspect of the present invention, n memory is used.
Number of memories, input data of the cycle T is input to the n memories in parallel, and a data write signal is sequentially applied to the n memories at the cycle nT; On the other hand, the period nt (including the case of t = T)
Since it includes the process of applying the data read signal in order,
The input data of the cycle T is allocated to the n memories and sequentially written in these memories. On the other hand, when reading the data, the data is sequentially read from the n memories and the cycle t (when t = T is satisfied). There is also a possibility).
Moreover, the above write operation in the memory is achieved by accessing each memory at a cycle n times as long as the cycle T of the input data (that is, at a speed of 1 / n when accessing at the cycle T). Further, the read operation is achieved by accessing each memory at a cycle n times as long as the cycle t of the output data (that is, at a speed of 1 / n when accessing at the cycle t). Therefore, the data input / output speed can be increased and the power consumption can be reduced as compared with the related art.

According to the memory device of the second aspect of the present invention, the predetermined n memories, the predetermined data write signal applying means, the predetermined data read signal applying means, the address data generating means, and the predetermined data generating means. With addressing means,
The first invention can be easily implemented. Of course, the address data designating the input / output destination of each of the n memories can be easily generated.

[Brief description of drawings]

FIG. 1 is a timing chart for explaining an access method according to a first embodiment.

2 is a timing chart following FIG. 1 for explaining an access method according to the first embodiment.

FIG. 3 is a diagram for explaining a memory device according to a first embodiment.

FIG. 4 is a timing chart for explaining an access method according to the second embodiment.

FIG. 5 is a timing chart following FIG. 4 for explaining the access method of the second embodiment.

FIG. 6 is a timing chart following FIG. 5 for explaining the access method according to the second embodiment.

FIG. 7 is a diagram for explaining a memory device according to a second embodiment.

FIG. 8 is an explanatory diagram of conventional technology and problems.

9 is an explanatory diagram following FIG. 8 of the related art and problem.

[Explanation of symbols]

20: Memory device of the first embodiment 21: Input / output section 23a-23c: n memories (3 single port SRAMs) 25: Means for applying data write signal 27: Means for applying data read signal 29: Address data generation means 31: Address designation means 23x, 23y: n memories (two dual port SRAMs) 29x: Write address data generation means 29y: Read address data generation means 31x: Write address designation means 31y: Read Addressing means

Claims (7)

[Claims] 1. In a method of accessing a memory, wherein data is written to a memory at a cycle T and data is read from the memory at a cycle t, n memories are used as memories, and the n memories are input at the cycle T. Data is input in parallel and a data write signal is sequentially applied to these n memories at a cycle nT, and a data read signal is sequentially applied to the n memories at a cycle nt. A memory access method characterized by including (where n is an arbitrary integer of 2 or more).
Further, there may be a case where t = T. ). 2. The method for accessing a memory according to claim 1, wherein n single-port random access memories are used as the memories, and a process of inputting input data of a cycle T in parallel to the n memories, A process of applying at least a data read signal and a data write signal to each of the n memories in this order and within each time of the next nT, but with a phase shift of the time T between the n memories. A method of accessing a memory, comprising: 3. The memory access method according to claim 1, wherein n dual-port random access memories are used as the memories, and a process of inputting input data of a cycle T in parallel to the n memories, At least the data write signal is applied to each of the n memories at each time of the next nT, but the process of applying the data write signal to each of the n memories so that the phase is shifted by the time T. A method of accessing a memory, wherein at least the data read signal is applied every next nt time, but so that the phase is shifted by a time t between the n memories. =
There may be a case of T. ). 4. The memory access method according to claim 1, wherein when writing data, the address data designating the same address is applied to each of the n memories at a time interval of T. When the write addresses of the n memories are designated and the data is read, the address data designating the same address is applied to each of the n memories while being shifted by a time t, thereby reading the n memories. A memory access method characterized by addressing (however, there may be a case where t = T). 5. The memory access method according to claim 2, wherein address data designating the same address is applied to each of the n memories at a time interval of T, thereby applying the address of the n memory. A memory access method characterized by specifying. 6. A memory device for inputting / outputting data to / from a memory at a cycle T, wherein n memories to which input data of the cycle T is input are input in parallel, and the n memories are sequentially arranged at a cycle nT. Means for applying a data write signal to the n memories, means for sequentially applying a data read signal to the n memories at a cycle nT, address data generating means for sequentially generating address data of the memories, and A memory device (where n is an arbitrary integer of 2 or more), the address data being shifted by time T for each address data and applied to the n memories without duplication. It is.) 7. In a memory device for writing data to a memory at a cycle T and reading data from the memory at a cycle t, n memories to which input data of the cycle T are input in parallel, and the n memories Means for sequentially applying a data write signal to the memory at a cycle nT, means for sequentially applying a data read signal to the n memories at a cycle nt, and writing for sequentially generating write address data of the memory Address data generating means, write address designating means for sequentially applying the write address data to the n memories by shifting the write address data for each generated write address data by time T, and sequentially generating read address data of the memories. Read address data generating means, and the read address for each of the generated read address data. A memory device comprising read addressing means for applying data to the n memories by shifting the data by time t without duplication (where n is any integer of 2 or more, and t = It may be T.).