JPH05303900A - Signal processor - Google Patents

Abstract

PURPOSE:To reduce by half the size of a device by writing and reading by a storage device storable more 1 data or above than the number of signal data in a prescribed interval. CONSTITUTION:In a first interval, input data is written in address A0-AN by the storage device 17. In a next second interval, the input data is written in the address AN+1-AN-1 by the storage device 18 and the data is read from the address A0-AN and the data delayed by 1 prescribed interval is outputted to an output terminal 22 and the output of the storage device 17 is written in the address AN-AN-2 as the input data by the storage device 18. Further, in a next third interval, by the storage device 17, the write to the address AN-AN-2, and the read from the address AN+1-AN-1 are executed and by the storage device 18, the write to the address AN+1-AN-1 and the read from the address A0-AN are executed and the data delayed by 1 prescribed interval is outputted to the output terminal 22 and the output data delayed by 2 prescribed interval is outputted to the output terminal 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device which delays or inverts an input signal with time to produce an output signal.

[0002]

2. Description of the Related Art A signal processing device that divides an input signal into a predetermined period, stores it in a storage device, delays the signal for a predetermined period, and outputs the signal delayed for a predetermined period is, for example, a television signal. The predetermined period is a horizontal scanning period, which is practically used when a signal interpolated in the vertical direction is obtained by performing an arithmetic operation using the signals of one horizontal scanning period before and two horizontal scanning periods before.

A signal delayed by one predetermined period and a signal delayed by two predetermined periods and inverted in terms of time are also put to practical use in the case of obtaining left-right inverted signals from data similarly interpolated by a television signal. There is.

In the conventional signal processing for obtaining signals delayed by a predetermined period of 1 and 2, three storage devices having a data capacity capable of recording signal data of a predetermined period are used in order to continuously obtain an output signal. The signals delayed by 1 and 2 predetermined periods were continuously obtained by repeating writing to each storage device in order for each predetermined period and reading from two storage devices other than the one in which writing was performed.

Further, in order to continuously obtain an output signal in which a signal delayed by a predetermined period of 1 and 2 is temporally inverted, in the configuration of the above-mentioned storage device, the last signal data at the time of writing is different from that at the time of writing. By reading in the opposite direction, signals delayed by a predetermined period of 1 and 2 and temporally inverted were obtained continuously.

FIG. 5 is a block diagram of a conventional signal processing apparatus for obtaining a signal delayed by a predetermined period of 1 or 2 and FIG. 6 is a block diagram of a signal processing device for obtaining a signal delayed by a predetermined period of 1 or 2 in FIG. FIG. 6 is a diagram illustrating signal writing and signal reading. Further, FIG. 7 is a diagram for explaining writing and reading of signals in the case of obtaining signals that are delayed by a predetermined period of 1 and 2 in FIG. 5 and that are temporally inverted. In FIGS. 6 and 7, the data amount of the signal in a predetermined period is represented by A
_{N + 1} .

First, the case where a signal delayed by a predetermined period of 1 and 2 shown in FIG. 6 is obtained will be described. In the first predetermined period (period 1), the input signal input to the input terminal 1 is input to the memory device 6 by the selector 2, the writing is permitted by the writing control signal 9, and the writing generated by the writing address generator 3 is performed. It is written according to the address. In the period 1, since no data is stored in the storage devices 7 and 8, no data is read to the output terminals 12 and 13.

In the next predetermined period (period 2), the input terminal 1
The input signal input to the storage device 7 is input to the storage device 7 by the selector 2.
The write control signal 9 permits writing, and writing is performed according to the write address generated by the write address generator 3. On the other hand, the read address generated by the read address generator 4 reads the signal data written in the period 1, the output signal thereof is selected by the selector 10 and output to the output terminal 12. During this period, since data for two predetermined periods has not been written in the storage device, only the signal for one predetermined period before is output.

In the next predetermined period (period 3), writing is performed by the storage device 8 and reading is performed by the storage devices 6 and 7, and the signal of the period 1 written in the storage device 6 is selected by the selector 11, and the output terminal 13 is selected. The signal of the period 2 written in the storage device 7 is selected by the selector 10 and output to the output terminal 12.

Further, in the next predetermined period (period 4), writing is performed by the storage device 6 and reading is performed by the storage devices 7 and 8, and the signal of the period 2 written in the storage device 7 is applied to the selector 1.
The signal selected in 1 is output to the output terminal 13, and the signal in the period 3 written in the storage device 8 is selected by the selector 10 and output to the output terminal 11. Then, the above operation is repeated thereafter.

That is, the selector 2 allows the storage device 6,
The input data is switched to 7, 8 and the storage device 6,
Write the input signal to one of the storage devices 7,
The reading of the signal data by the other two storage devices is shifted every predetermined period between the writing storage device and the reading storage device, and the signal data of one predetermined period before is selected by the selector 10 and the predetermined data is read by the selector 11 for two predetermined periods. The previous signal data is selectively taken out, and a signal that is continuously delayed by a predetermined period of 1 or 2 is obtained.

Further, in the case of obtaining a signal which is delayed by a predetermined period of 1 and 2 shown in FIG. 7 and which is inverted in time, in the writing / reading of the memory device described in FIG. Is performed in the reverse direction of writing, so that the signals are one predetermined period before and two predetermined periods before, and
I was getting a time-reversed signal.

In any case, in order to prohibit writing for a predetermined period and obtain the same output signal as the previous predetermined period, the read method is the same as the previous predetermined period and the write control signal 9 is used. Therefore, it is not necessary to allow writing to any storage device.

[0014]

However, in the above-mentioned conventional configuration, in the signal processing for obtaining the inverted signal at every predetermined period, in order to continuously obtain the inverted signal, it is necessary to store the signal data for the predetermined period. Three storage devices with a possible data capacity were required, and the scale of the device was large. Therefore, there is a big problem especially when the signal processing device is configured by an integrated circuit.

[0015]

In order to solve the above-mentioned problems, the signal processing apparatus of the present invention divides an input signal into a predetermined period and delays the divided input signal for a predetermined period of 1 or 2 or time. In a signal processing device for inverting and outputting the signal data, two storage devices capable of storing one or more data signals more than the number of signal data items in the predetermined period are provided, and write addresses for writing the signal data to each of the storage devices. And a read address generator for generating a read address for reading the signal data written in the storage device, so that at least one data write / read operation precedes the read / write operation on the storage device. The generation of the read / write address of the signal data of any storage device is connected at the beginning and end of the address. The first storage device has an output signal of the first storage device as an input signal of the second storage device, so that the signal data of the first storage device is read in a predetermined period before. The first signal data,
Alternatively, the signal is delayed from the last signal data by a predetermined period of 1 and 2, or a signal inverted in time is obtained.

[0016]

With the above configuration, using two storage devices,
When writing / reading to / from the storage device, the read is preceded by at least one data, and when the address of the storage device reaches the end, the next address returns to the first address.
Write as if the addresses are connected in a ring.
A signal processing device that obtains signals 1 and 2 predetermined periods ago by reading and using the output signal data of the first storage device as the input signal data of the second storage device,
Conventionally, it is possible to realize by significantly reducing the configuration scale. In addition, a signal delayed by a predetermined period of 1 or 2 and a signal inverted in time is also written to the storage device.
The read operation is made such that the read operation is preceded by at least one data, and the address of the first storage device is switched in the forward direction / reverse direction at every predetermined period to temporally change the output signal of the first storage device. A signal processing apparatus for obtaining a signal delayed by 1 and 2 predetermined periods and a signal inverted in time by outputting an inverted signal to the second storage device and processing the output signal. Also, it is possible to realize the configuration by significantly reducing the configuration scale. Furthermore, since the amount of signal data stored in the two storage devices is the same,
When only the signals delayed by a predetermined period of 1 and 2 are obtained, the read address generator of the first memory device and the write address generator of the second memory device generate the same address. Reduced to generators,
The one address generator can be a write / read address generator, which can further reduce the configuration scale.

[0017]

1 is a block diagram of a signal processing apparatus showing an embodiment of the present invention. FIG. 2 shows a signal processing device delayed by a predetermined period of 1 and 2 in which the read address generator of the first memory device and the write address generator of the second memory device are combined into one write / read address generator device. FIG. FIG. 3 shows 1 and 2 in FIGS.
It is a figure explaining signal writing and reading when a signal delayed for a predetermined period is obtained. Further, FIG. 4 is a diagram for explaining the writing and reading of signals in the case of obtaining signals that are delayed by a predetermined period of 1 and 2 in FIG. 1 and that are temporally inverted. In FIGS. 3 and 4, the data amount of the signal in a predetermined period is A _{N + 1,} and the configuration and operation of this embodiment will be described below.

First, FIG. 3 showing a case where a signal delayed by a predetermined period of 1 and 2 in the block diagram of FIG. 1 is obtained will be described. In the first predetermined period (period 1), the signal input to the input terminal 14 writes data for a predetermined period from the address A _{0 to the} address A _{N of} the storage device 17 according to the address generated by the write address generator 15. .. Period 1
Since the data for one predetermined period has not yet been written in the storage device 18, the read address generators 16, 20 are
From the output terminals 22, 2
No output signal is output from any of the three.

In the next predetermined period (period 2), the storage device 1
The write address generator 15 writes the input data of 7 so that the write is performed from the address A _{N + 1} to A _N−1, which is the next address of the signal data written in the period 1.
The address is generated from. At this time, the first and last addresses are connected so that the address next to the address A _{N + 1} becomes A ₀ , and the write address is generated so as to form a ring shape. At the same time, the read address generator 16 reads the signal data written in the period 1 from the storage device 17 so as to read from the first address to the last address A _{0 to} A _{N of the} signal data written in the period 1. The address is further generated, and a signal delayed from the input signal data by a predetermined period is obtained from the output terminal 22. At the same time, according to the address generated by the write address generator 19, the output signal of the memory device 17 is stored in the memory device 1
Data of a predetermined period is written from the address A _{0 to the} address A _{N of} 8. During this period, data for two predetermined periods has not yet been written in the storage device, so only the signal for one predetermined period before is output.

Further, in the next predetermined period (period 3), according to the write address generator 15, the addresses A _{N to} A _N are generated.
Up to _N-2 , input signals are written in the memory device 17, and at the same time, reading of the signal data written in the period 2 from the memory device 17 is performed from the first address to the last address of the signal data written in the period A _{N + 1.} As in the case of writing up to A _N-1 , addresses are generated from the read address generator 16 so that the beginning and end of the addresses are connected in a ring shape, and an output signal delayed from the input data signal by a predetermined period is output. Obtained from the output terminal 22. At the same time, storage device 1
According to the address generated by the write address generator 19, the address signal A of the storage device 18
Write data from _{N + 1 to} A _N-1 . Writing to and reading from the storage device 18 are performed so that the first and last addresses are connected in a ring shape, as in the storage device 17. At the same time, according to the address generated by the read address generator 20, A _{0 to} A _N , that is, the first address to the last address of the signal data written in the period 2 are read and the input input to the input terminal 14 is read. An output signal delayed by 2 predetermined periods from the signal is obtained at the output terminal 23. In the subsequent predetermined period, the same operation is repeated, and the signals delayed by the predetermined periods of 1 and 2 can be continuously obtained.

Here, if the storage capacity of the storage device is at least one data larger than the signal data in the predetermined period, the data written in the predetermined period can be output as the data of the delay signal before rewriting, so that writing / reading can be performed. By repeating the above operation, it is possible to continuously obtain signals delayed by 1 and 2 predetermined periods with respect to the input signal at the output terminals 22 and 23.

Further, when the signal data amounts stored in the two storage devices are the same and only the signals delayed by a predetermined period of 1 and 2 are obtained, the read address generator 16 of the first storage device is used.
Since the addresses generated by the write address generator 19 of the second memory device become the same, these are reduced to one address generator device as shown in FIG.
It is possible to use one address generator as the write / read address generator 24, thereby reducing the configuration scale. Writing / reading of signal data to / from the storage device in this case is the same as that in FIG.

Next, the case of obtaining a signal which is delayed by a predetermined period of 1 and 2 in FIG. 4 and which is temporally inverted will be described. When obtaining the inverted signal, the address generated by the write / read address of the signal to / from the storage device 18 is the same as when obtaining the signal delayed by 1 and 2 predetermined periods. In order to obtain a time-reversed signal, the read address of the memory device 17 is reversed from that for writing, and a time-inverted signal of the output signal is output to the output terminal 22, and at the same time, the input of the memory device 18 is input. By using a signal, it becomes possible to continuously obtain signals that are delayed by a predetermined period of 1 and 2 and are temporally inverted. Hereinafter, a case where a signal which is delayed for a predetermined period of 1 and 2 and temporally inverted is obtained will be described.

First, in the first predetermined period (period 1),
The input signal input to the input terminal 14 is the write address 1
According to the address generated by 5, the address of the storage device 17 is
Space A ₀Address ~ A_NWrite data for a specified period up to the address
Mu.

In the next predetermined period (period 2), the storage device 1
Addresses are generated from the write address generator 15 so as to write the input signal data from the addresses A _{N + 1} to A _{1 of} 7. At the same time, reading of the signal data written in the period 1 from the memory device 17 is performed from addresses A _N (the last address of the signal data written in the predetermined period) to A
Up to ₀ , an address is generated from the read address generator 16 in the reverse order of the data written in the period 1, delayed by one predetermined period, and a time-inverted signal is obtained from the output terminal 22. At the same time, the output signal of the storage device 17 is written in accordance with the address generated by the write address generator 19 to write data for a predetermined period from addresses A _{0 to} A _{N of} the storage device 18. This period is still 2
Since the data of the predetermined period has not been written in the storage device 18, only the inverted signal of one predetermined period before is output.

Next, in the next predetermined period (period 3), the write address generator 15 writes the input signals to the addresses A _{0 to} A _N in the memory device 17. At the same time, period 2
Of the signal data written in a predetermined period from the storage device 17 is read from the address A ₁ (the last address of the signal data written in the predetermined period) to A _{N + 1} . Addresses are generated from the read address generator 16 in the reverse order, delayed by one predetermined period, and a time-reversed signal is obtained from the output terminal 22. At the same time, the output signal data of the storage device 17 is written according to the address generated by the write address generator 19 to the addresses A _{N + 1 to} A _{N−1 of} the storage device 18. Writing to and reading from the storage device 18 are performed so that the first and last addresses are connected in a ring shape. At the same time, the read address generator 2
According to the address generated by 0, A _{0 to} A _N , that is, the first address to the last address of the signal data written one predetermined period before is delayed by the read output terminal 23 from the input terminal for two predetermined periods, and , Get the signal inverted in time.

Further, in the next predetermined period (period 4), the writing / reading of the storage device 17 becomes the same as the writing / reading of the period 2. Similarly, by repeating writing / reading every predetermined period, temporally inverted signals can be continuously obtained.

Here, if the storage capacity of the storage device is at least one data larger than the signal data in the predetermined period, the data written in the predetermined period can be output as the inverted signal data before being rewritten, so that the writing / reading is possible. By repeating the above operation, the output terminals 22 and 23 have
It is possible to continuously obtain an output signal which is delayed by a predetermined period of 1 and 2 with respect to the input signal and which is temporally inverted. In addition, to obtain a delayed signal or an inverted signal, in order to prohibit writing for a certain predetermined period and obtain the same output signal as the previous predetermined period, the reading method is the same as the previous predetermined period. Then, by the write control signal 21,
It is not necessary to allow writing to any storage device.

The case where the storage capacity of the storage device is larger than the signal data amount in the predetermined period by one data has been described as an example, but the same applies when the storage capacity of the storage device is larger than the predetermined period by two data or more. For example, when the storage capacity of the storage device is larger than the predetermined period by two data, the addresses of the storage device are A _{0 to} A _{N + 2 in} FIGS. 3 and 4. When an inverted signal is obtained, writing (corresponding to a in FIG. 3) / reading (corresponding to c in FIG. 3) in descending order (the address is in the reverse direction) is performed from the larger address, the addresses are A _{N + 2 to} A ₂ , or , A _{N + 1} ~ A ₁
Either is possible. Similarly, writing is performed in ascending order (address is in the forward direction) from the smaller address (a in FIG.
e)) ・ Reading (equivalent to f in Fig. 3) uses the address A
Either _{0 to} A _N or A _{1 to} A _{N + 1} is possible.
The same applies when the storage capacity of the storage device is larger than the signal data of the predetermined period by 3 data or more, and each of the two storage devices satisfies at least one data larger than the signal data amount of the predetermined period. The same applies when the data amount of the storage device is different. Further, when it is desired to obtain an output signal which is delayed or inverted by three predetermined periods, a storage device having a storage capacity larger than that of the predetermined period by at least one data and a write / read address generator are added, and an output terminal 23 is provided. By using this output signal as the input signal of the added storage device, it is possible to obtain an output signal that is delayed or inverted for three predetermined periods. The same applies when it is desired to obtain a delayed or inverted signal of four or more predetermined periods.

[0030]

As described above, the signal processing apparatus of the present invention has a significantly reduced size as compared with the conventional one. Therefore, for example, when the signal processing apparatus is configured by an integrated circuit, the configuration is reduced. There is an advantage that the area is small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a signal processing device according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram for explaining write and read operations for obtaining signals delayed by a predetermined period of 1 and 2 in the signal processing device of the embodiment.

FIG. 4 is an explanatory diagram for explaining write and read operations for obtaining a signal that is delayed by a predetermined period of 1 and 2 and temporally inverted in the signal processing device of the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional signal processing device.

FIG. 6 is an explanatory diagram for explaining write and read operations for obtaining signals delayed by a predetermined period of 1 and 2 in a conventional signal processing device.

FIG. 7 is a drawing for obtaining a signal which is delayed by a predetermined period of 1 and 2 in the conventional signal processing device and is temporally inverted,
Explanatory diagram for explaining the read operation

[Explanation of symbols]

 14 input terminal 21 write control signal 17,18 storage device 15,19 write address generator 16,20 read address generator 24 write / read address generator 22,23 output terminal

Claims (3)

[Claims] 1. A signal processing device that divides an input signal into a predetermined period and outputs a signal obtained by delaying the divided input signal by 1 predetermined period and 2 predetermined periods in terms of the number of signal data in the predetermined period. First and second storage devices capable of storing more than one data, a write address generator for generating a write address for writing signal data in each of the first and second storage devices, and the first , A read address generator for generating a read address for reading the written signal data of each of the second storage devices, and writing to the first storage device from a first address for a first predetermined period of time. When writing is performed, writing is performed from an address obtained by adding 1 to the last address of the previous period during the second predetermined period, and when the writing address becomes the last. Returning to the first address, to write to write,
At the same time, reading from the first memory device is performed from the address of the first signal data written in the first predetermined period, and the read signal data is read from the first address of the second memory device by a predetermined amount. Writing is performed only during the period, and during the third predetermined period, the data is written into the first storage device.
Writing is performed from an address obtained by adding 1 to the last address of the previous period, and at the same time, reading from the first storage device is performed for a predetermined period from the address of the first signal data written in the second predetermined period. Writing the read signal data into the second storage device,
At the same time, reading from the second storage device is repeatedly performed for a predetermined period from the address of the first signal data written in the second predetermined period, and the first and second storage devices are repeated. A signal processing device, wherein a signal delayed by one predetermined period and two predetermined periods is obtained. 2. One of the read address generator of the first storage device and the write address generator of the second storage device is reduced, and the remaining one address generator is used as the second storage device. 2. The signal processing device according to claim 1, wherein the signal processing device is a write address generating device for writing the data and the read address of the first storage device. 3. A signal processing apparatus which divides an input signal into predetermined periods, delays the divided input signals by 1 predetermined period and 2 predetermined periods in time, and outputs a signal inverted in time, First and second storage devices capable of storing one or more data items greater than the number of signal data items in a period, and writing for generating a write address for writing signal data to each of the first and second storage devices An address generator and a read address generator for generating a read address for reading the written signal data of each of the first and second storage devices are provided. Writing is performed in the ascending order for the first predetermined period, and for the second predetermined period, the writing is performed in the descending order from the last address for the next predetermined period, and the simultaneous reading is performed. The data is read from the address of the last signal data written in the first storage device in the first predetermined period, and the read signal data is read in the second storage device from the first address for a predetermined period. Writing is performed, and the first predetermined period is for the third predetermined period.
Writing to the storage device is performed in ascending order from the first address for a predetermined period, and at the same time, reading is performed for a predetermined period from the address of the last signal data written to the first storage device in the second predetermined period. Read out,
The read signal data is continuously written in the second storage device at the last address of the previous period, and when the write address reaches the end, the write data is written back by returning to the first address, and at the same time, the second address is written. The reading from the memory device is repeated from the address of the first signal data written in the second predetermined period, which is delayed from the first and second memory devices by one predetermined period and two predetermined periods, The signal processing device according to claim 1, wherein a signal inverted in time is obtained.