JPH07199883A - Image memory circuit - Google Patents

Abstract

PURPOSE:To realize an inexpensive image memory circuit capable of corresponding to plural conversion processing with simple constitution. CONSTITUTION:A memory circuit 1 is constituted of plural, e.g. two data registers 2, 3 where a column address in a memory cell array 121 stores the data of the same memory cell, a data register selector 4 selecting the two data registers 2, 3 by a selection signal (sel) and outputting the data of the column address specified by a column address decoder and a buffer selector 5 selecting the data stored in the data registers 2, 3 and outputting to a serial I/O buffer 141.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a column address specifying means for specifying a column address and a row address specifying means for specifying a row address, and stores image data based on the column address and the row address. / It relates to an image memory circuit for reproducing.

[0002]

2. Description of the Related Art When displaying an image on a monitor such as a computer, it is necessary to output the image data stored in a storage circuit composed of a RAM or the like with the number of scanning lines that matches the number of scanning lines of the monitor.

In the conventional image data output related to such scanning lines, as shown in FIG. 5A, for example, the image data stored in the storage circuit is read out and output for each line of 480 scanning lines. Was there.

By the way, in image processing of a computer or the like, there is a method of performing letterbox conversion on image data as shown in FIG. 5B. In this letterbox conversion, each line data of the 480 scanning lines of FIG. 5A is processed to generate an image of, for example, 3/4 360 scanning lines as shown in FIG. 5B. To do.

Conventionally, the arithmetic processing in this letterbox conversion has been performed by the arithmetic processing circuit shown in FIG. That is, in FIG. 6A, a conventional arithmetic processing circuit is a memory circuit 101 that stores image data, and an operation that reads image data from the memory circuit 101, performs letterbox conversion, and outputs an image to the monitor 102. And a circuit 103.

Specifically, first, the arithmetic circuit 103 specifies an address to the memory circuit 101, reads out the data of the first pixel on the first line, and stores the data in the register in the arithmetic circuit 103. Next, the arithmetic circuit 103 changes the memory circuit 10
By designating an address for 1, the data of the first pixel on the second line is read out and stored in the register in the arithmetic circuit 103. Then, a predetermined calculation is performed by using the data of the first pixel of the first line and the data of the first pixel of the second line stored in the register to generate the converted first pixel data of the first line, which is output to the monitor 102.

Subsequently, the arithmetic circuit 103 causes the memory circuit 10 to operate.
By designating an address for 1, the data of the second pixel on the first line is read out and stored in the register in the arithmetic circuit 103. Next, the arithmetic circuit 103 specifies an address for the memory circuit 101, reads out the data of the second pixel on the second line, and stores the data in the register in the arithmetic circuit 103. Then, a predetermined calculation is performed using the data of the second pixel of the first line and the data of the second pixel of the second line stored in the register to generate the second pixel data of the first line after conversion, and monitor 1
Output to 02. By repeating such processing, the image data of the first line after conversion is generated and the monitor 102 is generated.
Is output to.

Similarly, when the converted second line image data is generated, the second and third line data stored in the memory circuit 101 is read out and a predetermined calculation is performed.

As shown in FIG. 7, the memory circuit 101 comprises a memory cell array 121 composed of an inexpensive DRAM, and the memory cell array 121 is composed of columns (ro).
By specifying the w) address and the row address, the data stored in the specified memory cell can be read.

For this memory circuit 101, the arithmetic circuit 1
03 designates a column address and a row address.
A flag bit consisting of 2 bits is output. The upper bit of this flag bit is a column address designation bit (ras) that becomes "1" when the address designated by the arithmetic circuit 103 is a column address, and the lower bit is the arithmetic circuit 1
"1" if the address specified by 03 is a row address
Is a row addressing bit (cas).

The flag bit is used as the memory circuit 1.
01 is output to the clock generator 122 and the address is output to the address buffer 123.
The clock generator 122 outputs a pulse based on the flag bit ras or cas to the address buffer 12
By outputting to the address buffer 3, the address buffer 123 determines whether the input address is a column address or a row address.

The arithmetic circuit 103 includes a memory cell array 12
For 1, the column address is specified first, so ras
Is set to "1" (cas is "0" at this time), and the column address is output to the address buffer 123. The address buffer 123 outputs the input column address to the column address decoder 124, and the column address decoder 124 decodes the column address and designates the column of memory cells designated by the column address of the memory cell array 121. Subsequently, the arithmetic circuit 103 sets cas to “1” (at this time, ras is “0”) to specify the row address to the memory cell array 121, and outputs the row address to the address buffer 123. The address buffer 123 outputs the input row address to the row address decoder 125,
The row address decoder 125 decodes the row address and designates a row of memory cells designated by the row address of the memory cell array 121 via a sense amplifier (sense amp) 126. In this way, the memory cell is determined, and data is written or read in this memory cell.

When writing data to the designated memory cell, the write enable signal (we) from the arithmetic circuit 103.
Becomes "1", and this we is input to the write / read clock generator 127. Then, the write / read clock generator 127 outputs the write clock to the sense amplifier 126, so that the sense amplifier 126
Inputs data to be written via the I / O buffer 128 and writes the data to the designated memory cell. on the other hand,
When reading data from the specified memory cell, the write enable signal (we) becomes “0” from the arithmetic circuit 103, and this we is input to the write / read clock generator 127. Then, the write / read clock generator 127 outputs the read clock to the sense amplifier 1
By outputting the data to the memory cell array 26, the sense amplifier 126 reads the data from the designated memory cell of the memory cell array 121 and outputs the data to the arithmetic circuit 103 via the I / O buffer 128.

In such a memory circuit 103, when the desired data is read out and operated, especially in the operation processing of a huge amount of data such as image data, access cannot be made unless the column address and row address of the memory cell are designated each time. Therefore, there is a problem that the calculation process takes time.

Therefore, an arithmetic processing circuit having a plurality of line memories for performing letterbox conversion has been proposed. That is, in FIG. 6B, the arithmetic processing circuit includes a memory circuit 104 that stores image data and a plurality of FIFOs (first-in-first-fast) that store line data designated by column addresses from the memory circuit 104.・
Out) type line memory 105 and memory circuit 10
4 and an arithmetic circuit 106 that reads out the image data stored in the line memory 105, performs letterbox conversion, and outputs an image to the monitor 102.

Specifically, first, the arithmetic circuit 106 specifies an address for the memory circuit 104, reads out the data of the first pixel on the first line, and stores the data in the register in the arithmetic circuit 106. Next, the arithmetic circuit 106 sets the memory circuit 10
The address of the second line is designated with respect to 4, and the line data is read out and stored in the line memory 105. Then, a predetermined calculation is performed based on the data of the first pixel of the first line stored in the register and the data of the first pixel of the second line stored in the line memory 105, and the first data of the first line after conversion is obtained.
Pixel data is generated and output to the monitor 102.

Subsequently, the arithmetic circuit 106 causes the memory circuit 10 to operate.
By designating an address for 4, the data of the second pixel of the first line is read out and stored in the register in the arithmetic circuit 103. Next, a predetermined calculation is performed based on the data of the second pixel of the first line stored in the register and the data of the second pixel of the second line stored in the line memory 105, and the first pixel after conversion is performed.
The second pixel data of the line is generated and output to the monitor 102. By repeating such processing, the converted first-line image data is generated and output to the monitor 102.

When the converted second line image data is generated, the line data of the third line is stored in the line memory 105 so that the line data of the second and third lines are stored in the line memory 105. Therefore, the pixel data is sequentially stored from the line memory 105 to the register without accessing the memory circuit 104, and the pixel data is generated by performing a predetermined calculation. Similar processing is repeated from the second line onward.

As described above, in the memory circuit 104 for transferring continuous line data to the line memory 105, a DRAM having a high speed mode is used. Since this configuration is almost the same as the configuration in FIG. 7, only different configurations will be described. That is, as shown in FIG. 8, the data transfer to the line memory 105 is not performed via the I / O buffer 128, but the serial I / O buffer 1 is used.
Via 41. Specifically, since the column address is first specified for the memory cell array 121,
s is set to “1” (cas is “0” at this time), and the column address is output to the address buffer 123. The address buffer 123 outputs the input column address to the column address decoder 124, and the column address decoder 124 decodes the column address and designates the column of memory cells designated by the column address of the memory cell array 121. Then, the data in the memory cell in the designated column is transferred to the data register 142.
Stored in. This data register 142 is a pointer 1
When the pointer 143 is advanced by sas, the data of the memory cells in the column stored in the data register 142 are sequentially transferred to the line memory 105.
The data in the memory cells in the column stored in the data register 142 can be sequentially designated and transferred by the row address without using the pointer 143. In this case, once the column address is changed, that is, another column address is accessed, the data register 142 is changed.
Since the content of is rewritten, in order to access the memory cell of the original column address again, it is necessary to respecify the column address and transfer the data to the data register 142 again.

A case where the arithmetic circuit 106 uses the memory circuit 104 to perform the letterbox conversion shown in FIG. 5 will be described. In the letterbox conversion, as shown in FIG. 9, the data of the odd field of the nth line and the data of the odd field of the n + 1th line are used, the data of the odd field of the nth line is multiplied by 5 and the nth + 1th data. The data of the odd-numbered field of the line is multiplied by the weight of 1 and added, and the result is divided by 6 to obtain the m-th m after the letterbox conversion.
Generate data for the odd fields of the line. Similarly,
Data in the even field of the m-th line after the letterbox conversion is generated.

Next, using the data of the odd field of the (n + 1) th line and the data of the odd field of the (n + 2) th line, the data of the odd field of the (n + 1) th line is multiplied by a weight of 1 to obtain the data of the odd field of the (n + 2) th line. Is multiplied by a weight of 1 and divided by 2, thereby generating the data of the odd field of the (m + 1) th line after the letterbox conversion. Similarly, m-th after letterbox conversion
Data for the even field of +1 line is generated.

Then, using the data of the odd field of the (n + 2) th line and the data of the odd field of the (n + 3) th line, the data of the odd field of the (n + 2) th line is multiplied by a weight of 1, and the data of the odd field of the (n + 3) th line. Is multiplied by a weight of 5 and divided by 6 to generate the data of the odd field of the (m + 2) th line after the letterbox conversion. Similarly, the data of the even field of the (m + 2) th line after the letterbox conversion is generated.

By repeating the above processing, letterbox conversion is performed.

In the image display, the scanning line must read the data on the screen in time with the advance time. FIG. 10 shows the relationship between the read line data and the read time. That is, as shown in FIG. 10, when letterbox conversion is not performed, it is sufficient to read 480 lines of data from the memory in 1/30 seconds, and the slope at this time corresponds to the reading speed of the memory circuit and the bandwidth. Become.

However, in letterbox conversion, first, the upper ⅛ of the screen is output in black, and when the scanning line advances ⅛, data is first read from the memory circuit 104 and conversion processing is started. And this process must be completed before the scan line reaches the lower 1/8 of the screen. Then, black is output to the lower 1/8 of the screen. That is, it is necessary to read the data and finish the conversion in 3/4 time which is shorter than the normal reading time.

In the conversion process of FIG. 9, since data of all lines are used for conversion, in order to read all line data in a short 3/4 time, as shown in FIG.
It is necessary to use a memory circuit having a higher bandwidth (larger slope) than the memory circuit normally used for reading the screen.

Therefore, a modified example of the arithmetic processing for performing the letterbox conversion has been proposed. That is, as shown in FIG. 12, using the data of the odd field of the (n-1) th line and the data of the odd field of the (n + 1) th line,
-1 line odd field data is multiplied by a weight of 2, and n + 1 line odd field data is weighted by 2
Is added and divided by 4 to generate the data of the odd field of the m-th line after the letterbox conversion. Similarly, the data in the even field of the m-th line after the letterbox conversion is generated.

Next, using the data of the odd field of the (n + 1) th line and the data of the odd field of the (n + 2) th line, the data of the odd field of the (n + 1) th line is multiplied by weight 3 to obtain the data of the odd field of the (n + 2) th line. Is multiplied by a weight of 1 and divided by 4, thereby generating data in the odd field of the (m + 1) th line after letterbox conversion. Similarly, m-th after letterbox conversion
Data for the even field of +1 line is generated.

Next, using the data of the odd field of the (n + 2) th line and the data of the odd field of the (n + 3) th line, the data of the odd field of the (n + 2) th line is multiplied by a weight of 1, and the data of the odd field of the (n + 3) th line. Is multiplied by a weight of 3 and then divided by 4 to generate the data of the odd field of the (m + 2) th line after the letterbox conversion. Similarly, the data of the even field of the (m + 2) th line after the letterbox conversion is generated.

By repeating the above processing, letterbox conversion is performed.

Therefore, in the conversion process shown in FIG. 12, since only 3/4 line (360 line) data is used as shown in FIG. 13, a memory circuit having the same bandwidth as the normal screen can be used. . However, as a matter of course, since only 3/4 line data is used, the image quality is deteriorated as compared with the conversion processing of FIG.

[0032]

However, as shown in FIG.
Memory circuit 1 used in the arithmetic processing circuit of (a)
In 01, since the column and row address of the memory cell must be designated each time the data is accessed, the DRAM high speed mode cannot be used, and the read speed needs to be high, which causes deterioration in image quality. Even in the case of performing the conversion process of FIG. 12, it is necessary to have a high bandwidth, and there is a problem that the memory circuit becomes expensive.

Further, since the arithmetic processing circuit of FIG. 6B includes the line memory 105, the line data once read from the memory circuit is stored in the line memory, so that the bandwidth of the memory circuit is increased. Although the above problem is solved, there is also a problem that an inexpensive arithmetic processing circuit cannot be realized because a line memory must be provided and configured.

Furthermore, since the bandwidth of the memory circuit required depends on the conversion processing method, the conversion processing shown in FIGS. 9 and 12 cannot always be realized by the same memory circuit. There is a problem of being limited.

The present invention has been made in view of the above circumstances, and can cope with a plurality of conversion processes with a simple configuration.
It is an object to provide an inexpensive image memory circuit.

A memory circuit 1 as an image memory circuit of the present invention includes a column address decoder 124 as a column address designating means for designating a column address and a row address designating means as a row address designating means for designating a row address. In an image memory circuit that includes a row address decoder 125 and stores / reproduces image data based on a column address and a row address, a plurality of image data having different column addresses designated by the column address decoder 124 are stored. Data registers 2 and 3 as column data storage means, pointers 2a and 3a as column data row address designating means for designating a row address of image data of column addresses stored in the data registers 2 and 3, and data registers 2 and 3 is selected, and the pointers 2a and 3 stored in the selected data registers 2 and 3 are selected. There formed a buffer selector 5 as matrix data selection means for selecting a given matrix data.

The image memory circuit of the present invention sequentially selects the data registers 2 and 3, and selects the selected data register 2 and 3.
The arithmetic circuit 20 may be provided as a conversion image generating unit that generates conversion image matrix data based on the matrix data designated by the pointers 2a and 3a stored in the memory 3.

The arithmetic circuit 20 can generate letterbox converted image matrix data.

The arithmetic circuit 20 has multipliers 31 and 32 as a plurality of multiplying means for multiplying the matrix data designated by the pointers 2a and 3a stored in the data registers 2 and 3 by weights.
And a divider 33 as a dividing means for adding the outputs of the multipliers 31 and 32 and dividing by the sum of the multiplied weights. The sum of the weights divided by the divider 33 should be 2. It can be a number.

[0039]

[Operation] In the memory circuit 1 of the present invention, the buffer selector 5 selects the data registers 2 and 3, and the matrix data designated by the pointers 2a and 3a stored in the selected data registers 2 and 3 are selected. With a simple configuration,
It is possible to realize an inexpensive image memory circuit that can handle a plurality of conversion processes.

The arithmetic circuit 20 sequentially selects the data registers 2 and 3, and generates converted image matrix data based on the matrix data designated by the pointers 2a and 3a stored in the selected data registers 2 and 3. Thus, it is possible to realize an image memory circuit capable of supporting a plurality of conversion processes at higher speed.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a first embodiment of a memory circuit of the present invention. Since this embodiment includes the same configuration as the conventional memory circuit shown in FIG. 8, only different configurations will be described and the same configurations will be denoted by the same reference numerals and description thereof will be omitted.

As described above, in the conventional memory circuit of FIG. 8, the data of the row address within the same column address is accessed at high speed by designating the column address, but the column within the same row address is accessed. The address data cannot be accessed at high speed. The present embodiment is a memory circuit in which this point is improved.

As shown in FIG. 1, the memory circuit 1 of this embodiment has a plurality of, for example, two data registers 2 and 3 for storing data of memory cells having the same column address, and these two data registers 2 and 3. Is selected by the selection signal (sel) to output the data of the memory cell of the column address designated by the column address decoder, and the data stored in the data registers 2 and 3 is selected to select the serial I / O buffer. Buffer selector 5 for outputting to 141
And is configured. The data registers 2, 3
Is the data register 1 of the conventional memory circuit shown in the figure.
Like the reference numeral 42, the pointers 2a and 3a are provided, and the pointers 2a and 3a are stored in the data registers 2 and 3 by advancing by the sas or by designating the row address input via the data register selector 4. The data in the memory cells in the column can be sequentially transferred to the buffer selector 5. Other configurations are shown in FIG.
This is the same as the conventional memory circuit shown in FIG.

The operation of the present embodiment having such a configuration will be described. To specify the column address of the first line data to the memory cell array 121, first, ra
s is set to "1" (cas is "0" at this time), and the column address of the first line data is output to the address buffer 123. The address buffer 123 outputs the input column address to the column address decoder 124, and the column address decoder 124 decodes the column address and designates the column of memory cells designated by the column address of the memory cell array 121. Then, the data of the memory cell in the designated column is temporarily stored in the data register selector 4. And s
The data register 2 is selected by el and the data stored in the data register selector 4 is stored in the data register 2. Next, to specify the column address of the second line data, ras is set to "1" (at this time, cas is "
0 ″), and outputs the column address of the second line data to the address buffer 123. The address buffer 123
The input column address is output to the column address decoder 124, and the column address decoder 124 decodes the column address and designates the column of the memory cell designated by the column address of the memory cell array 121. Then, the data of the memory cell in the designated column is temporarily stored in the data register selector 4. Then, the data register 3 is selected by sel, and the data stored in the data register selector 4 is stored in the data register 3.

Then, by advancing the pointers 2a and 3a by sas or designating the row address input through the data register selector 4, the row of data of the memory cells in the columns stored in the data registers 2 and 3 is selected. After being determined, the buffer selector 5 selects the data registers 2 and 3, and the data of the memory cells of the columns alternately stored in the data registers 2 and 3 are sequentially transferred to the serial I / O buffer, and an arithmetic circuit (not shown) (for example, , The arithmetic circuit of FIG. 6)
Output to.

When the reading of one set of line data is completed, the column address of the third line data is designated for reading the next set of data and stored in the data register 2 via the data register selector 4. . At this time, since the second line data is already stored in the data register 3, the second line data is not read out again, and the data register 2,
According to the data of the memory cells in the column stored in No. 3, the data to be used in the next calculation is equivalent to the above data in the buffer selector 5
To select the data registers 2 and 3 to alternately transfer the data of the memory cells in the columns stored in the data registers 2 and 3 to the serial I / O buffer sequentially, and to execute an arithmetic circuit (not shown) (for example, the arithmetic circuit of FIG. ) Is output. Subsequent reading of line data is performed in the same manner, whereby all the sets of line data used for image conversion by the arithmetic circuit are sequentially read.

As described above, according to the memory circuit 1 of the present embodiment, in the memory circuit 1, a column address is designated, a plurality of row address data are stored in a plurality of data registers, and the data registers are switched to be selected. By doing so, data of different column addresses can be read alternately in the order of row addresses, so that the bandwidth of the memory circuit can be increased, and an inexpensive image memory circuit that can handle a plurality of conversion processes with a simple configuration. Can be realized.

Although it has been stated that all the row address data of the same column address are stored in the data registers 2 and 3, the present invention is not limited to this, and a plurality of corresponding row address data of the same column address are stored in the data registers 2 and 3. 3 may be stored in the data register 2,
Since the capacity of 3 can be made small, the cost can be further reduced.

Next, the second embodiment will be described. 2 to 4 relate to the second embodiment, FIG. 2 is a configuration diagram showing a configuration of a second embodiment of a memory circuit of the present invention, and FIG. 3 is a configuration diagram showing one configuration of the arithmetic circuit of FIG. 4 is an explanatory diagram for explaining an example of processing contents of the arithmetic circuit of FIG. Since the second embodiment is almost the same as the first embodiment, only different configurations will be described, the same configurations will be denoted by the same reference numerals, and description thereof will be omitted.

In the second embodiment, as shown in FIG. 2, in the memory circuit, an arithmetic circuit 20 for sequentially reading the data stored in the data registers 2 and 3 in the first embodiment by cal and performing a predetermined arithmetic processing is provided. Be prepared for. The other structure is the same as that of the first embodiment.

As described above, in the second embodiment, by providing the arithmetic circuit 20 in the memory circuit, it is possible to generate the line data used for the conversion processing. Therefore, in addition to the effect of the first embodiment, a plurality of line data can be obtained. It is possible to realize a high bandwidth capable of supporting the conversion processing of.

The arithmetic circuit 20 can be, for example, an arithmetic circuit for performing the letterbox conversion process shown in FIG. In this case, as shown in FIG. 3, the arithmetic circuit 20 includes a multiplier 31 for multiplying the line data stored in the data register 2 by the weight 5 and a multiplier 31 for multiplying the line data stored in the data register 3 by the weight 1. 32, and a divider 33 that adds the output of the multiplier 31 and the output of the multiplier 32 and divides by 6.

Since the divider 32 must be divided by 6, it cannot be constructed by a simple divider such as bit shift. Therefore, as shown in FIG. 4, the data of the odd field of the nth line is directly used as the data of the odd field of the mth line after the letterbox conversion. The same applies to the data in the even field of the m-th line after the letterbox conversion.

Next, using the data of the odd field of the (n + 1) th line and the data of the odd field of the (n + 2) th line, the data of the odd field of the (n + 1) th line is multiplied by weight 3 to obtain the data of the odd field of the (n + 2) th line. Is multiplied by a weight of 1 and divided by 4, thereby generating data in the odd field of the (m + 1) th line after letterbox conversion. Similarly, m-th after letterbox conversion
Data for the even field of +1 line is generated.

Next, using the data of the odd field of the (n + 2) th line and the data of the odd field of the (n + 3) th line, the data of the odd field of the (n + 2) th line is multiplied by a weight 1 to obtain the data of the odd field of the (n + 3) th line. Is multiplied by a weight of 3 and then divided by 4 to generate the data of the odd field of the (m + 2) th line after the letterbox conversion. Similarly, the data of the even field of the (m + 2) th line after the letterbox conversion is generated.

By repeating such processing, letterbox conversion is performed. Therefore, the number to divide is 2.
Since the power of 4 is 4, it is possible to easily perform division by bit-shifting, and the arithmetic circuit can be configured more easily.

[0057]

As described above, according to the image memory circuit of the present invention, the matrix data selection means selects a plurality of column data storage means, and the column data rows stored in the selected column data storage means. By selecting the matrix data designated by the address designating means, it is possible to realize an inexpensive image memory circuit that can handle a plurality of conversion processes with a simple configuration.

The converted image generation means sequentially selects a plurality of column data storage means, and converts the converted image matrix data based on the matrix data designated by the column data row address designation means stored in the selected column data storage means. The generation has an effect of realizing an image memory circuit capable of supporting a plurality of conversion processes at higher speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a first embodiment of a memory circuit of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a second embodiment of a memory circuit of the present invention.

FIG. 3 is a configuration diagram showing a configuration of an arithmetic circuit of FIG.

FIG. 4 is an explanatory diagram illustrating an example of processing contents of the arithmetic circuit of FIG.

FIG. 5 is an explanatory diagram illustrating letterbox conversion.

FIG. 6 is a configuration diagram showing a configuration of an arithmetic processing circuit including a conventional memory circuit.

7 is a configuration diagram showing a configuration example of the memory circuit of FIG.

FIG. 8 is a configuration diagram showing another configuration example of the memory circuit of FIG.

9 is an explanatory diagram illustrating a letterbox conversion processing method of FIG. 5;

FIG. 10 is an explanatory diagram illustrating a reading speed of an image memory of a normal image.

11 is an explanatory diagram illustrating a reading speed of the image memory according to the processing method of FIG.

FIG. 12 is an explanatory diagram illustrating a modified example of the letterbox conversion processing method of FIG. 5;

13 is an explanatory diagram illustrating a reading speed of the image memory according to the processing method of FIG.

[Explanation of symbols]

 1 Memory Circuit 2, 3 Data Register 2a, 3a Pointer 4 Data Register 5 Buffer Selector 20 Operation Circuit 31, 32 Multiplier 33 Divider 121 Memory Cell Array 122 Clock Generator 123 Address Buffer 124 Column Address Decoder 125 Row Address Decoder 126 Sense Amplifier 141 Serial I / O buffer

Front Page Continuation (72) Inventor Jun Yoneman 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (4)

[Claims] 1. An image memory comprising a column address designating means for designating a column address and a row address designating means for designating a row address, and storing / reproducing image data based on the column address and the row address. In the circuit, a plurality of column data storage means for storing image data of the plurality of different column addresses designated by the column address designating means, and a row address of the image data of the column address stored by the plurality of column data storage means A column data row addressing means for designating a plurality of column data storage means, and a matrix for selecting matrix data designated by the column data row addressing means stored in the selected column data storage means An image memory circuit comprising a data selecting means. 2. The converted image matrix data based on the matrix data designated by the column data row addressing means stored in the plurality of selected column data storage means sequentially selected from the plurality of column data storage means. The image memory circuit according to claim 1, further comprising a conversion image generation unit that generates 3. The image memory circuit according to claim 2, wherein the converted image generating means generates letterbox converted image matrix data. 4. The conversion image generation means includes a plurality of multiplication means for multiplying the matrix data designated by the column data row address designation means stored in the plurality of column data storage means by a weight, and the plurality of multiplication means. And a division unit that divides by the sum of the weights that are multiplied by the output of, and the sum of the weights that the division unit divides is a power of two. Image memory circuit.