JPS6055589A - Control system of memory - Google Patents

Abstract

PURPOSE:To obtain a memory of a nibble mode which has a normal actuation even with a single clock by validating just one of control signals sent successively and permiting the writing of just a data to a small area in case the cycle for successive transmission of data is larger than the cycle for successive transmission of control signals. CONSTITUTION:When the 1st memory start signal MGO which is sent to a terminal 13 from a CPU (not shown in the figure) is set at ''1'', ''1'' is delivered successively from DFF1-9 every time a single clock advances by a clock. While the 2nd memory start signal SMGO is delivered from a terminal 16 so that ''1'' is set only at T0-T1. A counter 37 is reset with the signal MGO and adds +1 to its value with reception of the signal SMGO. A selector 38 selects WE0, WE1, WE2 and WE3 when the value of the counter 37 is set at ''1'', ''2'', ''3'' and ''4'' respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION a8 TECHNICAL FIELD OF THE INVENTION The present invention relates to a storage device operating in nibble mode.

b. Background of the technology Conventionally, when writing data to or reading data from a storage device, an address assigned to each storage element (consisting of a row address and 9 column addresses) is specified, Data is written to or read from the memory element.

Incidentally, storage devices that operate in nibble mode have recently been proposed.

For example, if a storage device that operates in this nibble mode has a storage area of 256 kW (kiloword) capacity, the storage area is divided into four. It is assumed that each of the four divided small areas has a capacity of 54 kW and has the same address configuration. When one address is sent to the storage device at a certain timing, the previously sent address is sequentially designated to four small areas in synchronization with a certain cycle of clock pulses. If writing is specified, the data sequentially sent to the storage device in synchronization with the clock pulse is written into the storage element corresponding to the address in the small area that received the AT1/S.

Also, if reading is indicated, the data is read from the memory element corresponding to the address in the small area that received the atl bit in synchronization with the clock pulse.

Read data from the area.

C0 Prior Art and Problems Figure 1 shows a storage device that operates in on-pull mode.
is a storage area, 2 is an address register, 3 is an encoder,
4 indicates an at 1/s change register, and 5 indicates a data register. Note 11 Area 1 is divided into four small areas (0), (1), (2), and (3) (hereinafter referred to as small areas (0),
(1), (2), and (3)). The data register 5 is also divided into four parts corresponding to each small area of the storage area 1 (hereinafter referred to as registers (0), (1), (2), and (3)).

Fig. 2 shows a timing chart for each signal when writing to the storage device as shown in Fig. 1, and from the top it shows the free run clock timing (CLOCK), the storage device activation signal (MC; O), and the address signal. (ADH), write data signal (DIN).

Write/read selection signal (WT), column addressing signal (RAS), row addressing signal (CAS), 1 row address column address selection signal (SEL).

Indicates a write enable signal (WE).

If the capacity of the storage area is now 256kW, each small area (0)
The capacity of ~(3) is 64kw. The address signal (ADH) sent from the CPU has a capacity of 256k in storage area 1.
In the case of w, it consists of 18 bits (row address 9
(9 bits of bit string address, 18 bits in total).

By the way, when an address is given to storage area 1, the capacity of storage area 1 is 256 kW, but the capacity of each small area is 64 kW. Therefore, when trying to specify the address of the storage element in each small area, the address is 16 bits (row address 8 bits column address 8 bits).
bit) is enough. Then, the signal is sent from CPLJ to register 4, and then sent to register 4 via encoder 3.
The final bit of each of the 9 bits of the 9-bit row address and the 9-bit column address sent to is used as the address for specifying the small areas (0) to (3).

For example, if the final bit of the row address is 82, and the final bit of the column address is b, and both final bits are represented by (a, b), in the case of (0, O), the small area (0), (0,
In case of 1), small area (1).

In the case of (1, 0), the small area (2) is specified, and in the case of (1, I), the small area (3) is specified. When register 4 receives 9 bits of row address and 9 bits of column address from encoder 3, it changes the final bit of each in synchronization with the clock. For example, if the last bit of the row address and column address sent from encoder 3 is (0°0), register 4 will be (0,0)→(
The last bit is updated and specified in synchronization with the clock, such as 0°1)-(1,0)-(1,1).

The small area is changed, and the storage element of the small area is designated by the upper 8 bits of the row address and the upper 8 bits of the column address.

The register 5 is divided corresponding to small areas (0) to (3).

That is, the (0) area of register 5 for the small area (0), the (1) area of register 5 for the small area (1),
The (2) area of the register 5 corresponds to the small area (2), and the (3) area of the register 5 corresponds to the small area (3).

When data is sent from the CPU to register 5, register 5 receives the row address sent from register 4.

Based on the information of the last bit of the column address, data is stored in the area of the register corresponding to the designated small area, and then the data is written into the small area of storage area 1. for example,
If the final bits of the row address and column address are (0, O), when data is sent to register 5, the data is written to area (0).

The operation of the storage device shown in FIG. 1 will be explained using the timing chart shown in FIG. 2.

When the start signal (MGO> is sent from the CPU at to, the storage device starts writing or reading. At tI, an 18-bit address signal (ADH) is sent to register 2.
Since the selection signal (SF, L) indicates the column address at the time it is sent to the encoder 3, the 9 bits corresponding to the column address of the 18-bit address in the register 2 are sent to the encoder 3.
to register 4 via .

Since the selection signal (SET, ) indicates a row address at tZ, the row address is similarly sent from register 2 to register 4. Now, (a, b) of register 4 is (0
, O). When the first data is sent to register 5 at tZ, register 4 shows that (a, b) is (0
, O), it is temporarily written to register (0) corresponding to area (0). Column addressing signal (
RAS) falls at tl, so column addresses are continuously specified in storage area 1. Furthermore, when the row address designation signal (CAS) falls at t3, the row address is designated to storage area 1. Writable signal (W
Since E) indicates that writing is possible after tq, data is sent from register (0) to area (0) at t3, and writing is performed. When writing is completed, (a, b) of register 4 is updated to (0, 1). tl,t
Each time new data is sent to the storage device at 6°t8, writing is performed in areas (1), (2), and (3) using the same procedure.

Figure 3 shows a single clock (CLO) artificially created one pulse at a time in order to investigate the operation of storage devices, etc.
The signals synchronized with CK) are shown, starting from the top: memory device activation signal (MGO), address signal (ADR), and data signal (
DIN), which indicates the write/read selection signal (WT).

The period of this single clock is much larger than that of the free rank clock shown in FIG.

Incidentally, in such a storage device, the column address designation signal (RAS) and row address designation signal (CAS) must be synchronized with the free rank clock to perform normal operation.

Therefore, in order to investigate the operation of the storage device, a single clock was created and a single clock was used to send the address signal (ADR), data signal (DIN), write/read selection signal ( WT)
Even if the data is sent, the address designation signal (RAS), row address designation signal (CAS), row address column address selection signal (SEI, ), and l) write enable signal (WE) are synchronized to the free rank clock. Since it is very large in comparison, the row address 1 determination signal falls four times while one data is being sent (D T N). In other words, while one piece of data is being sent, the row address and column address are set in all areas (0) to (3), and the area (0) is
) to (3) are written with the same data.

41 OBJECTS OF THE INVENTION Accordingly, the present invention proposes a storage device that allows normal data writing and reading even during single clock operation.

00 Structure of the Invention Therefore, in the present invention, a storage area is divided into a plurality of small areas, one address is given from a host device, and data is sequentially sent by the number of the small areas in a certain period,
When control signals are sequentially sent as many times as the number of small areas in synchronization with the period, the small area is changed at each timing when the control signal is sent, and the storage element corresponding to the address of the small area is changed. In a storage device that writes data sent at the above-mentioned timing, if the period in which data is sent sequentially is larger than the period in which control signals are sent sequentially, only one of the control signals sent sequentially is valid, and one We propose a storage device control method that allows writing of only one piece of data into two small areas.

10 Embodiments of the Invention This embodiment shows a control method for a storage device as shown in FIG. 1 (storage area divided into four).

0 Figure 4 shows an embodiment of the present invention! A circuit for creating a write enable signal, a single row addressing signal, and a single column addressing signal used in the control method of the apparatus is shown, and FIG. 5 shows a timing chart of the present invention.

12.31.32 is OR game 1-, 29. 30.
33 to 36 are RS flip-flops 11 (hereinafter referred to as R3FF), 37 is a counter, and 38 is a selector.

FIG. 5 shows, from the top, a single clock, a first memory drive signal (MGO), and an address signal (ADR).

Data signal (DIN), write/read selection signal (W
T), (') Input free rank clock to R gate 11, input to OR gate 11, output of terminal 15, terminal 16
output, storage device second drive signal (SMGO), row addressing signal (RAS), column addressing signal (cAs)
, row address column address selection signal (RAS), row address column address selection signal (SEL), write enable signal (
WEO to WE3).

FIG. 6 shows a circuit 41 that generates a write enable signal, a 1-row address designation signal, and a 2-column address designation signal used during normal write/read operations, and a circuit 41 that generates a write enable signal, a 2-row address designation signal, and a 2-column address designation signal according to an embodiment of the present invention. A circuit 42 that generates designated signals and selectors 43 to 45 that select those signals are shown. Further, the circuit 42 has a structure as shown in FIG.

In this embodiment, the column address signal (C
Four types of write enable signals (WEO to WE3) are created that enable writing only when AS) falls once. For example, when the first data is sent, the WEO is set, and when the second data is sent, the WEI is set.
, when the third data is sent, WB2 is selected, and when the fourth data is sent, WB2 is selected. Then,
WEO corresponds to the first falling edge of CAS, WEI corresponds to the second falling edge of CAS, WB2 corresponds to the third falling edge of C1 As, and WB2 corresponds to the fourth falling edge of CAS. Therefore, even if the data is sent in synchronization with a single clock, the first data is sent to the small area (0) in Figure 1, the second data is sent to the small area (1), and the third data is sent to the small area (1) in Figure 1. The second data is written to the small area 1112(2), and the fourth data is written to the small area 113i(3).

In FIG. 4, signals are created as shown below.

DFFI-9 in FIG. 4 operate in synchronization with a single clock, and the other DFFs and R3FF operate in synchronization with a free rank clock.

τ When the storage device activation first signal (MGq) becomes “1”, DFF 1 is activated every time the sinkle clock advances by 1 clock.
"l" is output sequentially from 9 to 9.

OR gate 11. At DFFIO, OR gate 12°,
Every time "1" is input to the OR gate 11, a second memory activation signal (SMGO) is generated which is synchronized with the free rank clock and remains "1" for one clock.

3.2 DFFs 17 to 27 delay the storage device activation second signal (SMC; O) output from the OR gate 12 in synchronization with the free rank clock. R3FF29 uses the output of DFF17.27 to generate a row address designation signal (
RAS).

R3FF30 storage device activation second activation signal (SMGo)
, DFFs 18-25 are used to create a column addressing signal (CAS). R3FF33-36 are DFF
R3FF using the output of lB, 20, 22, 24.26
33 is WEO, R3FF34 is WEI, R3FF35 is WB2. The R3FF 36 creates four types of write enable signals <wEo-WB2) that indicate write enable only when a column address designation signal (CAS) such as WB2 falls once.

Based on the counter 37, the selector 38 selects four of the four types of write enable signals (WEO to WE3) when the first memory start signal (MGO) sent from the CPU (not shown) to the terminal 13 is "1". Then, each time the single clock advances by one clock, "1" is output from DFFs 1 to 9 in sequence. Among them, the outputs of DFFs 3, 5, and 7.9 are the inputs to the OR gate 11, so the inputs are As shown in the input to the OR gate 11 in FIG. 5, the signal becomes 1'' each time data (DIN) is sent in synchronization with a single clock pulse. The input to the OR gate 11 is “1” at first in ST3 (CTo)
Then, the output from the terminal 14 becomes 0''.

Also, since 0FFIO operates in synchronization with free rank 11, the output from terminal 15 is 1 at T1.
''.The OR gate 12 connects the LSI terminal 14 and the terminal 15.
The sum of the outputs is taken. Therefore, from terminal 16, 'ro
-T, a second storage device activation signal (SMGO) which becomes "1" only is output.

When the second storage device activation signal is input from the terminal 28, the DFFs 17 to 2 are activated every time the single clock advances by one clock.
"1" is sequentially output from 7 (DFF at T
The output of DFF17 is 1'', and the output of DFFlB at T2 is l''--m----).

In other words, the second storage device activation signal (SMGO) is D.
It is delayed by FFs 17-27.

Row addressing signal (RAS) is R3FF29 manual, D
Since the output of FF27 is used as the R input,! As shown in FIG. a, the signal becomes "0" between TlTl/.

A column addressing signal (CAS) is produced by R3FF30. R3FF30 is DFF19.21 2
3. The sum of the outputs of 25 is input to S, and the storage device second activation signal (
The R input is the sum of the outputs of SMGO) and DFFlB, 20, 22.24. Therefore, the output of R3FF30 becomes a signal as shown in FIG. 47 CAS.

A write enable signal (WEO) is created by R3FF33. R3FF33 receives the output of DFF185 (Tz-T, becomes "l") as S input and D
The output of the FF 20 (Tψ~T, becomes "1" and becomes "O".

Similarly, write enable signals (WEI), (WB2), (
WB2) is also created with R3FF34 and 35°36, respectively.

These storage device activation second signals (SMGO).

The row address designation signal (T?AS), the column address 1 determination signal (CAS), and the write enable signal (WEO to WE3) each time the output to the OR gate 11 becomes "1", that is, the data is Created each time one is sent.

One of the four types of write enable signals (WEO to WE3) created by the R3FFs 33 to 36 is selected based on the value of the counter 37.

The counter 37 is reset by the first storage device activation signal, and upon receiving the second storage device activation signal, increases its value by +1.
I'll go.

76 If the selector is WEO, if the value of counter 37 is “2”, it is WEO.
If the counter value is "3", WB2 is selected; if the counter value is "4", WB2 is selected.

The write enable signal created by the circuit 41 in FIG. 6 as described above. Row address specification signal. The column address designation signal is selected and used by selectors 43 to 45 only during a single clock. During normal free rank lock, the 6th
As shown in the figure, the normal write enable signal. Selectors 43 to 45 select and use the signals generated by the circuit 41 that generates the row address designation signal and the column address designation signal.

Note that the selection of circuits 41 and 42 in FIG. 6 is performed artificially using a selection signal.

g. Effects of the Invention According to the present invention, it is possible to obtain a nibble mode storage device that operates normally even when using a single clock.

[Brief explanation of the drawing]

B FIG. 1 shows the device 1a operating in nibble mode, 1
2 is a storage area, 2 is an address register, 3 &; t is an encoder, 2 is an address change l/raster, and 5 is a data register. Figure 2 is similar to Figure 1. The timing chart of each signal when writing 1M to a storage device is shown below.
Recording device start signal (MGO), address signal (AD
T? ), write data signal (r)IN) write/read 110~selection signal 1-J (WT) 1st column ALJ l/s specified information (RAS), row adreno, Ili specified information (CAS)
) 1st row address column address selection input (S l': L)
. Indicates a write enable signal (WTF, ). Figure 3 shows the operation of the equipment described in ↑a.
A single clock artificially created one pulse at a time (
8 signals with the same amount as C1, OCK) are shown, starting from the top: storage device activation signal 5 (Mco), address signal (ADR),
data signal (1) IN), τ1: write/read selection signal'; l1-(WT). FIG. 4 shows a circuit for creating a write enable signal, a one-row address designation signal, a one-column address designation signal used in a storage device control system according to an embodiment of the present invention, and FIG. 5 shows a timing chart of the present invention. show. 1 to 10 in Figure 4. and 17 to 27 are D flip-flops (hereinafter referred to as DFF), 11°12.31.
32 is an OR gate, 29. 30. 33-36 are RS
A flip-flop (hereinafter referred to as R3FF), 37 is a counter, and 38 is a selector. Figure 5 shows the single clock, storage device drive signal (from the top)
MGO), address signal (ADR), data signal (DI
N), write/read selection signal (WT), input free rank clock to OR gate 11, input to OR gate 11, output of terminal 15, output of terminal 16, memory device 2
Drive signal (SMGO), row address specification signal (RAS)
, column address designation signal (CAS), row address column address selection signal (RAS), write enable signal (WEO to W
]F, 3) is shown. 9 Figure 6 shows the write t+T fi13 Shinji 2 line A1! used during normal evening reading. L.S.1 statement 22
A circuit 41 for generating column addressing signals and a write enable signal 2 row addressing signal 1 according to an embodiment of the present invention.
Column a1'1/sli? A circuit 42 for generating constant signals and regulators 43 to 45 for selecting these signals -J are shown. 1 0 1st Figure 5Ttr 57+ 5T2 5T35T4 3T5 δ
rt sTy STa STYFigure 6 534-

Claims (1)

[Claims] The storage area is divided into a plurality of small areas, one address is given from the host device, and data is sequentially sent as many times as the number of the small areas in a certain cycle, and data is sequentially sent as many times as the number of the small areas in synchronization with the cycle. When a control signal is sent, the storage device changes the small area at each timing when the control signal is sent, and writes the data sent at the timing into a storage element corresponding to the address of the small area. If the period in which data is sent sequentially is greater than the period in which control signals are sent sequentially, only one of the sequentially sent control signals is valid, and writing of only one piece of data to one small area is permitted. A storage device control method characterized by: