JPH0822380A - Printer controller - Google Patents

Abstract

PURPOSE:To permit the performance of a device where CPU with plural bytes is aopted to sufficiently work so as to attain a high speed processing by simultaneously read plural kinds of data from first and second storage means. CONSTITUTION:A centronics connector 1 inputs a one-byte data N(N+1) and a strobe signal S from a host computer. A low-order byte register 2 and a high-order register 3 are arranged side by side in the succeeding stage of the centronics connector 1. The low-order byte register 2 stores data N when the strobe signal S falls (leading edge) and the high-order byte register 3 receives the inverted strobe signal S so as to store data N+1 when the strobe signal S rises (trailing edge). Then, the low-order register 2 and the high-order register 3 simultaneously output data N and data N+1 to CPU 7 at the time of receiving a data output signal 0 from CPU 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer controller, and more particularly to a printer controller having a Centronics interface.

[0002]

2. Description of the Related Art Conventionally, there is a technique as shown in FIG. FIG. 6 is a time chart of each signal of the printer controller. The printer controller is disposed between the host computer 200 and the printer, as shown in these figures, and converts 1-byte (8-bit) data D input from the host computer 200 via the Centronics connector 100. Latch circuit 1 in synchronization with strobe signal S
Stored in 01. In parallel with this operation, the busy register 103 to which the strobe signal S has been input inputs the H-level busy signal B to the host computer 200.

Then, the interrupt signal I is sent from the interrupt register 102 set by the strobe signal S to the CPU 201.
To the CP, which detects the interrupt signal I and which is not shown in the figure.
The read signal O is output to the latch circuit 101 from U201. When the read signal O is input, the data D is output from the latch circuit 101 to the CPU 201, and the CPU 2
01 confirms the reading of this data D, the CPU 2
From 01, the reset signal R is input to the busy register 103. When the reset signal R is input, the busy register 103 outputs an L level busy signal B to the host computer 200 to notify that the next data D can be received.

[0004]

Recently, a 16-bit or 32-bit CPU has been adopted for the host computer 200 and the printer controller in order to increase the processing speed. However, in the above-described conventional printer controller, 1-byte data D
And the 1-byte data D is transmitted to the CPU 201. Therefore, the transfer speed of the data D becomes a bottleneck, and the performance of each device employing the 16-bit or 32-bit CPU is sufficiently improved. There is a problem that it cannot be demonstrated.

[0005] A technique similar to the above-mentioned conventional printer controller is disclosed in Japanese Patent Application Laid-Open No. 1-121921. This technique is also configured to transfer 1-byte data. It does not solve the problem.

The present invention has been made in view of the above problems, and has as its object to provide a printer controller capable of transmitting and receiving a plurality of bytes of data.

[0007]

To achieve the above object, the present invention provides a printer controller having a Centronics interface for receiving data from a host computer, wherein the data synchronized with the leading edge of the sync signal from the host computer is used. For storing data synchronized with the trailing edge of the synchronization signal inverted by the inversion means, and a plurality of storage means stored in the first and second storage means. And a read-out means for reading out the data at the same time.

According to another aspect of the printer controller of the present invention,
The first storage means is formed by one or more first registers for storing the data when the synchronization signal falls, the inversion means is formed by an inverter, and the second storage means is formed by:
The read means is formed of one or more second registers for storing data at the rising edge of the synchronizing signal inverted by the inverter, and the read means has a plurality of bytes for simultaneously reading the plurality of data stored in the first and second registers. It has a configuration formed by a CPU.

According to a third aspect of the present invention, there is provided a printer controller comprising:
An interrupt register which is set at the rising edge of the synchronization signal and outputs an interrupt signal to the CPU and which is reset when an acknowledge signal from the CPU is input is provided. The CPU detects the interrupt signal from the interrupt register. Then, the data output signal is output to the first and second registers, and after reading out the data, an acknowledge signal is output to the host computer and the interrupt register.

According to a fourth aspect of the present invention, there is provided a printer controller comprising:
A busy register is provided for outputting to the host computer a busy signal which becomes H level when the synchronizing signal inverted by the inverter falls and becomes L level when the reset signal is input from the CPU.

[0011]

According to the printer controller, the data synchronized with the leading edge of the synchronizing signal from the host computer is stored in the first storage means and the data synchronized with the trailing edge of the synchronizing signal inverted by the inverting means. Are stored in the second storage means. Then, by the reading means, these first
And a plurality of data are simultaneously read from the second storage means.

According to the printer controller of the second aspect, the data synchronized with the falling edge of the synchronizing signal is stored in the first register, and the data synchronized with the leading edge of the synchronizing signal inverted by the inverter is stored in the second register. To be done.
Then, the plurality of data stored in the first and second registers are simultaneously read out by the CPU.

According to the printer controller of the third aspect, the interrupt register is set at the rising edge of the synchronization signal, and the interrupt signal is output to the CPU. When this interrupt signal is detected by the CPU, the data output signal becomes the first signal.
And the second register. Then, after reading the data, an acknowledge signal is output from the CPU to the host computer and the interrupt register, and the interrupt register that has received the acknowledge signal is reset.

According to the printer controller of the fourth aspect, when the synchronizing signal inverted by the inverter falls, H
A busy signal of a level is output from the busy register to the host computer. When a reset signal is input from the CPU, an L-level busy signal is output from the busy register to the host computer.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. First embodiment. FIG. 1 is a block diagram showing a printer controller according to a first embodiment of the present invention, and FIG. 2 is a time chart of each signal. The printer controller of the present embodiment shown in FIG. 1 is interposed between a host computer (not shown) and a printer, and is provided with a Centronics connector 1, a lower byte register 2 as a first register, and an upper byte register as a second register. 3, an interrupt register 5, a busy register 6, and a 16-bit CPU 7 connected to these circuits via a peripheral circuit (not shown).

The Centronics connector 1 receives 1-byte data N (N + 1) and a strobe signal S from a host computer. A lower byte register 2 and an upper byte register 3 are arranged side by side at the subsequent stage of the Centronics connector 1.

The lower byte register 2 is a register that receives the strobe signal S and stores data N when the strobe signal S falls (leading edge) as shown in FIGS. 2B and 2C. . On the other hand, an inverter 4 is provided in the preceding stage of the strobe signal S input side of the upper byte register 3, and the strobe signal S inverted by the inverter 4 is provided.
Are input to the upper byte register 3. As a result, the upper byte register 3 receives the inverted strobe signal S, and stores the data N + 1 at the rising edge (trailing edge) of the strobe signal S, as shown in (b) and (d) of FIG. Further, the lower byte register 2 and the upper byte register 3 have a data output signal O from the CPU 7 as shown in (h) and (i) of FIG.
When receiving the data, the data N and the data N + 1 are simultaneously output to the CPU 7.

The interrupt register 5 receives the strobe signal S and is set when the strobe signal S rises as shown in FIGS. 2 (b) and 2 (j).
It has the function of outputting to PU7. Then, as shown in (e) and (j) of FIG.
When the acknowledge signal A from the PU 7 is input, the reset is performed.

When the CPU 7 detects the interrupt signal I from the interrupt register 5, it outputs a data output signal O to the lower byte register 2 and the upper byte register 3 as shown in FIG. And the lower byte register 2
After the completion of the reading of the 2-byte (16-bit) data M containing the data N and N + 1 simultaneously output from the upper byte register 3 and the acknowledge signal A shown in FIG. 2E, the interrupt register 5 and the Centronics connector 1 is provided. Further, the CPU 7 outputs a reset signal R corresponding to the acknowledge signal A to the busy register 6, as shown in FIG.

As shown in (f) of FIG. 2, the busy register 6 becomes H level when the strobe signal S inverted by the inverter 4 falls, and becomes L level when the reset signal R is input from the CPU 7. It has a function of transmitting the busy signal B to the host computer via the Centronics connector 1.

Next, the operation of this embodiment will be described.
1-byte data N (N +
1) and the strobe signal S are connected to the Centronics connector 1
When input to the printer controller via, the data N is stored in the lower byte register 2 when the strobe signal S falls, and the data N + 1 is stored when the strobe signal S inverted by the inverter 4 rises (FIG. 2). (B) to (d)).

In parallel with this operation, the interrupt register 5 is set when the strobe signal S rises, and the interrupt signal I is output to the CPU 7 (see (b) and (j) in FIG. 2). Then, the data output signal O is output from the CPU 7 that has detected the interrupt signal I to the lower byte register 2 and the upper byte register 3 (see (h) of FIG. 2).

When the data output signal O is input to the lower byte register 2 and the upper byte register 3, data N and data N + 1 are simultaneously output to the CPU 7 (see (h) and (i) of FIG. 2). . That is, 2-byte (16-bit) data M containing the data N and N + 1 simultaneously output from the lower byte register 2 and the upper byte register 3 is read into the CPU 7. As described above, since the 2-byte data M can be transmitted to the 16-bit CPU 7, the performance of the apparatus employing the 16-bit CPU 7 can be sufficiently exhibited, and the processing speed can be increased. it can.

When the CPU 7 finishes reading the data M, the acknowledge signal A is output to the interrupt register 5 and the Centronics connector 1, and the interrupt register 5 is reset when the acknowledge signal A falls ((e in FIG. 2). ) And (j)). In parallel with this operation, the reset signal R corresponding to the acknowledge signal A is output from the CPU 7 to the busy register 6 (see (g) in FIG. 2). As a result, as shown in (f) of FIG. 2, the busy signal B, which has been at the H level at the fall of the strobe signal S inverted by the inverter 4, becomes the L level and is transmitted to the host computer. Informs the host computer that it is ready to receive the next data.

Second embodiment. FIG. 3 is a block diagram showing a printer controller according to a second embodiment of the present invention. The same elements as those in FIG. 1 will be described with the same reference numerals. The first embodiment is that the 32-bit CPU can read 4-byte data.
Different from the embodiment.

In this embodiment, the data output signal input terminals of the registers 2 and 3 are grounded, and the registers 8 and 9 are connected in series to the output terminals of the registers 2 and 3, respectively. Similarly to the register 2, the register 8 has its data output signal input terminal grounded and receives a strobe signal S 'from its synchronization signal input terminal. The register 8 inputs data from the register 2 when the strobe signal S 'falls. The register 9 has a data output signal input terminal grounded similarly to the register 3, and receives the strobe signal S 'via the inverter 4. Then, the register 9 inputs the data from the register 3 when the strobe signal S ′ rises.

On the output side of such registers 8 and 9,
A buffer 10 is provided. This buffer 10
It has a function of storing the output data from the registers 8 and 9 and the output data from the registers 2 and 3. CPU 7 '
Is a 32-bit CPU. By outputting a data output signal O to the buffer 10, the data stored in the buffer 10 is read out at the same time, and the 4-byte data M '
Is output as.

Next, the operation of this embodiment will be described.
FIG. 4 is a flowchart showing the operation. As shown in FIGS. 3A and 3B, two strobe signals S ′ continuous with data N, N + 1, N + 2, and N + 3 are output from the Centronics connector 1 to the registers 2 and 3.

In the register 2, the strobe signal S
Since the data N and N + 2 are sequentially stored in synchronism with the trailing edge of ‘′, as shown in (g) of FIG.
The previous data X and data N are sequentially output, and finally data N + 2 is output. The register 8 sequentially stores the data X and N from the register 2 in synchronization with the falling edge of the strobe signal S 'as shown in FIG. 4 (i). Is output.

As a result, data N + 2 from register 2
Is output to the buffer 10 and the data N
Is output to the buffer 10. The same operation as that of the registers 2 and 8 is performed in the registers 3 and 9, and FIG.
As shown in (j) and (j), data N + 3
Is output to the buffer 10 and the data N is output from the register 9.
+1 is output to the buffer 10.

In this way, data N, N + 1, N + 2, N
The buffer 10 storing +3 stores these data N, when the data output signal O from the CPU 7 ′ is input.
N + 1, N + 2, N + 3 are simultaneously written in 4-byte data M '
To the CPU 7 '. As described above, according to this embodiment, the 4-byte data M ′ is converted into the 32-bit CPU 7 ′.
Can be transmitted to the 32-bit CPU 7 '.
Can fully demonstrate the performance of this device that employs
The processing speed can be increased. The rest of the configuration, functions and effects are similar to those of the first embodiment, so the description thereof is omitted.

[0032]

As described above, according to the printer controller of the present invention, a plurality of data are simultaneously read from the first and second storage means. That is, when each data is set to 1 byte, a plurality of bytes of data are read at the same time, so that the performance of an apparatus employing a CPU of a plurality of bytes can be sufficiently exhibited and the processing can be speeded up. Has an excellent effect.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a printer controller according to a first embodiment of the present invention.

FIG. 2 is a time chart of each signal in the first embodiment.

FIG. 3 is a block diagram illustrating a printer controller according to a second embodiment of the present invention.

FIG. 4 is a time chart diagram of each signal in the second embodiment.

FIG. 5 is a block diagram showing a printer controller according to a conventional example.

FIG. 6 is a time chart illustrating signals of a printer controller according to a conventional example.

[Explanation of symbols]

 1 Centronics connector 2 Lower byte register 3 Upper byte register 4 Inverter 5 Interrupt register 6 Busy register 7 CPU

Claims (4)

[Claims] 1. A printer controller having a Centronics interface for receiving data from a host computer, comprising: first storage means for storing data synchronized with a leading edge of a synchronization signal from the host computer; A second storage means for storing data synchronized with the trailing edge of the synchronization signal; and a reading means for simultaneously reading the plurality of data stored in the first and second storage means. Printer controller. 2. The first storage means is formed by one or more first registers for storing the data at the falling edge of the synchronization signal, and the inverting means is formed by an inverter, and the second storage means. Is formed of one or more second registers for storing data at the rising edge of the synchronizing signal inverted by the inverter, and the reading means is configured to simultaneously read the plurality of data stored in the first and second registers. The printer controller according to claim 1, wherein the printer controller is formed by a CPU of a bite. 3. An interrupt signal which is set when the synchronizing signal rises and which outputs an interrupt signal to the CPU;
When an interrupt signal from the interrupt register is detected, the CPU outputs an output signal to the first and second registers to read the data. The printer controller according to claim 2, further comprising a function of outputting an acknowledge signal to the host computer and the interrupt register later. 4. A busy register is provided for outputting to the host computer a busy signal which becomes H level when the synchronizing signal inverted by the inverter falls and becomes L level when a reset signal is input from the CPU. Item 3. The printer controller according to Item 3.