JP2001117865A - Method for transferring data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency by transferring variable length data by a simple command in data transfer between independent processors. SOLUTION: At least one byte data and succeeding one byte address data are transferred to a DSP4. The DSP4 holds transferred data by data shift registers 12 and 13 at every byte. A writing signal creating circuit 15 creates a writing signal corresponding to the number of bytes of the data based on transferred address data and an LD signal, fetches data of the byte number corresponding to the signal from the data shift registers 12 and 13 into latch circuits 16 and 17 and outputs them to a circuit A or B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method between ICs, and more particularly, to a synchronous serial data transfer method for transferring data between a digital signal processor and a microprocessor.

[0002]

2. Description of the Related Art Conventionally, data transfer between independent processors has been performed in a data processing process of various electronic devices. For example, in an image processing apparatus such as a video camera, a digital signal processor (hereinafter referred to as DSP) and a microprocessor (hereinafter referred to as CPU) exchange digital data synchronously with each other in order to exchange data relating to various types of signal processing. Data transfer by the system is performed.

In such data transfer by the synchronous serial system, for example, one address is associated with one byte (or several bytes) of data. That is, when data is transferred from one processor to the other processor, one byte of fixed-length data and one byte of address data are transferred as a set.

[0004]

In the data transfer in which the data is fixed length as described above, for example, if one byte is constituted by one address, when transferring 10 byte data, 20 bytes including the address are transferred. Need to transfer. Therefore, when there is a large amount of data to be set in a large-scale LSI, the address data becomes 1 byte or more, so that the transfer efficiency is deteriorated and the transfer cannot be performed at high speed.

[0005] Further, in the case where data of several bytes is transmitted in one address, for example, in the case of data of 10 bytes in one address, it is sufficient to transfer 11 bytes including the address. improves. However, among the data used for the DSP, there are data having a large data amount such as lookup table data, and data requiring only one bit for turning on / off a function such as control data. Therefore, in the above method, even when 1-bit data is transferred, 11-byte data must be transferred, and there is a problem that transfer efficiency is deteriorated.

Further, in data transfer with variable length data, no extra bits are transferred, so that transfer efficiency can be improved. However, in this method, it is necessary to transfer information on the number of bits of data at the same time, so that there is a problem that commands become complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transfer method that enables variable-length data transfer with a simple command and improves data transfer efficiency.

[0008]

To achieve the above object, a data transfer method according to the present invention comprises first and second data transfer methods.
In the data transfer method for serially transferring data in synchronization with a predetermined clock signal between the processors, the first processor may be configured to identify m (≧ 1: natural number) × n-bit data and this data. In the second processor, the transferred m × n-bit data is held by m shift registers for every n bits, and
An identification signal of the data is generated based on the transferred data identification information, and the m signal specified by the identification signal is generated.
The m × n-bit data is transferred from a plurality of shift registers to a predetermined circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a data transfer method according to the present invention is applied to an internal circuit of a video camera will be described below.

FIGS. 5A and 5B are block diagrams showing a functional configuration of a video camera according to this embodiment.

In the video camera 10 shown in FIG.
The analog processing unit 2 performs various corrections on the R, G, and B video signals captured by the CCD 1, and performs an A / D conversion unit 3.
After that, the digital signal processor (DSP) 4 performs various kinds of signal processing, and further converts the digital signal into digital signals.
The luminance / color difference signals (Y, Pb, Pr) are output by converting the signals into analog signals by the A conversion unit 5. Where DS
Data transfer is performed between the P4 and the microprocessor (CPU) 6 by digital data in a synchronous serial system.

FIG. 5B shows the connection between the DSP 4 and the CPU 6.
Are connected by four signal lines as shown in FIG. In the figure, S
CK is a clock signal for data transfer, SDI is CP
Data (serial data) sent from U6 to DSP4, SDO is data sent from DSP4 to CPU6 (serial data), LD is to latch data transferred from CPU6 to DSP4, or to transfer data of DSP4 to CPU6. Are respectively shown.

FIG. 1 is a block diagram showing a configuration of a portion for writing data in the DSP 4. As shown in FIG. Here, a configuration in a case where data having different numbers of bits are transferred from the CPU 6 (FIG. 5) to the circuits A and B in the DSP 4 is shown.

Data writing to the circuits A and B of the DSP 4 is realized by the address shift register 11, the data shift register 12, the address shift register 13, the address decoder 14, the write signal generation circuit 15, the latch circuit 16, and the shift register 17. I have.

The address shift register 11 includes a CPU
6, the data and address data transferred from the memory 6 are fetched, and the data is shifted one bit at a time to the data shift register 12 at the subsequent stage in synchronization with SCK.

The data shift registers 12 and 13 are:
The data transferred from the address shift register 11 is shifted one bit at a time in synchronization with SCK. This shift register outputs 8-bit parallel data.

The address decoder 14 decodes the address data sent from the address shift register 11 and supplies an "L" or "H" signal to the write signal generation circuit 15 from the signal line 1 or 2.

The write signal generation circuit 15 includes AND circuits 21 and 22 and a NOT circuit 23.
The LD signal input from the CPU 6 is inverted by the NOT circuit 23 and then input to one input terminal of the AND circuits 21 and 22. Further, the other input terminals of the AND circuits 21 and 22 are connected to the signal lines 1 and 2 of the address decoder 14, respectively, and a "L" or "H" signal is input. According to this, when the LD signal is “L” (the input to the AND circuit is “H”) and the signal level from the address decoder 14 is “H”, the output level of the AND circuit becomes “H”, A write signal is output. The write signals output from the AND circuits 21 and 22 are input to the corresponding latch circuits 16 and 17, respectively.

The latch circuits 16 and 17 take in data from the data shift register 12 or 13 in accordance with the write signal output from the write signal generation circuit 15 and write the data to the circuit A or the circuit B at a predetermined timing.

The circuits A and B are signal processing circuits arranged in the DSP 4, and input data of different numbers of bytes. In this embodiment, one-byte data is written to the circuit A, and the address for writing is "1". Two-byte data is written to the circuit B, and the address for writing is "2". ". Although many signal processing circuits are arranged in an actual DSP, an example in which two types of circuits having different data amounts are arranged is shown here for the sake of simplicity.

Next, the procedure for transferring (writing) the data of the CPU 6 to the DSP 4 will be described with reference to the block diagram of FIG. 1 and the time chart shown in FIG.

First, the CPU 6 sends a signal 1 to the circuit A of the DSP 4.
A case where byte data is transferred will be described.

When data is transferred from the CPU 6 to the DSP 4, the CPU 6 sends SDI (data) in synchronization with SCK. In the CPU 6 of this embodiment, data is transferred in the order of data first, and then address. More specifically, as shown in FIG. 2, after sending 1-byte data first,
Byte address data (data identification information) is sent, and an LD signal for notifying the write timing is sent.

The data sent from the CPU 6 with such a data structure is taken into the address shift register 11 of the DSP 4 and shifted right by one bit in synchronization with the rising edge of SCK. In this example, since the data is one byte and the address is one byte (16 bits in total), one byte of data passes through the address shift register 11 and is set in the data shift register 12 at 16 SCK clocks. You. At the same time, 1-byte address data transmitted following the data is set in the address shift register 11, and the 1-byte address data is input from the address shift register 11 to the address decoder 14 as parallel data. . Since this address data is "1", in the address decoder 14, only the signal line 1 is at "H" level, and the other signal lines are at "L" level. When the LD signal becomes “L”, the write signal generation circuit 15
A write signal (data identification signal) is output from the D circuit 21 to the latch circuit 16 and the data shift register 12
Is sent to the latch circuit 16. Here, since only the latch circuit 16 outputs the write signal, no data is sent to other latch circuits.

Thus, the one-byte data transferred from the CPU 6 is written from the latch circuit 16 to the circuit A.

Next, the CPU 6 sends a signal 2 to the circuit B of the DSP 4.
A case where byte data is transferred will be described.

In this example, when data is transferred from the CPU 6 to the DSP 4, after transmitting 2 bytes of data first,
Subsequently, a one-byte address is transmitted, and an LD signal for notifying the write timing is transmitted.

The data sent from the CPU 6 is a DSP
4 is taken into the address shift register 11 and SC
The data is shifted right by one bit in synchronization with the rising edge of K. In this example, since the data is 2 bytes and the address is 1 byte (24 bits in total), the SCK 2
One byte of data is set in the data shift register 12 and the data shift register 13 at four clocks. At the same time, 1-byte address data transmitted following the data is set in the address shift register 11.
Is input to the address decoder 14 as parallel data. Since this address data is "2", in the address decoder 14, only the signal line 2 is at "H" level, and the other signal lines are at "L" level. When the LD signal becomes “L”, a write signal is output from the AND circuit 22 of the write signal generation circuit 15 to the latch circuit 17, and the 2-byte data set in the data shift register 12 and the data shift register 13 is output. Data is sent to latch 17. here,
Since only the latch circuit 17 outputs a write signal, no data is sent to another latch circuit.

Thus, the 2-byte data transferred from the CPU 6 is written from the latch circuit 17 to the circuit B.

The CPU 6 to the DSP 4 according to this embodiment
It is possible to perform data transfer from one byte to several bytes per address in the same manner as the variable-length data transfer while using the same simple command as the fixed-length data transfer. Transfer efficiency can be improved.

Although this embodiment does not show a specific example of a protocol or a command at the time of data transfer, it is possible to omit the exchange of a command relating to the number of bits of data.

Next, a procedure for transferring (reading) the data of the DSP 4 to the CPU 6 will be described.

FIG. 3 is a block diagram showing a configuration of a portion for reading data in the DSP 4. As shown in FIG. Here, data from the circuits A, B, and C in the DSP 4 are
6 is shown.

In the circuit shown in FIG. 3, since the address shift register is also used for writing data, it is given the same reference numeral as in FIG.

Data reading from the circuits A, B, and C of the DSP 4 is realized by the address shift register 11, data selector 24, NOT circuit 25, latch circuit 26, and parallel / serial conversion circuit 27.

The data selector 24 selects the detection data (X bytes) output from the circuits A, B and C according to the address data from the address shift register 11 and outputs the same to the latch circuit 26.

The latch circuit 26 fetches data from the data selector 24 in accordance with the LD signal inverted by the NOT circuit 25 and transfers the data to the parallel / serial conversion circuit 27 at a predetermined timing.

The parallel / serial conversion circuit 27 has a CP
The data fetched from the latch circuit 26 is converted from parallel / serial in synchronization with the SCK from U6, and is output to the CPU 6 as SDO of serial data.

Next, the procedure for transferring (reading) the data of the DSP 4 to the CPU 6 will be described with reference to the block diagram of FIG. 3 and the time chart shown in FIG.

When transferring data from the DSP 4 to the CPU 6, the CPU 6 sends the SDI in synchronization with the SCK, but in the case of reading, only the address data is sent. This address data is converted into 1-byte parallel data by the address shift register 11, and then converted to a data selector 2.
4 is output. The data selector 24 includes a circuit A,
X bytes of data are collected from B and C, and predetermined data is selected by the address data from the address shift register 11. And the selected data is
The data is taken into the latch circuit 26 in accordance with the LD signal inverted by the NOT circuit 25, and further taken into the parallel / serial conversion circuit 27 in synchronization with the SCK from the CPU 6. In the parallel / serial conversion circuit 27, the data fetched from the latch circuit 26 is parallel / serial converted and output to the CPU 6 as SDO of serial data.

As described above, in the data transfer from the DSP 4 to the CPU 6, the same simple command as in the fixed length data transfer is used, and the data from one byte to several bytes per address is used in the same manner as the variable length data transfer. Transfer can be performed, and data transfer efficiency can be improved.

It should be noted that X bytes of SCK are required for data reading, and the SD output from the DSP 4 is required.
O also becomes data of the same length. Therefore, depending on the address, bits may be left, and not all bits may be valid. In such a case, useless bits can be reduced by determining an effective bit length for each address and handling only data of that length.

[0043]

As described above, in the data transfer method according to the present invention, a write signal (data identification signal) corresponding to the data length is generated, and only the data corresponding to the write signal is output to the internal circuit. Therefore, it is possible to perform the same data transfer with the variable length with the same simple command as the data transfer with the fixed length of data, thereby improving the data transfer efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a portion for writing data in a DSP.

FIG. 2 is a time chart when transferring (writing) data of a CPU to a DSP.

FIG. 3 is a block diagram showing a configuration of a portion for reading data in a DSP.

FIG. 4 is a time chart when transferring (reading) DSP data to a CPU.

FIG. 5 is a block diagram showing a functional configuration of the video camera according to the embodiment.

[Explanation of symbols]

 Reference Signs List 4 DSP 6 CPU 11 Address shift register 12, 13 Data shift register 14 Address decoder 15 Write signal generation circuit 16, 17, 26 Latch circuit 24 Data selector 27 Parallel / serial conversion circuit

Claims (1)

[Claims] 1. A data transfer method for serially transferring data between a first processor and a second processor in synchronization with a predetermined clock signal, wherein the first processor includes m (≧ 1) × n-bit data. And n bits of data identification information for identifying this data are transferred in combination. In the second processor, the transferred m × n bits of data are transferred by m shift registers every n bits. Holding and generating an identification signal of the data based on the transferred data identification information, and transferring the m × n-bit data from the m shift registers specified by the identification signal to a predetermined circuit. A data transfer method, wherein the data is transferred.