JPH01315849A - Information processor - Google Patents

Abstract

PURPOSE:To transfer data from a main memory to a cache memory without being restricted with the bus width of the data bus of a central processor by connecting the main memory to the cache memory by means of the extended data bus at the broader width than that of the data bus to send the data to the central processor. CONSTITUTION:The data stored into a main memory 3 and a cache memory 2 are read through a data bus 6 at an (n) bit width by a central processor 1, and the main memory 3 is connected to the cache memory 2 by an extended data bus 7 at an (m) bit width (m>n). For example, the bus width of the data bus 6 is of 32 bits, and the bus width of the extended data bus 7 is of 64 bits. A multiplexer 4 extracts the data at 32 bits required by the central processor 1 out of the data at 64 bits on the extended data bus 7 by a control signal 102 from a controller 5, and sends them through the data bus 6 to the central processor 1. Thus, without being restricted by the bus width of the data bus 6 of the central processor 1, the data can be transferred from the main memory 3 to the cache memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to a data transfer method between a central processing unit and a main memory and cache.

Conventionally, in this type of information processing apparatus, a central processing unit 1, a cache 2, and a main memory 3 are connected by a data bus 6, respectively, as shown in FIG.

When the central processing unit 1 reads data stored in the main memory 3, it first checks whether the target data is stored in the cache 2, and if the target data is stored in the cache 2, it is checked. The target data is read directly from the cache 2 as a cache hit. At this time, the central processing unit 1 does not access the main memory 3.

Furthermore, if the target data is not stored in cache 2, a cache miss occurs and the target data is read from main memory 3, and at the same time, the data read from main memory 3 is written to cache 2. It will be done.

In such conventional information processing devices, when a cache miss occurs, data read from main memory 3 is written to cache 2; There is a drawback that the data that can be stored is limited by the bus width of the data bus 6, and furthermore, the bus width of the data bus 6 is limited by the bus width of the data bus of the central processing unit 1.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and is to transfer data from the main memory to the cache memory without being limited by the bus width of the data bus of the central processing unit. Proposal of an information processing device that can
Aiming at I-.

Structure of the Invention An information processing device according to the present invention is an information processing device in which data stored in a main memory and a cache memory is read out by a central processing unit via a data bus having a width of n bits (n is a positive integer). m bit width (m is a positive integer, m>n
), and extraction means for extracting n-bit data from m-bit data on the extended data bus and transferring it to the central processing unit in response to a control signal from the central processing unit. It is characterized by

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 6, an information processing device according to an embodiment of the present invention includes a central processing unit 1, a cache 2, a main memory 3, and a multiplexer. 4 and a controller 5.

Central processing unit 1 is connected via data bus 6 and multiplexer 4 to cache 2 and main memory 3, which are interconnected by expansion data bus 7. Here, the bus width of the data bus 6 is 32 bits, and the bus width of the extended data bus 7 is 64 bits.

Multiplexer 4 receives control signal 10 from controller 5
2 extracts the 32-bit data required by the central processing unit 1 from the 64-bit data on the extended data bus 7, and sends this 32-bit data to the central processing unit 1 via the data bus 6.

The controller 5 decodes the status signal 101 from the central processing unit 1 and decodes the 32 status signals required by the central processing unit 1.
A control signal 102 for loading only bit data from the expansion data bus 7 onto the data bus 6 is sent to the multiplexer 4.
Output to.

When the central processing unit 1 attempts to read 4 bytes (32 bits) of data from address 0 of the main memory 3, if a cache miss occurs in the cache 2, the access to the main memory 3 by the cache 2 causes the main 64-bit data is read from address 0 of memory 3.

Here, it is assumed that when main memory 3 is accessed to read data, 64-bit data is always output from main memory 3.

That is, since 1 byte of data is stored at each address in the main memory 3, the main memory 3 always outputs data for 8 consecutive addresses.

64-bit data from address 0 read from main memory 3 is written into cache 2 via expansion data bus 7. At this time, the controller 5 decodes the status signal 101 from the central processing unit 1 and outputs the control signal 102 to the multiplexer 4. Therefore, the multiplexer 4 needs to input the 64-bit data on the expansion data bus 7 to the central processing unit 1. 32-bit data (32-bit data from address 0 of main memory 3) is taken onto data bus 6, and this 32-bit data is sent to central processing unit 1 via data bus 6. Therefore, the central processing unit 1 can read only necessary data.

Furthermore, when central processing unit t attempts to read 32-bit data from address 4 of main memory 3 in the next read cycle, the 32-bit data from address 4 of main memory 3 has already been written to cache 2. Therefore, the cache 2 generates a cache hit and 64-bit data from address 0 of the main memory 3 is output onto the expansion data bus 7.

The 64-bit data on the expansion data bus 7 is converted into 32-bit data (32-bit data from address 4 of the main memory 3) required by the central processing unit 1 by the multiplexer 4 to which the control signal 102 from the controller 5 is input. data) is taken onto the data bus 6, and this 32-bit data is sent to the central processing unit 1 via the data bus 6.

Therefore, the central processing unit 1 can read only 32-bit data from address 4 of the main memory 3.

In this way, the bus width (3
The cache 2 and the main memory 3 are connected by an expansion data bus 7 having a bus width (64 bits) twice that of the 64-bit data bus (64 bits). By allowing the multiplexer 4 to extract only the 32-bit data to be processed, data can be transferred from the main memory 3 to the cache 2 without being limited by the bus width of the data bus of the central processing unit 1. .

Therefore, in the event of a cache miss in the cache 2, data that is twice the bus width of the data bus that the central processing unit 1 can access can be written to the cache 2 in one access. 1
When reading data from consecutive addresses in the main memory 3, the cache 2 will always receive a cash hit in the next read cycle, so the central processing
processing efficiency can be improved.

In addition, when data sequentially output from the main memory 3 block by block is written to the cache 2, the data bus width of the expansion data bus 7 is wide enough to
The time required for data read out block by block from the main memory 3 can be reduced.

In one embodiment of the present invention, the bus width of the extended data bus 7 is twice the bus width of the data bus 6, but it may be any number of times wider than the bus width of the data bus 6. Not limited.

As explained above, according to the present invention, a data bus with a width of n bits (n is a positive integer) for sending data stored in the main memory and cache memory to the central processing unit is used. The main memory and cache memory are connected by a wide m-bit width (m is a positive integer, m>n) expansion data bus, and n-bit data is extracted from the m-bit data on this expansion data bus. By sending the data to the central processing unit, data can be transferred from the main memory to the cache memory without being limited by the bus width of the data bus of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1...Central processing unit 2...Cache 3...Main memory 4...Multiplexer 5...Controller 6 ...Data bus 7...Extension data bus

Claims (1)

[Claims] (1) An information processing device in which data stored in a main memory and a cache memory is read by a central processing unit via an n-bit wide data bus (n is a positive integer),
an m-bit wide (m is a positive integer, m>n) expansion data bus that connects the main memory and the cache memory;
An information processing apparatus characterized by having an extraction means for extracting n-bit data from m-bit data on the expansion data bus and transmitting the extracted data to the central processing unit in response to a control signal from the central processing unit. .