JPH08166932A - Multiprocessor system - Google Patents

Abstract

PURPOSE: To reduce the number of reception registers, to shorten time for recognizing all the reception registers and to improve the speed of data communication by permitting CPU to access to a common memory in response to an ID number in the reception register, to read data and to reset a write part corresponding to the ID number. CONSTITUTION: For transmitting data from plural processor units 1 and 2 to a processor unit N, for example, the respective transmission source processor units 1 and 2 store data in the designated area of the common memory M and transmit the ID number to the reception register N2 of the reception transmission processor unit N. The reception register N2 receives the two ID numbers, and CPU.N1 of the reception destination processor unit N receives an interruption notice by the ID number which is previously received. Thus, CPU.N1 of the reception destination processor unit N takes in the ID number of the reception register N2, accesses to the common memory M in response to the ID number, reads data and resets the write part corresponding to the ID number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system for performing data communication between a plurality of processor units using a common memory.

In recent years, in communication and control computers, a multiprocessor system capable of efficiently performing data processing has become necessary with the demand for high reliability and high speed processing.

[0003]

2. Description of the Related Art A conceptual diagram of a conventional multiprocessor system is shown in FIG.
~ N are interconnected via the system bus SB,
A common memory is also connected to the system bus SB.

Each of the processor units 1 to N is a CP.
Supports U11-N1 and other processor units (N
-1) Reception registers RR1 to RR including one register group
N (see FIG. 8).

The operation of this conventional example will be described below with reference to FIGS. 7 and 8. FIG. 7 shows a sequence when data is transmitted from the source processor unit to the destination processor unit.
When performing data communication between 2, ..., N, a unique ID number is assigned to each processor unit.

For example, when data is transmitted from the source processor unit 1 to the destination processor unit N, the CPU 11 of the source processor unit 1 sends a write signal (FIG. 6) to the system bus SB to send a common memory. The data is stored in the designated area of M (S1 in FIG. 7).

CPU 1 of the processor unit 1 of the transmission source
1 transmits the assigned unique ID number () to the reception register RRN of the processor unit N of the reception destination (S2).

When the receiving register RRN of the receiving destination processor unit N receives the ID number from the processor unit 1 (S3), it writes it in the corresponding register portion as shown in FIG.

When the ID number is written, the reception register RRN sends an interrupt notification () to the CPU N1 of the processor unit N, and the CPU N1 receives the reception register RR.
Confirm the contents of N with the read signal () (S40),
The data stored for the processor unit 1 is fetched from the designated area of the common memory M (S5).

After reading the data, the CPU N1 resets the reception register RRN.

[0011]

In the conventional multiprocessor system, when data communication is performed among a plurality of processor units 1 to N as shown in FIG. 6, the unique ID number of the data transmission source is used. Since the receiving register of the receiving destination processor unit holds it, the receiving register of each processor unit corresponds to another processor unit (N-
1) It was necessary to have a register group.

When a unique ID number is received from a plurality of processor units, the CPU in the receiving destination processor unit that has received the interrupt notification from the reception register determines from which processor unit the interrupt notification is from. Since it is necessary to check the contents of all the register groups in the reception register in order to discriminate, there is a problem that it takes time to receive data from the common memory M.

Therefore, according to the present invention, a plurality of processor units each having a unique ID number are connected to each other via a system bus, and a common memory is connected to the bus so that one processor unit can be connected to another processor unit. When transmitting the data, the processor unit of the transmission source transmits the data to the common memory and the ID number of the transmission source to the processor unit of the reception destination, and the processor unit of the reception destination transmits the ID number of the transmission source. In a multiprocessor system which receives data from the common memory according to an ID number, the number of receiving registers in the processor unit is reduced to shorten the time for checking all receiving registers and improve the speed of data communication. The purpose is to

[0014]

To achieve the above object, in a multiprocessor system according to the present invention, as shown conceptually in FIG.
One including a writing unit corresponding to the ID number and an OR circuit for issuing an interrupt notification to the CPUs 11 to N1 in the processor unit when one or more unique ID numbers are written in the writing unit. The reception registers 12 to N2 are provided, and the CPU corresponds to the ID number in the reception register and the common memory M
Is accessed to read the data, and at the same time, the writing unit corresponding to the ID number is reset.

Further, in the present invention, preferably, the above-mentioned writing section holds a first AND circuit for inputting a write command and data from the bus SB and an output of the first AND circuit, respectively. F / F section given to the OR circuit and the CPU
A gate circuit for giving the output of the F / F section to the CPU by a read signal from the CPU, a write signal generated when the CPU reads data from the common memory M, and each writing section. And a second AND circuit for inputting a reset signal to the F / F section and resetting the F / F section.

[0016]

In the multiprocessor system shown in FIG. 1, when transmitting data from the source processor unit 1 to the destination processor unit N, the source processor unit 1 specifies the data in the common memory M. The data is stored in the area (; S1 in FIG. 4), and at the same time, the unique ID number of the transmission source processor unit 1 is transmitted to the reception register N2 of the reception destination processor unit N via the system bus SB (; S2).

The reception register N2 of the destination processor unit N writes the ID number of the source processor unit 1 as conceptually shown in FIG. 2 (S3).

Since each processor unit confirms the ID number of only one reception register (S4), it is not necessary to have (N-1) reception registers corresponding to the number of other processor units, and one reception register is required. Just register.

Further, for example, when data is transmitted from the plurality of processor units 1 and 2 to the processor unit N, the respective source processor units 1 and 2 store the data in designated areas of the common memory M, respectively. (; S
At the same time as 1), the ID number is transmitted to the reception register N2 of the reception destination processor unit N (; S2).

The reception register N2 receives two ID numbers as conceptually shown in FIG.
Since the number and the next received ID number are OR conditions, the CPU / N1 of the receiving destination processor unit N receives an interrupt notification according to the ID number received first ().

As a result, the CPU N1 of the receiving processor unit N fetches the ID number of the receiving register N2 (), and correspondingly accesses the common memory M to read the data (; S5). At the same time, the writing unit corresponding to the ID number is reset.

Therefore, after that, the data is similarly read in the writing section of the reception register N2 which is not reset and remains.

[0023]

FIG. 5 shows an embodiment of the multiprocessor system according to the present invention shown in FIG. 1. In particular, the reception register N2 used in the processor unit N in FIG.
It shows the details of.

That is, the basic structural difference between this embodiment and the conventional example of FIG. 6 lies in the reception register in each processor unit.

The conventional receiving register corresponds to the number of each processor unit to which a unique ID number is given (N-
1) is provided with a register group, whereas the receiving register of the present embodiment has only one receiving register composed of the write units b1 to b (N-1) and has a unique ID number possessed by each processor unit. It is stored in association with (N-1) bits.

In other words, the conventional processor unit has the reception registers shown in FIG. 5 for other processor units.

Each processor unit, that is, the processor unit N, receives writing numbers b1 to b (N-1) for receiving ID numbers unique to the other processing units, and writing units (b1 to b (N- 1) and an OR circuit 10 which takes the logical sum of the interrupt signals from 1) and gives it to the CPU N1. The writing sections b1 to b (N-1) are respectively connected to the bus S.
First AND circuits b11 to b (N-1) 1 for inputting a write command and data from B and the first AND circuit
F / F sections b12 to b (N-1) 2 which hold the outputs of the circuits b11 to b (N-1) 1 and give them to the OR circuit 10;
The F / F section b is read by the read signals from the PU11 to N1.
Gate circuits b14 to b (N-1) 4 for giving the outputs of 12 to b (N-1) 2 to the CPUs 11 to N1;
1 to N1 input a write signal generated when the data is read from the common memory M and a reset signal to each writing section to input the F / F sections b12 to b (N-1) 2. It is composed of second AND circuits b13 to b (N-1) 3 which are reset.

When the data is transmitted from the processor unit 1 to the destination processor unit N in the same manner as the above-described example in which the operation of such an embodiment will be described with reference to FIGS. The processor unit 1 stores the data in the designated area of the common memory M by the write signal (FIG. 1) via the system bus SB (S in FIG. 4).
1).

At the same time, the receiver processor unit N
In response, the transmission source processor unit 1 transmits a unique ID number (; S2).

The receiving register N2 of the receiving destination processor unit N stores the unique ID number () of the sending source processor unit 1 in accordance with the write command signal via the AND circuit b11 of the writing section b1 corresponding to the sending source processor unit 1 and F It is stored in the / F section b12 (S3 and FIG. 2).

The output signal of the F / F section b12 is the OR circuit 10.
Is given as an interrupt notification signal to the receiver CPU N1 via. Recipient CPU that received the interrupt notification signal
N1 outputs a common ID number take-in signal to each of the write sections b1 to b (N-1), opens the gate of the gate circuit b14, and deletes the unique ID number of the source processor unit 1. The data is fetched into the receiving CPU N1 via the internal bus IB (S4).

As a result, the CPU N1 can recognize that the interrupt signal is an interrupt from the processor unit 1,
Data is read from the specified area of the common memory M via the system bus SB (S5).

After the completion of reading the data, the CPU N1 executes the unique I of the source processor unit 1 via the internal bus IB.
The F / F part b12 in which the D number is set is connected to the AND circuit b by both the reset signal and the write signal.
Reset via 13.

In addition, for example, when data is transmitted from a plurality of processor units 1 and 2 to the destination processor unit N at the same time, the source processor units 1 and 2 are designated areas of the common memory M via the system bus SB. The transmission source processor units 1 and 2 transmit the ID number to the reception register N2 of the reception destination processor unit N at the same time when the transmission data is stored in (; S1) (;
S2).

In the reception register N2, the write units b1 and b2 store the ID numbers in the F / F units b12 and b22 via the AND circuits b11 and b21, respectively (FIGS. 3 and S3).

The receiving register N2 receives the two unique ID numbers in this way. The first received ID number and the next received ID number are transferred from the F / F sections b12 and b22 to the O register.
Send to the R circuit 10.

Since the OR circuit 10 uses the input signal as the OR condition, the ID number received previously, for example, the F / F section b
The output of 22 causes the CPU N1 to receive an interrupt notification.

As a result, the CPU N1 takes in the ID number data via the internal bus IB when the read signal is given to the gate circuit b24 (S4), and correspondingly accesses the common memory M. Then, the data is read (; S5).

At the same time, the F / F section b22 of the writing section b2 corresponding to the ID number is reset by the reset signal via the AND circuit b23.

Therefore, after that, the F / F section b12 of the writing section b1 of the reception register N2 remains without being reset, and the CPU / N1 continues to read the data in the same manner as the above, using this as an interrupt signal. Will be done.

[0041]

As described above, in the multiprocessor system according to the present invention, each processor unit is
When one or more ID numbers are written in the writing unit corresponding to the bits of the ID number, the reception unit has one reception register that gives an interrupt notification to the CPU in the processor unit by OR output. Since the common memory corresponding to the ID number in the register is accessed to read the data and then the bit corresponding to the ID number is reset, the receiving register of each processor unit can be reduced and the processor This has the effect of improving the communication speed between the units.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a multiprocessor system according to the present invention.

FIG. 2 is a conceptual diagram (1) of a reception register used in the multiprocessor system according to the present invention.

FIG. 3 is a conceptual diagram (No. 2) of a reception register used in the multiprocessor system according to the present invention.

FIG. 4 is an operation sequence diagram of the multiprocessor system according to the present invention.

FIG. 5 is a block diagram showing an embodiment of one processor unit in the multiprocessor system according to the present invention.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is an operation sequence diagram of a conventional example.

FIG. 8 is a conceptual diagram of a reception register used in a conventional example.

[Explanation of symbols]

 1-N processor unit 11,21-N1 CPU 12,22-N2 receiving register M common memory SB system bus b1, b2-b (N-1) writing part b11, b21-b (N-1) 1 AND circuit b12, b22 to b (N-1) 2 F / F section b13, b23 to b (N-1) 3 AND circuit b14, b24 = b (N-1) 4 gate circuit 10 OR circuit Indicates the same or corresponding part.

Claims (2)

[Claims] 1. A plurality of processor units each having a unique ID number are connected to each other via a system bus, and a common memory is connected to the bus so that one processor unit can be connected to another processor unit.
When transmitting the data, the processor unit of the transmission source transmits the data to the common memory and the ID number of the transmission source to the processor unit of the reception destination, and the processor unit of the reception destination transmits the ID number of the transmission source. In the multiprocessor system for receiving data from the common memory according to the above, each processor unit writes a writing unit corresponding to the ID number and one or more unique ID numbers to the writing unit. The CPU is provided with one reception register including an OR circuit for notifying an interrupt to the CPU in the unit.
A multiprocessor system characterized in that U accesses the common memory corresponding to the ID number in the reception register to read data and at the same time resets the writing unit corresponding to the ID number. 2. A first AND circuit in which each writing section inputs a write command and data from the bus, and the first AN circuit.
An F / F section for holding the output of the D circuit and giving it to the OR circuit, a gate circuit for giving the output of the F / F section to the CPU by a read signal from the CPU, and the CPU It is composed of a second AND circuit for inputting a write signal generated when data is read from the common memory and a reset signal to each writing section to reset the F / F section. The multiprocessor system according to claim 1, characterized in that.