JPH05128048A - Information processor - Google Patents

Abstract

PURPOSE:To improve the occupation rate of a data bus at the time of continuously transferring data by means of direct memory access(DMA) by converting data from a bus with a large size into the bus size of a data bus through a data register, an address register and a bus conversion register. CONSTITUTION:In the case that the memory reading of continuous addresses based upon DMA transfer is executed through a bus 2 whose bus size is larger than that of a data bus 4, a data register 13 stores data read out from the memory through the bus 2 and an address register 14 in a register control circuit 16 stores the address of the data. When the circuit 16 judges that the address corresponds to data in the range of the register 13 in each data transfer, a bus conversion register 15 converts the data into the bus size of the data bus 4 and outputs the converted data to the bus 4. Consequently the occupation rate of the bus 2 can be improved (lowered) and the continuous transfer of data can efficiently be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a data transfer system in an apparatus having two buses having different sizes and different transfer capacities.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, an example of a data transfer system in an information processing apparatus of this type is an I / I connected to a bus 1 having a small bus size and capable of only single transfer of data. For read access from the O boards 5 ₁ , 5 ₂ , ..., 5 _n to the memory 7 connected to the bus 2 having a bus size larger than that of the bus 1 and capable of continuous data transfer, the bus 1 is used every time data is transferred. Access the bus to acquire the bus usage right, output the address, and convert the bus 2
The address received in 6 is converted to the standard of the bus 2, the bus 2 is accessed to acquire the bus use right, the converted address is output to the memory 7, and the data read from the memory 7 is the data in the bus conversion function 26. Once stored in a register (not shown), only the necessary data that fits the size of the bus 1 is taken out and output to the data bus 4 of the bus 1, and this is output to the I / O boards 5 ₁ , 5 ₂ , ..., 5 _n Was being captured.

[0003]

In the above-mentioned conventional data transfer system, the I / O board 5 ₁ connected to the bus ₁ ,
Each time 5 ₂ , ..., 5 _n reads the memory, the bus 1 and the bus 2 are accessed and the data received from the memory 7 is taken out by the bus conversion function 26 and converted into the size of the data bus 4 of the bus 1. Therefore, in the case of data transfer of continuous addresses by direct memory access (hereinafter referred to as DMA), for example, if the bus 2 has a size twice that of the bus 1, the bus conversion function 26 is shown in FIG. As shown, first, the lower byte 27 corresponding to 1/2 of the bus 2 corresponding to the bus size of the data bus 4 of the bus 1 is sent to the bus conversion register 29 and output to the data bus 4 of the bus 1.
When the address bus 3 of the bus 1 outputs the next continuous address, the data of the same address is read again on the bus 2, and this time, as shown in FIG. 6B, a bus corresponding to the bus size of the data bus 4 of the bus 1 is obtained. The upper byte 28 corresponding to 1/2 of 2 is sent to the bus conversion register 29 and output to the data bus 4 of the bus 1. As a result, the bus 2 occupies a large proportion, and further, the data bus 4 of the bus 1 can only perform single transfer even though the bus 2 can continuously transfer data. Therefore, the bus 2 can also perform only single transfer. Therefore, there is a drawback that transfer efficiency is poor.

It is an object of the present invention to continuously transfer data from an I / O board connected to a first bus capable of transferring data only in a single transfer, and a second bus having a larger bus size than the first bus. It is an object of the present invention to provide an information processing device capable of efficiently performing data transfer without increasing the occupation rate of the bus connected to the memory when the DMA is read-accessed to the memory connected to the bus to continuously transfer the data. ..

[0005]

According to the information processing apparatus of the present invention, the bus conversion function has an address register for holding an address when the I / O board attempts a memory read access, and a data stored in the data register. And a bus conversion register for converting the bus size of the I / O board to the bus size of the first bus, and the I / O board when the I / O board attempts to perform a memory read to the memory by direct memory access through the first bus. The address from the board is compared with the address stored in the address register, and if the address is outside the range stored in the data register, the address is read-accessed to the memory according to the standard of the second bus. And perform continuous transfer,
The data read from the memory is stored in the data register, the contents of the address register are updated to the accessed address, and when the memory read access is received from the I / O board, the data is sent through the first bus. The address stored in the data register is compared with the address stored in the address register, and if the address is within the range stored in the data register, the data at the corresponding address is selected from the data register and the bus conversion register is used. Convert the size to the bus size of the first bus and send it to the I / O board side, and monitor the second bus for a command, and perform memory write access at an address within the range stored in the data register. For example, a register control circuit for invalidating the data in the data register.

[0006]

When the memory read of consecutive addresses by the DMA transfer is performed, the data is held in the data register and the address is held in the address register for each channel of the bus conversion unit corresponding to the I / O board through the first bus. When the first bus issues a memory read data transfer word by word or byte by byte, a second bus acquisition request is issued and the target address is reached without accessing the bus. Since the stored data can be retrieved by accessing the memory, the bus occupation rate of the second bus at the time of memory read can be reduced. In addition, since the first bus can only perform single transfer even though the second bus can continuously transfer data, the second bus 2 can also perform only single transfer. Will be resolved.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention, and FIG. 2 is a bus conversion unit 8 ₁ , 8 ₂ , ..., Of FIG.
8 _{n is} a block diagram, FIG. 3 is a detailed diagram of the data register 13 of FIG. 2, and FIG. 4 is a diagram showing bus size conversion in the bus conversion register 15 of FIG.

This information processing apparatus has a bus 1, a bus 2, and an I / O.
O board 5 _1, 5 _2, ..., and a 5 _n and bus converting function 6 and the memory 7.

The bus 1 and the address bus 3 are independent from each other.
Data bus 4 has a width of 16 bits.
Therefore, only single transfer is possible for data transfer. Bus 2
Is a bus that uses command addresses and data in a time division
With 32-bit data width, 4 consecutive transfers are possible.
Memory 7 is connected. I / O board 5₁ 5,₂ ,
... 5_n Is connected to bus 1 and memory 7
When trying to read, the memory read command signal 9
And bus request signal 12₁ , 12₂ , ..., 12 _n From
Go out and get the right to use bus 1 and issue a busy signal 10
And outputs the address to the address bus 3. I / O
Card 5₁ 5,₂ ... 5_n Data transfer by DMA
If it is a transmission, the DMA cycle signal 11 is activated.
The bus conversion function 6 is a bus conversion unit 8₁ , 8₂ , ..., 8_n Equipped
I am. Bus converter 8₁ , 8₂ , ..., 8_n Are each
Corresponding I / O board 5₁5,₂ , ... 5_n And channel
And the data register 13 and the address register.
Star 14, bus conversion register 15, and register control circuit 1
6 equipped with I / O board 5₁ 5,₂ , ... 5_nFrom
Memory read command signal 9 and bus request signal 12
₁ , 12₂ , ..., 12_nWill be selected. Each bus strange
Exchange section 8₁ , 8₂ , ..., 8_n The processing inside is as follows.
It

The data register 13 stores the data read from the memory 7 through the bus 2 when the memory is read. The address register 14 stores the address at which the address bus 3 of the bus 1 accesses the memory 7 through the bus 2 when reading the memory. Bus conversion register 1
Reference numeral 5 converts the bus size of the data read from the memory 7 through the bus 2 and stored in the data register 13 into the bus size of the data bus 4 of the bus 1. When the register control circuit 16 receives an address from the corresponding I / O board 5 ₁ , 5 ₂ , ..., 5 _n through the busy signal 10 and the address bus 3, it receives the received address if the DMA cycle signal 11 is disabled. As it is, it is converted to the standard of the bus 2 and output to the memory 7 to transfer the data of the corresponding address. When the DMA cycle signal 11 is enabled, as a result of comparison, if there is an address error outside the range where the address from the address bus 3 is stored in the data register 13, a read command for the bus 2 is generated and the address bus is generated. The address from No. 3 is converted into the standard of the bus 2, the data of the corresponding address is continuously transferred from the memory 7 through the bus 2, and the data register 13 is sequentially stored from 1 to 4 times. Then, the contents of the address register 14 are updated to the address at this time. The register control circuit 16 selects the designated data for outputting to the bus 1 from the data register 13 in which the data is stored by the data register select signal 17 to select the bus conversion register 15
To the data size of the data bus 4 of the bus 1 and outputs the data to the data bus 4 of the bus 1. Next, the register control circuit 16 compares the address sent from the address bus 3 with the contents of the address register 14, and if the error is within the range stored in the data register 13, the data register select signal 17 is used to output the data register 13 Selects the data specified from to send it to the bus conversion register 15 and converts it to the bus size of the data bus 4 and then the bus 1
To the data bus 4 of.

In the register control circuit 6, the bus 2 is always used.
When the board (not shown) connected to is monitoring the memory access state and detects that the memory write command is issued at an address within the range stored in the data register 13, Address register 1
4 is initialized to invalidate the contents of the data register 13.

Next, the address comparison in the register control circuit 16 will be described. First, the addresses to be compared are addresses other than the lower 4 bits. Bus 2 is 32 bits (4 bytes) and transfers 4 times (16 bytes) at a time, so it is not necessary to look at the lower 4 bits of address bus 3, and if there is a match other than the lower 4 bits, the data register The select signal 17 is generated by the lower 4 bits. Figure 3
As shown in, the upper 2 bits (A
The three 32-bit data registers 13 are selected by comparing the addresses 3 and A2). As shown in FIG. 3A, 1 is selected when A3 = 0 and A2 = 0, and when A3 = 0 and A2 = 1 as shown in FIG.
2 is selected, and A3 = 1 and A2 = 0 as shown in FIG.
In case of, # 3 is selected, and as shown in FIG. 3D, A3 = 1,
When A2 = 1, # 4 is selected. Next, the selected data register 13 is selected by the address of the lower 2 bits (A1, A0) and converted into the bus size of the data bus 4 of the bus 1. As shown in FIG. 4A, the upper 2 bytes when A1 = 1 and A0 = 0, and as shown in FIG. 4B, A1 = 0 and A0 =
When it is 0, the lower 2 bytes of data are transferred to the bus conversion register 15
To the data bus 4 of the bus 1. Figure 4 (c)
As shown in FIG. 4A, when A1 = 1 and A0 = 1, the upper 1 byte of the upper 2 bytes is A1 = 0, A0 as shown in FIG.
When = 1, the upper 1 byte of the lower 2 bytes is sent to the lower byte side of the bus conversion register 15, and the upper byte side outputs the previous data as it is to the data bus 4 of the bus 1.

As for the data sent through the data bus 4 of the bus 1, all 16 bits or lower 8 bits of data are taken into the board on the side of the I / O boards 5 ₁ , 5 ₂ , ... 5 _n as required. ..

By performing the above processing, for example, when the I / O boards 5 ₁ and 5 ₂ connected to the bus 1 are simultaneously trying to transfer the data of the memory read by the DMA, the bus 1 is alternately accessed. Even data register 1
In order to have 3 independently for each I / O board,
Without the I / O board 5 ₂ data register 13 also the I / O board 5 ₁ and memory read is being destroyed contents after the I / O board 5 ₁ has a memory read, I / O board 5 is, again Address register 1 when memory is read
Since the data can be fetched from the data register 13 if the address is within the range stored in 3, it is possible to reduce the bus occupation rate of the bus 2 at the time of memory read. That is, in this embodiment, one memory read transfer of the bus 2 can transfer data from one time of the bus 1 to a maximum of 16 times. Due to the difference in the data transfer capacities of the bus 1 and the bus 2, the bus 2 and the bus 1 are also different. The inefficiency due to the fact that only single transfer equivalent to the above was possible is also eliminated.

[0016]

As described above, according to the present invention, the first bus having a small bus size is the first bus to which the memory is connected.
When a memory read of continuous addresses by DMA transfer is performed to a second bus having a bus size larger than that of the above bus, the data register and the address register hold the data for each channel through the second bus, Whenever the first bus transfers the memory read data by one word or one byte, the second bus acquisition request is issued and the data register is accessed if the target address is reached without accessing the bus. By reading the data stored in
Since the bus occupancy rate of the second bus can be reduced and the first bus can only perform single transfer of data, the second bus can only perform single transfer of data, while the second bus can perform continuous transfer of data. This has the effect of eliminating the inefficiency due to.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention.

FIG. 2 is a block diagram of bus conversion units 8 ₁ , 8 _2, ..., 8 _n shown in FIG.

FIG. 3 is a detailed diagram of a data register 13 in FIG.

4 is a diagram showing bus size conversion in the bus conversion register 15 of FIG.

FIG. 5 is a block diagram of a conventional example of an information processing apparatus.

6 is a diagram showing bus size conversion in the information processing apparatus of FIG.

[Explanation of symbols]

1, 2 bus 3 address bus 4 data bus 5 ₁ , 5 ₂ , ..., 5 _n I / O board 6 bus conversion function 7 memory 8 ₁ , 8 ₂ , ..., 8 _n bus conversion unit 9 memory read command signal 10 busy Signal 11 DMA cycle signal 12 ₁ , 12 ₂ , ..., 12 _n Bus request signal 13 Data register 14 Address register 15 Bus conversion register 16 Register control circuit 17 Data register select signal

Claims (1)

[Claims] 1. A first device capable of performing only a single transfer of data.
The address for read access received from the I / O board connected to the first bus is connected to the second bus which has a bus size larger than the first bus and capable of continuous data transfer. A bus for converting the specified data out of the data read from the memory into the bus size of the first bus and outputting the converted data to the O / I board. In the information processing device having a conversion function, the bus conversion function stores an address register that holds an address when the I / O board attempts read access to the memory, and data read from the memory. An address register for converting the bus size of the data stored in the data register to the bus size of the first bus; When the I / O board attempts to read a memory into the memory by direct memory access through the first bus, the address from the I / O board is compared with the address stored in the address register to obtain the data. If the address is out of the range stored in the register, the address is read-accessed to the memory according to the standard of the second bus for continuous transfer, and the data read from the memory is stored in the data register. When the contents of the address register are updated to the accessed address and the memory read access is received from the I / O board next, the address sent through the first bus and the address stored in the address register are updated. Compare and compare with an address within the range stored in the data register. For example, the data at the corresponding address is selected from the data register, the size is converted to the bus size of the first bus by the bus conversion register, the size is sent to the I / O board side, and the second bus is command monitored. And a register control circuit that invalidates the data in the data register if there is a memory write access at an address within the range stored in the data register, and is provided corresponding to the I / O board. An information processing device having a bus converter.