JPH1196103A - I/o controller with memory monitoring function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an I/O controller with a memory monitoring function which can reduce the number of memory accesses, shorten the memory access waiting time of a processor and prevent the reduction of system performance. SOLUTION: The I/O controller 3 built in a computer system is provided with a memory access monitor circuit 14 and a data entry circuit 16. When the circuit 14 detects writing operation in a memory 4 by a processor 1, a request for entering data to be written is outputted from the circuit 14 to the circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an I / O controller with a memory monitoring function incorporated in a computer system such as a personal computer, an office computer, and a server.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing the configuration of a conventional I / O controller with a memory monitoring function incorporated in a computer system and its peripheral circuits.

A processor 1 sends an I / O signal to a contention control circuit 2 through a local bus access right request signal 5.
A request for an access right to the controller 3 or the memory 4 is made. The contention control circuit 2 performs contention control according to an arbitrary priority, and notifies the I / O controller 3 or the memory 4 of access permission / non-permission through the local bus access permission signal 6.

When the processor 1 receives a notice of access permission to the I / O controller 3 or the memory 4 through the local bus access permission signal 6, in the case of I / O access, the data bus 9 and the address bus 10 and I
Data is written to the I / O controller 3 via the / O write signal 11. In the case of memory access, the data bus 9, address bus 10 and memory write signal 12
, The data is written to the memory 4.

The I / O controller 3 requests the contention control circuit 2 for an access right to the memory 4 through a memory access right request signal 7. The contention control circuit 2 performs contention control according to an arbitrary priority, and notifies the memory access permission signal 8 of permission / non-permission of access to the memory 4.

When the I / O controller 3 receives a notice of access permission to the memory 4 through the memory access permission signal 8, the data in the memory 4 is transmitted through the data bus 9, the address bus 10, and the memory read signal 13. Read. I / O controller 3 according to the read data
Works.

Next, the operation of the conventional apparatus shown in FIG. 3 will be described with reference to the timing chart shown in FIG. During the “timing 1” period, a request is made via the local bus access right request signal 5 from the processor 1 ('L' active)
Is transmitted to the contention control circuit 2, and the contention control circuit 2 gives permission (“L” active: indicates permission when it becomes “L”) and non-permission (“H” state) according to an arbitrary priority. Notify the processor 1 through the access permission signal 6. When the processor 1 receives the permission from the local bus access permission signal 6, the processor 1 uses the address bus 10, the data bus 9, and the memory write signal 12 to store the data on the memory 4.
Write the command of the I / O controller 3.

In the period of “timing 2”, a request (“L” active) is transmitted to the contention control circuit 2 through the local bus access right request signal 5 from the processor 1. The contention control circuit 2 gives permission ('L' active: indicates permission when it becomes 'L') and non-permission ('H' state) to the processor 1 through the local bus access permission signal 6 according to an arbitrary priority. Notice. The processor 1 receives the permission from the local bus access permission signal 6, and writes a start command to the I / O controller 3 using the address bus 10, the data bus 9, the I / O write signal 11, and the like.

During a “timing 3”, a request (“L” active) is transmitted to the contention control circuit 2 through the memory access right request signal 7 from the I / O controller 3. The contention control circuit 2 gives permission (“L” active: indicating permission when it becomes “L”) and non-permission (“H” state) through the memory access permission signal 8 according to an arbitrary priority. Notify the O controller 3.

The I / O controller 3 having been permitted by the memory access permission signal 8 reads the command written in the memory 4 using the address bus 10, the data bus 9, and the memory read signal 13. During the memory read of the I / O controller 3, the processor 1 outputs a bus access request and is in a waiting state.

[0011]

The above prior art has the following problems. Write a command to the I / O controller 3 on the memory, and write the command to the I / O controller 3.
In a computer system in which reading operation is performed by the O controller 3, since the I / O controller 3 performs memory access, there is a problem that a memory access waiting time of the processor 1 is required and the performance of the computer system is reduced.

While the I / O controller 3 is reading commands from the memory 4, the processor 1 cannot use the bus.

An object of the present invention is to provide an I / O controller with a memory monitoring function that can reduce the number of times of reading information from a memory, reduce the memory access waiting time of a processor, and prevent a decrease in system performance. It is in.

[0014]

In order to solve the above-mentioned problems, an I / O controller with a memory monitoring function according to the present invention has the following characteristic configuration. (1) In an I / O controller built in a computer system, a memory access monitoring circuit and a data fetch circuit are provided in an I / O controller main body, and the memory access monitoring circuit performs a write operation to a memory by a processor. Upon detection, the memory access monitoring circuit issues a request to fetch the data to be written, to the data fetch circuit.

(2) In the controller according to the above (1), the data fetch circuit, which has received the data fetch request, fetches the data during the memory write operation of the processor.

(3) In the I / O controller built in the computer system, the memory write signal output from the processor is monitored during the memory write of the processor. A memory access monitoring circuit for outputting a request signal, and a data capturing circuit for receiving data output from the processor during a memory write operation of the processor in response to a data capture request from the memory access monitoring circuit during the memory write operation And the data captured in the data capturing circuit is used as control information.

(4) In the I / O controller built in the computer system, a memory access monitoring circuit and a data fetch circuit are provided in the I / O controller main body, and the memory access monitoring circuit is provided in the I / O controller main body. When a command is received from the memory access monitoring circuit, a command fetch request is sent from the memory access monitoring circuit to the data fetch circuit.

(5) In the controller according to the above (1), the data fetch circuit, which has received the command fetch request, fetches the command during the memory write operation of the processor.

[0019]

FIG. 1 is a block diagram showing a configuration of an I / O controller with a memory monitoring function according to a first embodiment of the present invention together with its peripheral circuits. As shown in FIG.
The I / O controller 3 according to the present embodiment includes a data fetch circuit 16 and a memory access monitoring circuit 14 in the main body of the I / O controller.

The processor 1 requests the contention control circuit 2 for an access right to the I / O controller 3 or the memory 4 through a local bus access right request signal 5. The contention control circuit 2 performs contention control according to an arbitrary priority, and notifies the I / O controller 3 or the memory 4 of access permission / non-permission through the local bus access permission signal 6.

When the processor 1 receives a notification of access permission to the I / O controller 3 or the memory 4 through the local bus access permission signal 6, the data bus 9 and the address bus 10 for I / O access. , I /
Data is written to the I / O controller 3 through the O write signal 11. In the case of memory access, data bus 9, address bus 10, memory write signal 12
, The data is written to the memory 4.

When the memory of the processor 1 is written,
The memory access monitoring circuit 14 inside the I / O controller 3 monitors the address bus 10 and the memory write signal 12. When it is determined that a memory write operation to the memory space in the area where the command of the I / O controller 3 is written is performed, the fetch request signal 15
A data fetch request is issued to the data fetch circuit 16 through. The data capture circuit 16 that has received the data capture request captures the data during the memory write operation of the processor 1.

The I / O controller 3 requests the contention control circuit 2 for an access right to the memory 4 through a memory access right request signal 7. The contention control circuit 2 performs contention control according to an arbitrary priority, and notifies the memory access permission signal 8 of permission / non-permission of access to the memory 4.

When the I / O controller 3 receives a notice of access permission to the memory 4 through the memory access permission signal 8, the data bus 9, the address bus 10,
The data in the memory 4 is read through the memory read signal 13.

When the I / O controller 3 receives a start command from the processor 1, the I / O controller 3 operates according to the data read earlier (data stored in the data acquisition circuit 16).

Next, the operation of the apparatus shown in FIG. 1 will be described with reference to the timing chart of FIG. In the “timing 1” period, a request (“L” active) is transmitted to the contention control circuit 2 through the local bus access right request signal 5 from the processor 1, and the contention control circuit 2 permits the contention according to an arbitrary priority ( 'L' active: 'L'
, The permission is indicated), and the non-permission (“H” state) is notified to the processor 1 through the local bus access permission signal 6. Upon receiving permission from the local bus access permission signal 6, the processor 1 writes a command for the I / O controller 3 on the memory 4 using the address bus 10, the data bus 9, and the memory write signal 12.

When the memory access monitoring circuit 14 determines that the command is a command to the I / O controller 3, a fetch request (“L” active signal) is made to the data fetch circuit 16 through a fetch request signal 15.
The data fetch circuit 16 fetches data at the same timing as writing to the memory 4 of the processor 1.

During the "timing 2" period, a request ("L" active) is transmitted to the contention control circuit 2 through the local bus access right request signal 5 from the processor 1. The contention control circuit 2 gives permission (“L” active: indicates permission when it becomes “L”) and non-permission (“H” state) through the local bus access permission signal 6 according to an arbitrary priority. Notify. The processor 1 receives the permission from the local bus access permission signal 6, and the address bus 10, the data bus 9, the I / O
A start command is written to the I / O controller 3 using the write signal 11.

In the "timing 3" period, the I / O controller 3 does not perform memory access, reads out the command read in the "timing 1" period from the data acquisition circuit 16, and operates according to the command.

The I / O controller 3 does not need to access the memory as in the case of "timing 3" in FIG.
The processor 1 receives a bus access permission and performs a memory access.

[0031]

As described above, according to the present invention,
The memory access count of the I / O controller can be reduced, the memory access waiting time of the processor is reduced,
An I / O controller with a memory monitoring function that can improve the processing performance of a computer system can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an I / O controller with a memory monitoring function according to a first embodiment of the present invention and a circuit configuration around the I / O controller;

FIG. 2 is a diagram showing operation timings of the I / O controller with a memory monitoring function according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an I / O controller according to a conventional example and a circuit configuration around the I / O controller.

FIG. 4 is a diagram showing operation timing of an I / O controller according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processor 2 Contention control circuit 3 I / O controller 4 Memory 5 Local bus access (LBA) right request signal 6 Local bus access (LBA) permission signal 7 Memory access (MA) right request signal 8 Memory access (MA) ) Permit signal 9 Data bus 10 Address bus 11 I / O write signal 12 Memory write signal 13 Memory read signal 14 Memory access monitoring circuit 15 Capture request signal 16 Data capture circuit

Claims (5)

[Claims] 1. I / O built in a computer system
In the controller, a memory access monitoring circuit and a data fetching circuit are provided in the I / O controller main body, and when the memory access monitoring circuit detects a write operation to a memory by a processor, the memory access monitoring circuit outputs the data from the memory access monitoring circuit. An I / O controller with a memory monitoring function, wherein a request for taking in the data to be written is made to a taking-in circuit. 2. The I / O with a memory monitoring function according to claim 1, wherein said data fetch circuit, which has received a data fetch request, fetches said data during a memory write operation of said processor. controller. 3. I / O built in a computer system
A memory access monitoring circuit for monitoring a memory write signal output from the processor during a memory write of the processor and outputting a capture request signal when the transmission of the memory write signal is detected; A data capture circuit that captures data output from the processor during a memory write operation of the processor during a memory write operation in response to a data capture request from the processor.
An I / O controller with a memory monitoring function, wherein data captured in the data capturing circuit is used as control information. 4. I / O built in a computer system
In the controller, a memory access monitoring circuit and a data fetch circuit are provided in the I / O controller main body, and when the memory access monitoring circuit detects a command to the I / O controller main body, the memory access monitoring circuit transmits the command to the I / O controller main body. An I / O with a memory monitoring function, wherein a request to fetch the command is sent to a data fetch circuit.
controller. 5. The I / O controller with a memory monitoring function according to claim 4, wherein said data fetch circuit, which has received the command fetch request, fetches the command during a memory write operation of the processor. .