JPH07210498A - Bus arbiter - Google Patents

Abstract

PURPOSE:To increase the speed of consecutive transfer of data by omitting wastefull arbitration during the consecutive access of a shared memory by CPU or a DMA device with a successive transferring function. CONSTITUTION:This bus arbiter arbitrates a shared memory access right when access to the shared memory by CPU and the DMA device with a successive transferring function compete each other. The circuit is provided with an AND circuit 39 which starts arbitration based on a shared memory access requiring signal 2b from communication LS 12 as the DMA device and outputs a shared memory access valid signal 3i by admitting the validity of shared memory access by communication LSI 12 when the shared memory access right by CPU 1 is not acquired. Besides, the circuit is provided with an AND circuit 41 holding the shared memory access right by communication LSI 12 based on a bus acquiring signal 2d showing the acquiring state of a shared bus by communication LSI 12 and the shared memory access valid signal 3i, and OR circuits 40 and 42.

Description

Detailed Description of the Invention

[0001]

This invention relates to a CPU and a DMA (Dire
ct Memory Access) A shared memory is provided between the device and the CPU, and the data interface between the DMA device is performed by the shared memory, and access to each dedicated memory is prevented by mutual interference of bus cycles. The present invention relates to a bus arbitration circuit in an information processing device designed to achieve high speed.

[0002]

2. Description of the Related Art A communication LSI is hereinafter referred to as a DMA device.
The prior art when using is described. Conventionally, in order to access a shared memory existing on a physically separated bus, an address output by a communication LSI is decoded and an arbitration is started by a communication LSI shared memory access request signal obtained by conversion, and this arbitration is performed. A ready signal indicating that the shared memory is ready for access to the communication LSI.
It is known how to return to. In this method, the communication LSI shared memory access request signal becomes invalid due to address switching, and arbitration is abandoned. This method
This is a method in which an arbitration operation is performed every bus cycle when the communication LSI accesses the shared memory.

FIG. 7 is a general overall configuration diagram of an information processing apparatus of this type. Since the CPU-dedicated memory 11 connected to the CPU-dedicated bus 12 is not accessed from the communication LSI 2, it indicates that the CPU-dedicated memory 11 is ready based on the CPU-dedicated memory chip select signal 1a output from the CPU address decoding circuit 13. The CPU ready signal 1f can be returned to the CPU 1 by the OR circuit 15. In this case, the CPU dedicated memory 11 is the CPU
Since it has a sufficiently fast access speed for one bus cycle, it is a non-wait CPU ready signal 1f.
return it.

Similarly, when the communication LSI 2 accesses the communication LSI dedicated memory 21 connected to the communication LSI dedicated bus 22, the communication LSI dedicated memory chip select signal 2a output from the communication LSI address decoding circuit 23 is used for communication. The communication LSI ready signal 2f can be returned to the LSI 2 via the OR circuit 24.

However, since the shared memory 61 connected to the shared bus 62 is accessed by both the CPU 1 and the communication LSI 2, if the access conflicts, the right to access the shared memory 61 via the shared bus 62 is granted. It is necessary for the bus arbitration circuit 3 to arbitrate which of the CPU 1 and the communication LSI 2 obtains.

In FIG. 7, reference numeral 16 denotes a buffer provided between the CPU-dedicated bus 12 and the shared bus 62.
Reference numeral 5 denotes a buffer provided between the communication LSI dedicated bus 22 and the shared bus 62. 1b is a CPU shared memory access request signal, 2b is a communication LSI shared memory access request signal, 1c is a CPU system clock, 2c is a communication LSI system clock, 2g is a communication LSI bus access request signal, and 2h is a communication LSI bus use permission. signal,
3a is a CPU side buffer enable signal, 3b is a shared memory chip select signal, 3c is a communication LSI side buffer enable signal, 3d is a CPU side shared memory ready signal, and 3e is a communication LSI side shared memory ready signal.

FIG. 8 is a block diagram showing a schematic configuration of the conventional bus arbitration circuit 3. When the CPU 1 accesses the shared memory 61, the CPU shared memory access request signal 1
b is valid and CPU shared memory access prohibition signal 3
The shared memory 61 can be accessed when k is invalid. Then, when the AND circuit 36 outputs the CPU shared memory access right acquisition signal 3f, this signal 3f passes through the OR circuit 35 and the shared memory chip select signal 3b.
At the same time, the CPU side buffer enable signal 3a and the buffer valid signal 3h are validated after being input to the buffer timing control circuit 32 and the ready control circuit 31 for timing control, and the shared memory ready signal 3d is returned to the CPU 1.

On the other hand, when the communication LSI 2 accesses the shared memory 61, the shared memory 61 is accessed when the communication LSI shared memory access request signal 2b is valid and the communication LSI shared memory access prohibition signal 3g is invalid. You can Then, the AND circuit 39 causes the communication LS
When the I shared memory access right acquisition signal 3j is output, this signal 3j is output as the shared memory chip select signal 3b via the OR circuit 35, and at the same time, is input to the buffer timing control circuit 34 and the ready control circuit 33 for timing control. After that, the communication LSI side buffer enable signal 3c and the buffer valid signal 3m are validated, and the shared memory ready signal 3e is returned to the communication LSI 2. In addition, in FIG. 8, 37 and 38 are NOT circuits.

FIG. 9 is a timing chart until the CPU 1 or the communication LSI 2 acquires the shared memory access right and ends the bus cycle. CPU1 is shared memory 6
When accessing 1, the CPU 1 outputs an address.
As a result of decoding the address, the CPU shared memory access request signal 1b is output to participate in the arbitration of the shared memory access right. In the case of the portion in FIG. 9, since the CPU shared memory access prohibition signal 3k is invalid (“H” level), the CPU 1 immediately obtains the shared memory access right and outputs the CPU shared memory access right acquisition signal 3f.

However, in the case of the portion, when the CPU 1 outputs the shared memory access request signal 1b, the communication L has already been transmitted.
SI2 has acquired the shared memory access right, and the CPU
Since the shared memory access prohibition signal 3k is valid (“L” level), the CPU 1 waits until the shared memory access of the communication LSI 2 is completed.

On the other hand, when the communication LSI 2 accesses the shared memory 61, the communication LSI 2 outputs an address. As a result of decoding the address, the communication LSI shared memory access request signal 2b is output to participate in the arbitration of the shared memory access right. In the case of the part in FIG. 9, a communication LSI
Since the shared memory access prohibition signal 3g is invalid, the communication LSI 2 can immediately obtain the shared memory access right. However, in the case of the portion, when the communication LSI 2 outputs the shared memory access request signal 2b, the CPU 1 has already acquired the shared memory access right in the portion, and the communication LSI shared memory access prohibition signal 3g is valid. The communication LSI 2 waits until the shared memory access of the CPU 1 is completed.

[0012]

In the above prior art, when the CPU 1 or the communication LSI 2 accesses the shared memory 61, it is efficient for single transfer access. However, like sequential transfer (burst transfer), CP
Shared memory 6 stores data in the area where U1 and communication LSI 2 are located.
In the case of continuous transfer to and from 1, the arbitration for the shared memory access right will occur each time the address is switched during continuous access to the shared memory 61. Therefore, there is a problem that it takes a long time to transfer the data even though the data is continuously transferred, and the advantage of the continuous transfer cannot be maximized.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a shared system in which a CPU or a DMA device having a sequential transfer function is connected to a physically separated bus. An object of the present invention is to provide a bus arbitration circuit that can reduce the data transfer time by omitting arbitration when continuously accessing a memory.

[0014]

In order to achieve the above object, a first aspect of the present invention is to start arbitration based on a shared memory access request signal from a DMA device, and when the shared memory access right by the CPU is not acquired. A means for recognizing that the shared memory access by the DMA device is valid and outputting a shared memory access valid signal; and a bus acquisition state signal indicating a shared bus acquisition state by the DMA device and the shared memory access valid signal, DM
And a means for holding the shared memory access right by the A device.

According to the second aspect of the invention, the arbitration is started based on the shared memory access request signal from the CPU, and the shared memory access by the CPU is recognized as valid when the shared memory access right by the DMA device is not acquired. Means for outputting a shared memory access enable signal by means of a CP
A unit for holding the shared memory access right by the CPU based on the continuous access request signal for requesting the continuous access of the shared memory by U and the shared memory access valid signal is provided.

[0016]

According to the first aspect of the invention, the DMA device participates in the arbitration for the shared memory access right based on the shared memory access request signal. At this time, if the CPU has not acquired the shared memory access right, as a result of the arbitration, D
Access to the shared memory by the MA device is enabled. Then, as long as the shared bus is continuously acquired by the DMA device, the DM is switched by switching the address.
Even if the shared memory access request signal and the shared memory access valid signal by the A device become invalid, the shared memory access right acquisition signal continues to be valid.

In the second invention, the CPU participates in the arbitration for the shared memory access right based on the shared memory access request signal. At this time, if the DMA device has not acquired the shared memory access right, the access to the shared memory by the CPU is enabled as a result of the arbitration. As long as the continuous access request signal for the shared memory by the CPU is valid, the shared memory access right acquisition signal is valid even if the shared memory access request signal and the shared memory access valid signal by the CPU are invalidated by the address switching. And keep going.

Due to the above operation, the DMA device or C
After the PU once acquires the shared memory access right, it is possible to perform continuous access to the shared memory by omitting useless arbitration at the time of address switching.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Each of the embodiments is a case where a communication LSI is used as a DMA device as in the prior art. In addition,
The DMA device may be a dedicated DMA controller or an input / output processor. First, FIG. 2 is an overall configuration diagram of an information processing apparatus to which the embodiment of the first invention is applied. The main constituent elements are the same as those in FIG. 7, and the difference is that the communication LSI bus acquisition status signal 2d is sent from the communication LSI 2 as a DMA device to the bus arbitration circuit 3A.

When the structure of this information processing apparatus is briefly described together with its operation, the CPU 1 is provided with a CP via a CPU dedicated bus 12.
U dedicated memory 11, CPU address decoding circuit 13,
The buffer 16 is connected. The address from the CPU 1 is converted into a CPU dedicated memory chip select signal 1a by the CPU address decoding circuit 13 and input to the CPU dedicated memory 11 and the OR circuit 15, and the address is converted into the CPU shared memory access request signal 1b. Is input to the bus arbitration circuit 3A.

The OR circuit 15 generates a CPU ready signal 1f based on the CPU dedicated memory chip select signal 1a and the CPU side shared memory ready signal 3d from the bus arbitration circuit 3A. This signal 1f is input to the ready terminal of the CPU 1. To be done.

The communication LSI 2 includes the communication LSI dedicated bus 2
A communication LSI dedicated memory 21, a communication LSI address decoding circuit 23, and a buffer 25 are connected via 2. Further, a shared bus 62 is connected between the buffers 16 and 25, and a shared memory 61 is connected to the shared bus 62. Here, the shared memory 61 may be a register or the like in addition to the RAM or the like.

The address from the communication LSI 2 is the communication LS
The I-address decoding circuit 23 converts the memory LSI dedicated memory chip select signal 2a into the communication LSI dedicated memory 21 and the OR circuit 24, and the address is the communication LSI shared memory access request signal 2b.
And is input to the bus arbitration circuit 3A. In the OR circuit 24, the communication LSI dedicated memory chip select signal 2
a and shared memory ready signal 3e from the bus arbitration circuit 3A
A communication LSI ready signal 2f is generated on the basis of the above, and this signal 2f is input to the ready terminal of the communication LSI 2.

Next, FIG. 1 shows the configuration of the bus arbitration circuit 3A, and the same components as those in FIG. 8 are designated by the same reference numerals. In other words, the bus arbitration circuit 3A includes buffer timing control circuits 32 and 34 and a ready control circuit 3
1, 33, OR circuits 35, 40, 42, AND circuit 3
6, 39, 41 and NOT circuits 37, 38.

Here, the AND circuit 36 receives the CPU shared memory access request signal 1b and the CPU shared memory access prohibition signal 3k as input, and generates the CPU shared memory access right acquisition signal 3f, which is the NOT circuit 3.
7, the ready control circuit 31, the buffer timing control circuit 32, and the OR circuit 35.

The CPU system clock 1c, the buffer valid signal 3h and the CPU shared memory access right acquisition signal 3f are input to the ready control circuit 31, and the CPU side shared memory ready signal 3d is generated and output. The CPU system clock 1c and the CPU shared memory access right acquisition signal 3f are input to the buffer timing control circuit 32, and the buffer timing control circuit 32 outputs the CPU side buffer enable signal 3a and the buffer valid signal 3h.

The communication LSI shared memory access request signal 2b and the communication LSI shared memory access prohibition signal 3g are input to the AND circuit 39, and the output thereof is the communication LSI.
The shared memory access valid signal 3i is the OR circuit 40, 42.
Entered in. A communication LSI shared memory access valid signal 3i and a communication LSI shared memory continuous access signal 3n are input to the OR circuit 40, and the output is a communication LSI.
The continuous access enable signal 3p is input to the AND circuit 41.

The AND circuit 41 has a communication LSI bus acquisition status signal 2d and a communication LSI continuous access enable signal 3
p and p are input, and the output becomes the communication LSI shared memory continuous access signal 3n. In the OR circuit 42, the OR
Similarly to the circuit 40, the communication LSI shared memory access valid signal 3i and the communication LSI shared memory continuous access signal 3n are input, and the output of the communication LSI shared memory access right acquisition signal 3j, which is the output thereof, is the NOT circuit 38, the ready control circuit 33, Buffer timing control circuit 34 and OR circuit 3
Input to 5.

Further, the ready control circuit 33 includes a communication LSI.
The system clock 2c, the buffer valid signal 3m, and the communication LSI shared memory access right acquisition signal 3j are input,
The ready control circuit 33 outputs the communication LSI side shared memory ready signal 3e. The buffer timing control circuit 34 includes a communication LSI system clock 2c and a communication LSI.
The shared memory access right acquisition signal 3j is input, and the buffer timing control circuit 34 outputs the communication LSI side buffer enable signal 3c and the buffer valid signal 3m.

The CPU shared memory access right acquisition signal 3f and the communication LSI shared memory access right acquisition signal 3j are input to the OR circuit 35, and the output of the shared memory chip select signal 3b is sent to the shared memory 61.

Next, the operation of this embodiment will be described. First, if the CPU shared memory access request signal 1b is at "H" level, the CPU 1 participates in arbitration over the shared memory access right.

At this time, if the CPU shared memory access prohibition signal 3k is invalid ("H" level), the AND circuit 36 outputs the "H" level CPU shared memory access right acquisition signal 3f. When this signal 3f is at "H" level, the communication LSI shared memory access prohibition signal 3g becomes "L" level via the NOT circuit 37, and the communication LS
I2 is not allowed to acquire the shared memory access right, and
Shared memory chip select signal 3b via R circuit 35
Is output, and after the timing is controlled by the ready control circuit 31 and the buffer timing control circuit 32, the buffer valid signal 3h, the CPU side buffer enable signal 3a, and the CPU side shared memory ready signal 3d are output.

On the other hand, if the communication LSI shared memory access request signal 2b is at "H" level, the communication LSI 2 participates in arbitration over the shared memory access right. At this time,
If the communication LSI shared memory access prohibition signal 3g is invalid (“H” level), the AND circuit 39 outputs the “H” level communication LSI shared memory access valid signal 3i. When the signal 3i is at "H" level, the "H" level communication LSI shared memory access right acquisition signal 3j is output through the OR circuit 42.

The communication LSI shared memory access right acquisition signal 3j sets the CPU shared memory access prohibition signal 3k to the "L" level via the NOT circuit 38 to prevent the CPU 1 from acquiring the shared memory access right, and also through the OR circuit 35. The shared memory chip select signal 3b is output,
Ready control circuit 33, buffer timing control circuit 34
After timing control by, the buffer valid signal 3m, the communication LSI side buffer enable signal 3c, and the communication LSI side shared memory ready signal 3e are output. Note that these signals are timing-controlled only at the beginning of the access cycle, and thereafter, as long as the shared memory access right by the communication LSI 2 is valid, as will be described later, they remain valid without timing control.

Communication LSI shared memory access valid signal 3
When i is at “H” level, communication L is performed via the OR circuit 40.
The SI continuous access enable signal 3p becomes "H" level. At this time, if the communication LSI bus acquisition status signal 2d is at "H" level, the AND circuit 41 causes the communication LS
The I shared memory continuous access signal 3n becomes "H" level. This signal 3n is fed back to the OR circuit 40, and even if the communication LSI shared memory access request signal 2b and the communication LSI shared memory access valid signal 3i become "L" level by switching the address, the communication LSI continuous access enable signal 3p is set. Then, hold it at "H" level.

Therefore, the communication LSI shared memory continuous access signal 3n continues to be at "H" level unless the communication LSI bus acquisition state signal 2d becomes "L" level. Therefore, the communication LSI shared memory access right acquisition signal 3j can be continuously output via the OR circuit 42, and the communication LSI 2 can continuously access the shared memory 61.

FIG. 3 is a timing chart showing these operations. When the communication LSI 2 accesses the shared memory 61, the communication LSI 2 outputs an address. As a result of decoding the address, the communication LSI shared memory access request signal 2b is output to participate in the arbitration of the shared memory access right. When the communication LSI shared memory access prohibition signal 3g is invalid, the communication LSI 2 can immediately obtain the shared memory access right. Further, when the communication LSI 2 acquires the shared memory access right and the communication LSI bus acquisition status signal 2d is at the “H” level, the communication LS is in the meantime.
The I shared memory access right acquisition signal 3j is kept at "H" level. Therefore, when the communication LSI 2 continuously accesses the shared memory 61, useless bus arbitration at the time of address switching can be omitted.

Next, an embodiment of the second invention will be described. Contrary to the first aspect of the invention, the present invention eliminates unnecessary arbitration when the CPU continuously accesses the shared memory. First, FIG. 5 shows the overall configuration of an information processing apparatus to which this embodiment is applied. The same components and signals as those in FIG. The part will be mainly described.

5 is different from FIG. 2 in that a register 14 for storing the CPU shared memory continuous access request signal 1d from the CPU dedicated bus 12 is added and the signal 1d is input to the bus arbitration circuit 3B. Besides,
Accordingly, the communication LS from the communication LSI 2 in FIG.
This is the point where the input of the I-bus acquisition status signal 2d to the bus arbitration circuit has disappeared.

FIG. 4 shows the bus arbitration circuit 3 according to this embodiment.
2 is a block diagram showing the configuration of B, in which the same components and signals as in FIG. 1 are assigned the same reference numerals. The difference from FIG. 1 will be mainly described. An OR is applied to the output side of the AND circuit 36.
A circuit 40 and an AND circuit 41 are sequentially provided, and
The CPU shared memory access valid signal 3i ′ output from the ND circuit 36 and the CPU shared memory continuous access signal 3n ′ output from the AND circuit 41 are input to the OR circuit 40. Further, the CPU shared memory access right acquisition signal 3f, which is the output of the OR circuit 40, outputs the AND circuit 41, N
It is input to the OT circuit 37, the ready circuit 31, the buffer timing control circuit 32, and the OR circuit 35. In addition,
The CPU shared memory continuous access request signal 1d is also input to the AND circuit 41.

Further, the communication LSI shared memory access request signal 2b and the communication LSI shared memory access prohibition signal 3g.
The output of the AND circuit 39 to which is input is directly used as the communication LSI shared memory access right acquisition signal 3j
It is input to the circuit 38, the ready circuit 33, the buffer timing control circuit 34, and the OR circuit 35.

Next, the operation of this embodiment will be described. C
When the PU 1 continuously accesses the shared memory 61, the CPU shared memory continuous access request signal 1d is written to the register 14, and then the CPU shared memory access request signal 1b is sent to the bus arbitration circuit 3B via the decoding circuit 13. . If the signal 1b is at "H" level, the CPU 1 participates in arbitration over the shared memory access right.

At this time, if the CPU shared memory access prohibition signal 3k is invalid ("H" level), the AND circuit 36 changes the CPU shared memory access request signal 1b to "H" level to "H". The CPU shared memory access valid signal 3i 'of the level is output. This signal 3
When i'is at the "H" level, the CPU is connected via the OR circuit 40.
The shared memory access right acquisition signal 3f becomes the “H” level, the communication LSI 2 is not made to acquire the shared memory access right via the NOT circuit 37, and the shared memory chip select signal 3b is output via the OR circuit 35 to perform ready control. After the timing is controlled by the circuit 31 and the buffer timing control circuit 32, the buffer valid signal 3
h, the CPU side buffer enable signal 3a, and the CPU side shared memory ready signal 3d are output.

When the CPU shared memory access right acquisition signal 3f is at "H" level and the CPU shared memory continuous access request signal 1d is at "H" level, the CPU shared memory continuous access signal is sent via the AND circuit 41. Three
n'becomes "H" level. This signal 3n 'is fed back to the OR circuit 40 and holds the CPU shared memory access right acquisition signal 3f at "H" level.

Therefore, by switching the address, the CPU
Even if the shared memory access request signal 1b and the CPU shared memory access valid signal 3i 'become "L" level, C
Unless the PU shared memory continuous access request signal 1d becomes "L" level, the CPU shared memory continuous access signal 3n 'and the CPU shared memory access right acquisition signal 3f continue to be "H" level. Therefore, the CPU 1 can continuously access the shared memory 61.

On the other hand, if the communication LSI shared memory access request signal 2b is at "H" level, the communication LSI 2 participates in arbitration over the shared memory access right. At this time,
If the communication LSI shared memory access prohibition signal 3g is invalid (“H” level), the AND circuit 39 outputs the “H” level communication LSI shared memory access right acquisition signal 3j. This signal 3j sends the CPU shared memory access prohibition signal 3k to "L" via the NOT circuit 38.
The level is set so that the CPU 1 does not acquire the shared memory access right, the shared memory chip select signal 3b is output through the OR circuit 35, and the buffer control signal 3m is output after the ready control circuit 33 and the buffer timing control circuit 34 perform timing control. , A communication LSI side buffer enable signal 3c and a communication LSI side shared memory ready signal 3e are output.

FIG. 6 is a timing chart showing these operations. In FIG. 6, (A) is the timing when the CPU 1 makes a single transfer access to the shared memory 61. As a result of decoding the address output by the CPU 1, the CPU shared memory access request signal 1b is output to participate in the arbitration of the shared memory access right. When the CPU shared memory access prohibition signal 3k is invalid, CP
U1 can immediately obtain the shared memory access right.

The portion (B) of FIG. 6 shows the timing when the CPU 1 continuously accesses the shared memory 61. In this case, the CPU 1 writes in advance in the register 14 so that the CPU shared memory continuous access request signal 1d becomes the “H” level. After that, when the CPU shared memory access request signal 1b becomes the “H” level, it participates in arbitration, and C
When the PU shared memory access prohibition signal 3k is invalid, the CPU shared memory access right acquisition signal 3f becomes "H" level.

Then, this signal 3f is held at the "H" level unless the CPU shared memory continuous access request signal 1d goes to the "L" level, and the CPU shared memory access request signal 1b is changed to the "L" level by switching the address from the CPU1. The access right to the shared memory 61 is not abandoned even when the level becomes "level". Therefore, when the CPU 1 continuously accesses the shared memory 61, useless bus arbitration can be omitted.

When the communication LSI 2 accesses the shared memory 61, as a result of decoding the address from the communication LSI 2, the communication LSI shared memory access request signal 2b.
And participate in the arbitration of the shared memory access right. When the communication LSI shared memory access prohibition signal 3g is invalid, the communication LSI 2 can immediately acquire the shared memory access right.

[0051]

As described above, according to the first or second invention, the bus acquisition status signal of the DMA device or the CPU
Of the shared memory continuous access request signal and holds the access right to the shared memory.
It is possible to omit useless arbitration when the addresses are switched during continuous access of the device or CPU, and it is possible to shorten the continuous transfer time of data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a first invention.

FIG. 2 is a configuration diagram of an entire information processing apparatus to which the embodiment of FIG. 1 is applied.

FIG. 3 is a timing chart showing the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing an embodiment of the second invention.

5 is a block diagram of the entire information processing apparatus to which the embodiment of FIG. 4 is applied.

FIG. 6 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 7 is a configuration diagram of an entire information processing apparatus to which a conventional technique is applied.

FIG. 8 is a block diagram showing a conventional technique.

FIG. 9 is a timing chart showing the operation of the conventional technique.

[Explanation of Codes] 1 CPU 2 Communication LSI 3A, 3B Bus Arbitration Circuit 11 CPU Dedicated Memory 12 CPU Dedicated Bus 13 CPU Address Decode Circuit 14 Registers 16 and 25 Buffer 21 Communication LSI Dedicated Memory 22 Communication LSI Dedicated Bus 23 Communication LSI Address Decode Circuit 31, 33 Ready control circuit 32, 34 Buffer timing control circuit 15, 24, 35, 40, 42 OR circuit 36, 39, 41 AND circuit 37, 38 NOT circuit 61 Shared memory 62 Shared bus

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideki Ota 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Fuji Electric Co., Ltd. Incorporated (72) Inventor Shinichi Hiramoto 1 Fujimachi, Hino-shi, Tokyo Within Fujifacom Control Co., Ltd. (72) Inventor Atsuki Umehara 1 Fujimachi, Hino-shi, Tokyo Within Fujifacom Control Co., Ltd.

Claims (2)

[Claims] 1. A bus arbitration circuit that arbitrates an access right to a shared memory when access to the shared memory by a CPU and a DMA device having a sequential transfer function conflicts via a shared bus. Means for starting arbitration based on an access request signal, outputting a shared memory access valid signal by recognizing access to the shared memory by the DMA device as valid when the shared memory access right by the CPU is not acquired, and sharing by the DMA device A bus arbitration circuit comprising: means for holding a shared memory access right by a DMA device based on a bus acquisition state signal indicating a bus acquisition state and the shared memory access valid signal. 2. A shared memory access from a CPU in a bus arbitration circuit that arbitrates an access right to the shared memory when access to the shared memory by the CPU and a DMA device having a sequential transfer function conflicts via the shared bus. Arbitration is started based on the request signal, and means for recognizing the access to the shared memory by the CPU as valid when the shared memory access right by the DMA device is not acquired, and a means for outputting the shared memory access valid signal; A bus arbitration circuit comprising: means for holding a shared memory access right by the CPU based on a continuous access request signal for requesting continuous access and the shared memory access valid signal.