JP3264336B2 - Image conversion processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a storage medium,
Performs conversion processing on the data stored in the storage medium, and
The present invention relates to an image conversion processing device that stores image data again in a storage medium .

[0002]

[Prior art]

Japanese Patent Application Laid-Open No. 01-25224 [H1.1.27] Title "Memory Initialization Method in Microprocessor System" In this known example, an address and a size to be initialized are set, and a start signal is used. An object of the present invention is to speed up the initialization by DMA-transferring initialization data to each address of the memory corresponding to the size from the set address.

In order to achieve this object, a DMA circuit for executing memory initialization by DMA transfer is constituted by an address counter, a transfer number counter, a register, and the like, and initialization data is set in the register. . And MP
When the memory is initialized by the U, the address to be initialized is set in the address counter, and the transfer number is set in the transfer number counter. The start request signal from the MPU causes the bus use request creation circuit to control the timing control circuit via the priority control circuit. Start up,
Outputs the contents of registers and counters and writes them to memory. Further, the contents of the counter are updated each time DMA transfer is performed, and initialization data in a register is written in a predetermined area of the memory by the number of transfers.

[0004]

In the above prior art, it is necessary to set initialization data in a register by software every time an initialization request is made. In addition, during storage area initialization, bus arbitration is performed. CP while DMAC is bus master
U loses the bus right, and there is a problem that the instruction word cannot be fetched and the processing is stopped.

According to the present invention, the initialization data for initializing the storage area is held in a buffer, so that it is not necessary to set it by software every time an initialization request is made, and the initialization data is transferred continuously by DMA. It is an object of the present invention to speed up storage area initialization and speed up a system to which the present invention is applied.

Further, if image conversion processing is performed while the previously processed data remains, if the data is output to a printer or an output device similar thereto, unnecessary data appears as a printing defect. Data corresponding to dots and characters,
The image data is written to the image data storage area currently being processed by the image processing controller of the image conversion processing device. It will be different. In order to solve this problem, an object of the present invention is to perform an initial setting of an image conversion processing storage area by the above-described method to improve the quality of image output in a short time.

It is another object of the present invention to speed up a system to which the present invention is applied by guaranteeing a CPU processing operation during DMA performed at the time of storage area initialization.

[0008]

According to the present invention, in order to achieve the above-mentioned object, the present invention is connected to a storage medium, and stores the storage medium.
Performs a conversion process on the stored data and stores it in the storage medium.
An image conversion processing device for storing again, wherein the storage medium
An interface unit for transmitting and receiving data to and from the
Main memo that stores data transmitted and received via the face
And the interface unit and the main memory.
System bus, and an image used for performing the conversion process.
An image processing memory, and data in the image processing memory.
An image processing unit for performing a conversion process;
An image processing bus connecting the image processing unit and the image processing unit;
A main memory connected to the system bus and the image processing bus;
Between the image processing memory and the image processing memory
And an initialization bus controller for performing A-transfer.
The initialization bus controller initializes the image processing memory.
Initialization buffer that holds initialization data for performing initialization
The image processing in a state where the system bus is in use.
The initialization data is transferred to the image processing memory via a bus.
Initialization data transfer means for performing DMA transfer to the
The image processing memory is initialized .

[0009]

[0010]

[0011]

According to the above configuration, by initializing the initialization data in the hardware buffer in advance, the storage area can be initialized without setting the software.

When the DMAC is the bus master when the storage area is initialized, the bus connected to the CPU and the storage area
By separating the buffer for holding the initialization data and the bus connected to the control unit for initializing the storage area,
Since U can initialize the storage area without stopping the processing, the processing speed of the system can be increased.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail.

FIG. 1 is a system configuration diagram of an image conversion processing apparatus to which the present invention is applied. Reference numeral 1 denotes a magneto-optical disk storage device for recording image data and character data on a magneto-optical disk. Reference numeral 2 denotes an image conversion processing apparatus to which the present invention is applied, which performs drawing processing (image expansion / compression, line density conversion, etc.)
It is connected to the magneto-optical disk storage device 1 via the SI interface. Reference numeral 3 denotes a magneto-optical disk. Reference numeral 4 denotes a communication control device (hereinafter, referred to as “CS”) that performs interface conversion between the communication line 5 such as a public network and the LAN 6. Reference numeral 6 denotes a LAN (Local Area Network) for connecting the CS 4 to the magneto-optical disk storage device 1 and performing communication. A SCSI (Small) 7 connects the magneto-optical disk storage device 1 and the image conversion processing device 2 and transmits and receives data.
Computer System Interface
This is a communication interface called e).

The system operation of the image conversion processing device will be described below with reference to FIGS. FIG. 2 is a flowchart showing an outline of the operation of the image conversion processing device.

Image and character information data input via the communication line 5, CS4, and LAN 6 are stored in the magneto-optical disk storage device 1. The stored image and character information data is sent to the image conversion processing device 2 via the SCSI 7. The image conversion processing device 2 performs a drawing process on the image and character information data captured by the image conversion processing device 2. First, it is determined whether or not information data has been input (S5).
01). According to the contents of the image and character information data, the document containing the image and character is reproduced on the image processing memory, and the image is expanded (S502). Then, the magneto-optical disk storage device 1 converts the image into the specified image (S50).
2, S503, S504). Further, image compression is performed for efficient storage on the magneto-optical disk 3 (S505). After the completion of the image compression, the image conversion processing device 2 returns the processed image data to the magneto-optical disk storage device 1 (S50).
6).

The magneto-optical disk storage device 1 stores the returned image data on the magneto-optical disk 3. Here, the image and character information data input via the communication line 5 is also sent during the drawing process of the image conversion processing device 2.
Therefore, high-speed processing is required for the processing of the image conversion processing device 2 because improving the response to the magneto-optical disk storage device 1 improves the performance of the system.

FIG. 3 is a block diagram showing the internal configuration of the image conversion processing device 2.

Reference numeral 201 denotes a CPU for controlling the image conversion processing device 2. Reference numeral 202 denotes an initialization / bus controller for performing bus format conversion, DMA control, and initialization.
A controller unit 209 controls the SCSI interface, and is connected to a controller that controls the SCSI interface controller 209.
203 is a SCSI interface controller 209
And the image data and the character information data input from the SCSI interface are stored in the memory 204 by DMA, and the image data stored in the memory 204 after the drawing processing is transferred to the SCSI interface controller 209 by DMA. SCSI / DMA controller.

Reference numeral 204 denotes a main memory which stores a control program (software) of the apparatus, image and character information data to be transmitted / received via a SCSI interface, and image data after drawing processing. 205
Is a memory controller for controlling the RAS, CAS, and the like of the memory 204. 207 denotes an RA of the drawing processing memory
This controller controls S, CAS, read and write, and controls the image processing unit bus 214 and has a DMA function. A drawing processing memory 208 is connected to the bus / memory controller 207.

Reference numerals 210 and 211 denote image processing controllers, which perform expansion / compression of image data and character data stored in the memory 208, conversion of line density, and the like, and are connected to an image processing unit bus 214. A DMAC (Direct Memory Access Controller) 206 performs DMA transfer between the image processing memory 208 and the main memory 204 together with the bus / memory controller 207 through initialization / control of the bus controller 202. Reference numeral 212 denotes a system bus.
1. Connect the SCSI / DMA controller 203 and the like. 214, image processing controllers 210 and 211, image processing memory 208, bus / memory controller 20
7 is an image processing unit bus for connecting the image processing unit constituted by 7. A SCSI interface 216 is a communication line connected to the magneto-optical disk storage device 1.

FIG. 4 is an operation sequence chart of the image conversion processing device, and FIGS. 5 and 6 are supplementary diagrams for explaining the operation of the image conversion processing device.

In FIG. 4, 600, 670, 680,
There are three types of arrows, and the same type of arrow indicates processing of the same data.

In FIGS. 5 and 6, arrows indicated by 601 and the like indicate the direction in which data flows. The rectangular area showing the main memory 204 is a symbol conceptually showing the area of the storage area. Similarly, the image processing memory 2
The rectangular area indicated by 08 is a symbol conceptually indicating the area of the storage area. The area of the image processing memory 208 is assumed to be divided into three areas RBUF1 to RBUF3 for convenience of explanation. Each application is R
BUF1 and RBUF2 are areas for drawing processing, which are areas where image expansion, line density conversion, and 90 ° rotation are performed. RB
UF3 is the drawing process performed in RBUF1 and RBUF2,
This area stores data subjected to MMR compression. Hereinafter, the operation inside the image conversion processing device will be described with reference to FIGS. 3, 4, 5, and 6.

The image / character information data 1 input from the SCSI interface 216 is transferred to the main memory 204 by the SCSI / DMA controller 203 in the form of a DMA.
Stored by transfer (see FIG. 4 601, FIG. 5 No. 1)
reference). The stored image and character information data is stored in the DM
The AC 206 performs the DMA transfer between the image processing memory 208 and the main memory 204 together with the bus / memory controller 207 and performs the initialization / control through the bus controller 202. System bus 212, initialization / bus controller unit 202, bus / memory controller 207
Is stored in the RBUF1 of the image processing memory 208 (see 602 in FIG. 4 and item No. 2 in FIG. 5).

The stored image and character information data is reproduced on the memory by the image processing controller 210 as a document containing images and characters (image expansion) (FIG. 460).
3 and FIG. 5 item No. 3). At this time, the next information data 2
When 604 is input from the SCSI interface 216, it is stored in the main memory 204 by DMA transfer (see 605 in FIG. 4 and item No. 3 in FIG. 5). The document on the image processing memory 208 of the reproduced information data 1 is subjected to line density conversion, 90 ° rotation, and MMR compression drawing processing by the image processing controller 211 (see FIG. 4 606, FIG. 5 item No. 4). reference). The information data 2 604 of the next data is stored in the RBUF 2 (FIG. 46).
09, FIG. 5, item No. 4).

The image data that has been subjected to the drawing process is temporarily stored in the RBUF 3, and is stored in the bus / memory controller 207.
From the image processing memory 208 by the DMAC 206,
The path along which the image and character information data has passed is stored in the main memory in reverse order (see FIG. 4607, see FIG. 6, item No. 5). The information data 2 604 is subjected to image decompression (see FIG. 4 610, FIG. 5 item No. 4). The image data stored in the main memory is output by the SCSI / DMA controller 203 to the SCSI interface 216 via the SCSI interface controller 209, and returned to the magneto-optical disk storage device 1 (FIG. 4).
611, 612, FIG. 6, item No. 5).

The memory area where the drawing processing has been performed is a CP.
Initialized by instruction from U201 / Bus controller 2
02 and the bus / memory controller 207 initialize the designated area for processing the next information data (see 613 in FIG. 4 and item No. 6 in FIG. 6). Drawing processing is performed on the information data 2 for which image expansion has been completed (FIG. 46).
14, see FIG. 6, item 6). Further, the information data 3 sent from the magneto-optical disk storage device 1 during the drawing process is stored in the main memory 204 (see FIGS. 4 680 and 6).
15, FIG. 6, item 7), image processing memory 20
If the initialization of RBUF1 of 8 has been completed, RB
Transferred to UF1 (refer to FIG. 4 616, FIG. 6, item No. 7)
reference). If the initialization of the image processing memory RBUF1 has not been completed, the information data 3 is held in the main memory 204 and waits for the completion of the initialization until the initialization is completed.

Thereafter, the information data 2 670 and the information data 3 680 are subjected to the same processing as the information data 1 1600, and are returned to the magneto-optical disk device.

As described above, since the next image data is processed, the initialization can be performed at high speed, and the processing of the next data can be smoothly performed. Therefore, the system processing performance can be improved by making initialization faster.

Further, since information data of characters and images is input from the magneto-optical disk storage device even during the initialization, it is required that the processing operation of the CPU be continued for the control and the like.

FIG. 7 shows a circuit configuration example of the present invention, and FIG. 8 shows an operation timing chart of the circuit of the present invention.

Reference numeral 301 denotes a buffer for holding initialization data for initialization according to the present invention. Reference numeral 302 denotes a signal line connected to the ground for outputting initialization data to the bus. Reference numeral 303 denotes a three-state output flip-flop and a buffer for connecting the bus 214 and the local bus 213. 305, 306, and 307 are basic clocks of the bus 214 output from the bus / memory controller 207. 308 is a data transfer request signal (MBREQ2). Reference numeral 309 denotes a data transfer recognition signal (MBACK2) indicating that the address and data are valid. 310
Is a signal (CBUSW) indicating write during data transfer. Reference numeral 311 denotes an address valid signal (MBAEN) indicating that the address output to the bus 214 is valid.

The operation of the present invention will be described below with reference to FIGS. CPU 201 (CPU 201 is main memory 2
In this case, an initialization start address and the number of words to be initialized (the number of transfers) are set in the bus / memory controller 207 in response to an instruction to read the software on the CPU 04. CPU201
From the system bus 212 and the system bus 21
2, set in the bus / memory controller 207 via the buffer unit 303 and the image processing unit bus 214.

Next, a start instruction is given from the CPU 201 to the initialization start register 312. Upon receiving the start instruction, the initialization start register 312 sets the data transfer request signal (MBREQ2) 308 to true (low level) (see 401 in FIG. 8). Data transfer request signal (MBR
The bus / memory controller 207 whose EQ2) 308 is set to true makes the data transfer recognition signal (MBACK2) 309
Is true (low level) (see 402 in FIG. 8). When the data transfer recognition signal (MBACK2) 309 becomes true,
The initialization / bus controller 202 sets the data transfer write signal (CBUSW) 310 to true (low level) (403 in FIG. 8). Bus / memory controller 2
07 outputs a memory write address (404 in FIG. 8).
8), the address valid signal (MBAEN) 311 is set to true (high level) for the valid period of the address (405 in FIG. 8)
reference).

In the controller unit 202, the data transfer recognition signal (MBACK2) 309 is true (low level) and the address valid signal (MBAEN) 311 is false (low level).
8, the initialization data held in the initialization data holding buffer is output to the image processing unit bus 214 (FIG. 8).
406). The initialization data output to the image processing unit bus 214 is captured by the bus / memory controller 207 at the fall of the basic clock MBCLK4 (FIG. 8).
408). The data taken into the bus / memory controller 207 is written to the image processing memory 208 by the bus / memory controller 207. After fetching the data, the bus / memory controller 207 sets the data transfer recognition signal (MBACK2) 309 to false (high level) (see 409 in FIG. 8). Controller unit 20
2 detects a false (high level) of the data transfer recognition signal (MBACK2) 309 and outputs the write signal (CBUSW).
310 is set to false (high level) (see 410 in FIG. 8). Further, the output of the initialization data holding buffer 301 to the initialization data bus 214 is stopped (see 411 in FIG. 8).

At the time of the last transfer cycle, the bus / memory controller 207 sets the last transfer cycle signal (DTC) 315 to true (low level) (see 415 in FIG. 8). After recognizing that the transfer final cycle signal (DTC) 315 is true (low level), the initialization / bus controller 202 thereafter stops outputting the data transfer request signal (MBREQ2) 308 and ends the initialization. As described above, the bus cycle is continuously repeated by the DMA until the designated number of transfer words is completed.

As described above, initialization can be performed at high speed by holding the initialization data in the data buffer and continuously transferring the data by DMA. Further, the bus connected to the CPU 201, the image processing memory 208, and the control unit that DMA-transfers the initialization data and the bus that connects the buffer that holds the initialization data are separated by buffers, so that the CPU 201 can be continuously transferred. The initialization of the image processing memory 208 can be performed without affecting the arithmetic processing.

The effects of the system of this embodiment are as follows.

Since initialization is performed in 32 bytes / bus cycle, initialization of 6 MBytes takes the following time.
Initialization can be performed, while the operation of the CPU is guaranteed.

6 MByte / 32 (Byte / bus cycle) = 187500 bus cycle Time required for one bus cycle = 500 ns 500 ns × 187500 = 93.75 ms

[0042]

As described above, according to the present invention, by initializing the storage area by holding the initialization data in the buffer, it is not necessary to set each time when the system is started up. The processing can be reduced, the output of unnecessary data is suppressed, and the quality of image output data is improved.

Even during the initialization of the storage area, the operation of the CPU is guaranteed, so that the software processing can be continued and the processing speed can be improved.

As a result, the initialization of the storage area is speeded up, and the processing speed of the system is improved.

[Brief description of the drawings]

FIG. 1 shows a system configuration diagram of an image conversion processing apparatus to which the present invention is applied.

FIG. 2 is a configuration diagram showing the inside of an image conversion processing device to which the present invention is applied.

FIG. 3 shows a circuit configuration of the present invention.

FIG. 4 shows an operation timing chart of the circuit of the present invention.

FIG. 5 is a flowchart showing an outline of the operation of an image conversion processing device to which the present invention is applied.

FIG. 6 shows an operation sequence chart of the image conversion processing device to which the present invention is applied.

FIG. 7 is a supplementary explanatory diagram of the operation of the image conversion processing device to which the present invention is applied.

FIG. 8 is a timing chart of each signal in FIG. 7;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 magneto-optical disk storage device 2 image conversion processing device 3 magneto-optical disk 4 CS (communication server) 5 communication line 6 LAN (local area network) 7 SCSI (Small Computer System Interface) 201 CPU 202 initialization / bus controller unit 203 SCSI / DMA controller 204 main memory 205 memory controller 206 DMAC 207 bus / memory controller 208 image processing memory 209 SCSI interface controller 210, 211 image processing controller 212 system bus 214 image processing unit bus 216 SCSI interface 220 Main control of the device 221 Controlling the transmission and reception of internal data to and from the SCSI interface 301 Initialized data holding buffer 302 Initial Formatted data 303 Flip-flop with buffer 305 Basic clock (MCLK) 306 Basic clock (MBCLK2) 308 Data transfer request signal (MBREQ2) 309 Data transfer recognition signal (MBACK2) 310 Data transfer write signal (CBUSW) 311 Address valid signal (MBAEN) 312 Initialization start register signal 315 Data transfer last cycle signal (DTC)

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06T 1/60 450 G06F 13/28 310

Claims (1)

(57) [Claims] And a storage medium connected to the storage medium.
Performs a conversion process on the stored data and stores it in the storage medium.
An image conversion processing device for storing data again, wherein an interface unit transmits and receives data to and from the storage medium.
And data to be transmitted and received via the interface unit
And a system for connecting the interface unit and the main memory.
A system bus, an image processing memory used for performing the conversion processing, and an image for performing conversion processing of data in the image processing memory.
A processing unit, and an image connecting the image processing memory and the image processing unit.
An image processing bus, connected to the system bus and the image processing bus,
Transfer data between the main memory and the image processing memory
It has an initialization bus controller that performs DMA transfer with each other.
And the initialization bus controller includes the image processing memory.
Initialization buffer that holds initialization data for initializing the
Buffer and the system bus is in use.
The initialization data is transferred to the image processing bus via an image processing bus.
Initialization data transfer means for DMA transfer to the memory.
In addition, the image processing memory is initialized .
Image conversion processing equipment that.