JPH01129635A - Received fifo control circuit - Google Patents

Abstract

PURPOSE:To eliminate the reception frame causing overrun among plural reception frames and to receive other effective reception frames if a reception overrun takes place by providing an end bit detection circuit or the like. CONSTITUTION:A flag is detected from a signal X sent from a signal line 108 by a flag detector 101 and a frame synchronization is established, then the assembling of the received data is started via a serial/parallel conversion circuit 102. If a reception overrun takes place and it is detected by an overrun detection circuit 107 by using a use bit signal 115 and a write signal 112, the end bit detection circuit 106 detects the end bit of the closest end bit, that is, a 2nd frame end bit. Thus, the corresponding use bit from the write end till the end bit is all reset and only the ineffective frame due to overrun is eliminated and the remaining reception frame is receptible and it is read by the host system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial data receiving circuit, and particularly to a receiving FIFO control circuit when an overrun occurs.

[Conventional technology]

Traditionally, certain data communication protocols, such as HD
LC (High Level Data Link C)
As shown in Figure 5, a method for receiving serial data sent in frame format (ontrolProcedure), converting it into parallel data, and transmitting it to the host system uses a serial-to-parallel converter circuit as shown in Figure 5. A technique has been adopted that uses a multiplier circuit configured with a reception FIFO. This is an HDLC frame.
The signal X sent by signal line 507 in the format
is stored in the reception FIFO using the following procedure. First, when the receiving circuit becomes ready for reception, the receiving circuit enters a synchronous detection mode, and the 8-bit flag detection circuit 501 starts detecting the flag in the signal X received. This state continues until the first flag is detected. When the flag is detected and frame synchronization regarding the signal X is established, the flag detection circuit 501 activates the flag detection signal 508, transitions to a data reception state, and starts seven assembling of received data.

In the data reception state, the reception data 509 output from the flag detection circuit 501 is assembled into n-bit parallel reception data Y by the serial-to-parallel conversion circuit 502 for each predetermined bit length n. Each time the received data Y is assembled, it is transferred to the receive FIFO through the signal line 510. Normally, the reception FIFO has a FIFO configuration of several tens of stages. Each stage of the receive FIF○ has an n-bit wide data register 503 for storing received data Y, and a 1-bit use bit register 504.
and a 1-bit end bit register 505. The use bit register indicates that valid received data exists in each stage of the data register 503 in each stage of the receive FIFO, and the end bit register indicates that the last received data Y of the receive frame is present in the data register 503.
indicates that it exists. The flag detection function of the receiving circuit is valid even while receiving data, and when the flag is detected again after moving to the data receiving state, it is regarded as the end of one frame, and the last received data Y of the frame is stored in the data register 503. At the same time as writing, frame end signal 5
13 sets the end bit register 505. The receiving circuit uses the read end of the receiving FIFO.
Bit register 504 requests the host system to receive received data Y. The host system sequentially receives FIFs as long as the use bit is active.
1 by continuing to read received data Y from O and reading received data Y whose end bit is active.
Recognize the final data of each received frame.

If there is a delay in reading the received data Y by the host system, the received data Y will be buffered one after another in the receive FIFO, and eventually the receive FIFO will overflow, causing a receive overrun. The reception overrun occurs due to the write end use bit of the reception FIF○.
Use bit signal 5 stored in register 504
14 and write signal 5 of receive data Y to receive FIFO
11, the overrun detection circuit 506 detects this and transmits this to the host system.

When overrun detection signal 511 becomes active, the host system determines that all data in the receive FIFO is invalid.

By using the above method, the host system can transfer the received data sent in HDLC frame format to the receiving FI.
It is possible to know that a reception overrun has occurred in the FO.

[Problem that the invention seeks to solve]

According to the conventional method described above, all valid data stored in the receive FIFO becomes invalid due to the occurrence of a receive overrun. Therefore, when a plurality of receive frames exist in the receive FIFO, not only the receive frame in which the overrun occurred, but also all other valid receive frames in the receive FIFO are invalidated.

[Contents of the difference [originality] of the invention with respect to the prior art]

In the conventional receiving circuit described above, data in the receiving FIFO is invalidated all at once due to receiving overrun.
The present invention is unique in that the validity of received data is handled for each frame in the receive FIFO.

[Means for Solving the Problems] The reception FIFO control circuit according to the present invention is a reception FIFO control circuit that receives a serial signal X transmitted for each data block according to a predetermined data communication protocol in serial data communication. The circuit includes a serial-to-parallel conversion circuit that converts the signal X into n-bit parallel data Y, and a FIFO that stores the data Y.
a configuration data register; a use bit register indicating that valid data Y is present in the data register; the data Y stored in the data register is the last data of the data block; an end bit register that indicates that the data register has been written, an end bit detection circuit that detects the last end bit written in the data register, and an overrun detection circuit that detects that the data register has overflowed. The receiving FIFO control circuit is characterized in that, when an overrun occurs in the data register, only the data block in which the overrun has occurred is deleted from the data register.

[Example 1] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, 101 is an 8-bit flag detector that detects a flag from the signal X sent through the signal line 108 in HDLC frame format.
Establish a cycle with the C frame. Detection of the flag is transmitted to the serial/parallel conversion circuit 102 via a signal line 109. When the flag is detected and frame synchronization with respect to signal X is established, a transition is made to the data reception state and the assembling of the received data is started. In the data reception state, the serial-to-parallel conversion circuit 102 assembles the reception signal 110 output from the shift register 101 into n-bit parallel reception data Y for each predetermined bit length n, and outputs it to the signal line 111. be done. Each time the received data Y is assembled, a write signal 112 is generated.
is transferred to the data register 103 of the receive FIFO. Normally, the reception FIFO has a FIFO configuration of several tens of stages. Each stage of the receive FUFO includes an n-bit wide data register 103 for storing received data Y, and a 1-bit use bit register 1 that does not indicate the existence of received data Y.
04, a 1-bit end bit register 105 indicating that it is the last data of the received frame, and an end bit detection circuit 106 that has the function of finding the end bit closest to the write end of the receiving FIF○. Become. The flag detection function of the receiving circuit is valid even while receiving data, and when the flag is detected again after moving to the data receiving state, it is regarded as the end of one frame, and the last received data Y of the frame is stored in the data register 103. At the same time as writing, the end bit register 105 is set by the frame end detection signal 113 indicating the end of the frame. After this, the state shifts to the frame synchronization detection state again to receive the next frame. The receiving circuit requests the host system to receive the received data Y using the use bit register 104 at the top stage of the receiving FIFO.

The host system continues to sequentially read received data Y from the receive FIFO as long as the use bit at the read end of the receive FIFO is active, and by reading the receive data Y whose end bit is active, the host system reads the final data of one receive frame. Recognize.

If there is a delay in reading the received data Y by the host system, the received data Y will be buffered one after another in the receive FIFO, and eventually the receive FIFO will overflow, resulting in a receive overrun. The occurrence of a receive overrun is detected by the overrun detection circuit 107 based on the use bit signal 115 and write signal 112 stored in the use bit register 104 at the write end of the receive FIFO, and this is detected by the overrun detection circuit 107. The overrun detection signal 114 is used to convey the information.

Due to the reception overrun, the reception frame containing the reception data Y transferred from the serial-to-parallel conversion circuit 102 to the data register 103 of the reception FIFO becomes invalid. When the reception overrun detection signal 114 becomes active, the end bit detection circuit 106 detects the reception FI.
The end bit closest to the write end of the FO is searched from among the end bit registers 105, and all the use bit registers 104 on the write end side of the end bit are reset. That is, the use bits corresponding to all received data Y included in the frame in which the overrun occurred are reset. FIG. 2 shows the operation of each register at this time. Figure 2
As an example, a 12-stage reception FIFO is assumed.

As shown in FIG. 2, immediately after an overrun occurs, the data register 103 of the receive FIFO is full with received data, so each bit of the use bit register 104 is all "1 ++." If the frame in which this occurs is the third frame, then the end
The end bits of the two frames received immediately before should be "1°" in the pit register 105. Upon detection of an overrun, the end bit detection circuit 1
06 detects the end bit closest to the write end, that is, the end bit of the second frame. Upon detection of an end bit, all corresponding use bits from the write end to this end bit are reset.

By the above operation, only the frames that have become invalid due to overrun are deleted from the receive FIFO, and the remaining frames remain valid in the receive FIFO and the host
It can be read by the system.

By using the above method, the host system can transfer the received data sent in HDLC frame format to the receiving FI.
Even if a reception overrun occurs in the FO, only the reception frame in which the overrun occurred will be invalidated, and the reception frame
All other valid received frames in the IFO are available for reading by the host system.

[Embodiment 2] FIG. 2 is a block diagram showing the system configuration of Embodiment 2 of the present invention. This figure shows a configuration example in which a programmable end bit detection circuit is arranged in place of the end bit detection circuit in FIG. 1, and the other configurations are the same as in the first embodiment.

In the figure, 301 is an 8-bit flag detector, and 302
is a serial-to-parallel conversion circuit. Receive FIFO is data register 303, use bit register 3
04, end bit register 305, and receive F
It consists of a programmable end bit detection circuit 306 that has the function of finding the end bit closest to the write end of the IFO. Further, 307 is an overrun detection circuit.

Similarly to Embodiment 1, if the reading of received data Y by the host system is delayed while receiving serial data, the received data Y is buffered one after another in the receive FIFO, and eventually the receive FIFO overflows. , a reception overrun occurs. The occurrence of a reception overrun is detected by the overrun detection circuit 307 based on the use bit signal 315 stored in the use bit register 304 at the write end of the reception FIFO and the write signal 312.
detects and communicates this to the host system in a receive overrun detection signal 314.

Due to the reception overrun, the reception frame containing the reception data Y transferred from the serial-to-parallel conversion circuit 302 to the data register 303 of the reception FIFO at this time becomes invalid. When receive overrun detection signal 314 becomes active, end bit detection circuit 306 searches end bit register 305 for the end bit closest to the write end of the receive FIFO.

If the host system needs several bytes of information from the beginning of the frame, including the address field and control field, even if the host system has caused an overrun, it does not delete all the frames that caused the overrun. It is necessary to leave several bytes in the receive FIFO. Therefore, the end bit detection circuit 306 removes the preprogrammed leading data bytes from the frame in which the overrun has occurred, and resets all the remaining use bit registers 304 on the write end side. That is, the use bits corresponding to all received data Y except the first few bytes of the frame in which the overrun occurred are reset. FIG. 4 shows the operation of each register at this time. In FIG. 4, a 12-stage reception FIF is assumed as an example. As shown in FIG. 2, immediately after an overrun occurs, the data register 303 of the receive FIFO is full with received data, so each bit of the use bit register 304 is all par 1''.
′. Also, the frame in which the overrun occurred is 3
If it is the frame, the end bits of the two frames received immediately before should be "1" in the end bit register 305. By detecting the overrun, the end bit detection circuit 306 detects the end bit closest to the write end, that is, the end bit of the second frame. If the program is programmed in advance to leave the first two bytes, upon detection of the end bit, all corresponding use bits from the write end to the two bytes before the end bit are reset.

By the above operation, all but the necessary information at the beginning of the frames invalidated by the overrun are deleted from the receive FIFO, and the remaining frames remain valid in the receive FIFO and the post system can be read by.

With the above method, even if a receive overrun occurs in the receive data FIFO sent in the HDLC frame format, the host system invalidates only the receive frame that caused the overrun, and the receive FIFO
All other valid received frames within the host system can be read by the host system.

〔Effect of the invention〕

As explained above, according to the present invention, if a plurality of receive frames exist in the receive FIFO when a receive overrun occurs, other receive frames in the receive FIFO, excluding the receive frame that caused the overrun, Reception of all valid received frames is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a system using the present invention. In the figure, the numbers indicated are as follows. 101... Flag detection circuit, 102...
・Serial/parallel conversion circuit, 103... Data register, 104... Use bit...
Register, 105... End bit register, 106... End bit detection circuit, 10
7... Overrun detection circuit, 108...
...Received signal X1109...Overrun detection signal, 110...Received signal, 111...
・Received data Y, 112...Write signal, 1
13... Frame end detection signal, 114...
. . . Overrun detection signal, 115 . . . Use bit signal, FIG. 2 shows the state of each register when an overrun occurs. FIG. 3 is a block diagram showing the configuration of a system according to a second embodiment of the present invention. In the figure, the numbers indicated are as follows. 301...Flag detection circuit, 302...
・Serial/parallel conversion circuit, 303... Data register, 304... Use bit...
Register, 305... End bit register, 306... End bit detection circuit, 30
7... Overrun detection circuit, 308...
... Received signal X, 309 ... Overrun detection signal, 310 ... Received signal, 311 ...
・Received data Y, 312...Write signal, 3
13... Frame end detection signal, 314...
... Overrun detection signal, 315 ... Use bit signal. FIG. 4 shows the state of each register when an overrun occurs. FIG. 5 is a block diagram showing the configuration of a conventional system. 501... Flag detection circuit, 502...
・Serial/parallel conversion circuit, 503... Data register, 504... Use bit...
Register, 505... End bit register, 506... Overrun detection circuit, 507
......Received signal X, 508...Flag detection signal, 509...Received signal, 510...
...Received data Y, 511...Write signal,
512... Frame end detection signal, 513...
...Overrun detection signal, 514...Use bit signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In serial data communication, in a receiving circuit that receives a serial signal X transmitted in units of data blocks according to a fixed data communication protocol, a serial signal converts the signal・A parallel conversion circuit, a FIFO-configured data register that stores the data Y, and a data register that stores the data Y.
a use bit register indicating that valid data Y exists in the register; an end bit register indicating that the data Y stored in the data register is the last data of the data block; The last written end value from the data register.
It has an end bit detection circuit that detects a bit, and an overrun detection circuit that detects that the data register has overflowed, and when an overrun occurs in the data register, the A reception FIFO control circuit, characterized in that it deletes only the data block in which an overrun has occurred.