JPS6039972A - Picture processing system - Google Patents

Abstract

PURPOSE:To reduce a fitting space and to attain proper interfacing by providing a DMA control circuit so as to obtain a data transfer end signal of the screen to be formed based on a control signal used for a picture printer. CONSTITUTION:The output of a carry terminal R/C of a 4-bit counter 8 in a DMA control circuit 22 goes to a high level at each clock of a video clock VC16 and an unblank signal UB goes to a high level while the video clock VC is counted by the 4-bit counter 8, then the output of an AND gate 9 is obtained. As a result, when the leading edge of output of the carry terminal R/C is obtained, a memory address revision signal MS is obtained via an OR gate 13 and a data of the next 16-bit is read from a bit map memory.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to an image processing system that transfers image information stored as parallel data as serial data to an image printer configured using the so-called Carlson process, such as a laser printer. More specifically, the present invention relates to an image processing system 11 provided with an I) HA (die reflex 1-memory access) control circuit for transferring serial data synchronized with printing by an image printer.

The introduction of OA (office automation) systems is becoming more and more popular in order to streamline office work and save labor, but as various types of information become more complex, information input/output devices, etc. Intelligent technology is rapidly progressing along with the advancement of various technologies.

That is, these devices are controlled by a plurality of CPUs (central processing units) and are configured to organically process complex information. In this case, since the CPU directly handles digital signals, data exchange with its peripheral devices must naturally be processed digitally.

On the other hand, the information handled in OA systems is text,
Since it is necessary to consist of not only simple information media such as symbols but also complex information media such as images, there is a need for such complex information media to be easily processed within the system. .

However, as a matter of course, information media such as images have an extremely large amount of information compared to those such as characters, and data processing becomes extremely complicated. for example.

In character recording, if 4,000 characters are recorded per page on an A4 size document, the amount of information is approximately 30 bits, whereas in image recording, the amount of information is 12 bits per page on an A4 size document.
Approximately 1M if recorded at dot/(incorporated) resolution
Bytes of information are required. Of course, in order to process such a large amount of information, it is necessary to control the data by making full use of a large capacity memory, and accordingly it is necessary to take measures such as component arrangement and cost 1.

Incidentally, in an OA system, texts and images processed by each device in the system are not only converted into soft copies through means such as a CRT display, but also converted into hard copies through a predetermined printer. When converting into hard copies, the common method is to record text and image information as file data in memory, and then transfer the output of this memory all at once to a printer such as a laser printer. There is. In this case, if image information is included, the amount of information is large, so data can be exchanged directly between the memory and printer without going through the CPU, and data transfer can be controlled using the MA (direct memory access) method. It is being done.

However, conventional DMA control circuits are unsatisfactory for processing large amounts of data, such as the range in which they can directly access memory is small.

Furthermore, since it is difficult to match the printer control process and the control timing of the control signals, attempts to optimize these will increase the number of so-called external circuits and complicate the circuit configuration.

This invention was made by paying attention to such conventional problems, and is an OA system, especially an image processing system for transmitting images, which are complex information, and which has a system bus and an image processing system. An object of the present invention is to provide an image processing system in which an interface for connecting to a printer is provided with a new MA control circuit that can efficiently transfer image information data from a memory to a printer.

□ Figure 1 explains the image processing system of this invention, and the bitmap memory 1 constituting the storage section stores image data read from an image processing device (not shown) and large-capacity storage such as a so-called file station. The image data and the like stored in the storage unit are stored. The image data in this bitmap memory 1 is transferred to a laser printer 4 as an image printer via a system bus 3 whose use is controlled by an interface 2, and the data transfer by the interface 2 is from the CPU 5. It is controlled by the command of

Next, FIG. 2 shows the relationship between various signals in the laser printer 4, and the video clock VC (FIG. 2 (A)), which is the reference of the image signal, is used for the horizontal direction of the screen created by the laser printer 4, for example. 1 scanning period VH
T appears for a certain period of time every time. Further, a horizontal synchronizing signal H5 (FIG. 2(B)) for determining the point in time at which printing actually starts is obtained for each scanning period Vll. Furthermore, when the horizontal synchronization signal H5 is obtained, the unranked signal UB is obtained (Fig. 2 (C)).
), an actual printing period P is determined during the high level period of this unblank signal UB, and during this period P, parallel image takes from the bitmap memory 1 synchronized with the video clock are serially output to the laser printer 4. (Figure 2 (D)).

Next, FIG. 3 shows an embodiment of the DMA control circuit 22 applied to the image system according to the present invention, in which a data latch circuit 6 is connected to the take bus OB constituting the system bus 3. , this taber latch circuit 6
The output of, for example, 16-bit parallel data is supplied to the shift 1 register 7. Also, this Schiff 1~
Serial data SD is output from the output terminals S and 0LIT of the register 7, and this serial data SD is supplied to the laser printer 4. Further, a video clock VC is supplied from the laser printer 4 to the clock terminal CLK of the shift register 7, and this video clock VC is also supplied to the clock terminal CLK of the 4-bit counter 8. Furthermore, these 4
The unblank signal 013 is supplied from the laser printer 4 to the load end LO of the bit counter 8, and the carry end R/C of this 4-bit counter 8
is connected to the load end LO of the shift register 7.

Further, the unblank signal UB is supplied to one input terminal of the AND gate 9, and the carry one terminal R/C of the 4-bit counter 8 is connected to the other input terminal of the AND gate 9. Furthermore, the horizontal synchronization signal Its output from the laser printer 4 is output from the rising edge detection circuit I.
The output of this detection circuit 10 is supplied to OR games 1 to 1.
] ■ is supplied to one input end of the. The output of the rising edge detection circuit 12 is supplied to the other input terminal of the OR gate 11, and one input terminal of the OR games 1 to 13 is connected thereto. Note that an ant game 1 is connected to the other input terminal of this OR gate 13.
9 are connected, and the output of the OR gate 13 becomes a memory address update signal MS as a control signal for the interface 2.

On the other hand, the rising edge detection circuit 12 receives the DMA start signal AS from the interface 2 and detects the rising edge thereof. This leaf^ start signal A5
is obtained by receiving the output ET of the falling edge detection circuit 14, and this falling edge detection circuit 1
4 is a circuit for detecting the falling edge of the unblank signal LiB. Furthermore, the output of the falling edge detection circuit 14 is supplied to one input terminal of an OR gate 15 11. The output of the line number counter 16 is supplied to the other input terminal of the OR games 1 to 15. This line number counter 16 receives a horizontal synchronizing signal +
It counts 15 pulses. Further, the output of the OR gate 15 is supplied to the reset terminal 1 to terminal R of the 1 (-S flip-flop 17), and the output of the OR gate 1-11 is supplied to the set terminal S of this flip-flop 17. The output terminal Q of this flip-flop 17 outputs t to the system bus 3.
A path request signal BR for obtaining the L bus is obtained.

Further, one input terminal of an AND gate 18 is connected to the output terminal Q of the flip-flop 17, and the other input terminal of the AND gate 18 is connected to the bus!
Address/data enable signal AD supplied when
is now entered. In addition, and gate 1
From the output terminal of 8, a hash override signal BO which is output towards the system bus 3 and continues to be output while the bus is acquired is obtained. Further, the address/cheeter enable signal AD is supplied to each input terminal of the gate 19 along with the access signal AK necessary for latching the image data from the system bus 3. And this anime game-1-1
The output of 9 is supplied to the clock terminal CLK of the double data latch circuit 6, and is also supplied to the terminal R of the recess 1 of the R-S flip-flop 20. Further, an or gate 13 is provided at one end S of the cell 1 of this flip-flop 20.
The output terminal Q of the flip-flop 20 provides a memory 1-command signal which is outputted to the system bus 3 via the delay line 21.

Next, the operation of the DMA control circuit 22 will be explained with reference to FIGS. 4 and 5. First, FIG. 4 shows the relationship of each signal when acquiring the system bus 3. When the interface 2 instructs the laser printer 4 to start printing an image, the laser printer 4 outputs an unblank signal. LIB is obtained (FIG. 4(B)), and when a falling edge (for example, Pi) of this unblank signal UB is detected, a DMA start signal As is obtained (FIG. 4(D)).

Then, upon receiving this DMA start signal As, the rising edge detection circuit 12 operates, so that the output of the OR gate 11 sets the flip-flop 17, and as a result, the hash list signal BR becomes high level (FIG. 4(E)).
). Note that FIG. 4(A) shows the video clock signal VC, and this video clock signal VC and the horizontal synchronization signal H3
(FIG. 4(C)) and the relationship with the unranked signal UB are as described above in the explanation of FIG.

If system bus 3 can be acquired in this way, system bus 3
The address/data enable signal AD is obtained through (FIG. 4(F)), but in this case, the address/data enable signal AD is delayed by a delay time t from the rising edge P2 of the request signal BR. Get up late. Furthermore, when the address/cheat enable signal AD is obtained, the bus override 1 is sent via the ant game 1-18.
A bus override signal BO is output (FIG. 4(G)), and this bus override signal BO remains at a high level until the bass reflexist signal BR falls to a low level, during which time the system bus 3 continues to be acquired.

In this way, when the data transfer of the first scanning line v111 of the screen to be printed 1 is completed, the unblank signal UB becomes low level, and at the same time, the bus override Shinzuki BO is made low level and its falling edge P:] By detecting this, the flip-flop 17 is reset through ordays 1 to 15. As a result, the path request]-signal BR and bus override signal BO become low level, and acquisition of the system bus 3 is stopped.

For the second scanning line v112 and subsequent lines, the horizontal synchronization signal I
By detecting the rising edge P4 of Is, the flip-flop 17 is set to the set state via OR days 1 to 11, and bus acquisition is stopped at the falling edge of the unrank signal UB, as described above. Note that when the line number counter 16 counts the horizontal synchronizing signal by the preset number of lines on the screen, an output OF as an overflow signal is obtained (FIG. 4 (H)). Therefore, the rising edge of the horizontal synchronizing signal H5 The flip-flop 17, which has been in the reset 1- state, is changed to the reset 1-state by the output of the orday h15, and the data transfer to the laser printer 4 is completed. That is, line number counter 1
When the output OF of No. 6 becomes high level, the bus request signal 13R, bus override signal BO1 and address/data enable signal AD each become low level.

Next, FIG. 5 shows the relationship of each signal when reading parallel data stored in the bitmap memory 1 via the system bus 3, converting it into serial data, and outputting it to the laser printer 4. It is. First, when the rising edge PS of the DMA start signal As from the interface 2 is detected (FIG. 5(A)), the memory address update signal MS is obtained via the OR gate 13 (FIG. 5(B)).

When this memory address update signal MS is output, the flip-flop 20 enters the cell 1-state, but in this case, the initial memory address is changed to the address one address before the address to be read for the first time. Make sure to keep it.

In this way, the updated address is output to the interface 2, and along with this, a memory read command signal delayed by the delay time D2 from the cell 1~ state of the flip-flop 20 is output to the system bus 3 via the delay line 21. Output signal (Figure 5 (C)).

On the other hand, in bitmap memory 1, system bus 3
According to the address and memory read command signal MR output toward the memory read command signal MR, for example, the pin I to map data for 16 bits 1 is output, and the access signal A/K is output (FIG. 5(D)). In this case, the bus is being acquired in interface 2, and the address/data enable signal AD is at high level, and the access signal AK is also at high level accordingly. The flip-flop 20 is put into a reset state. Also, since the output of this AND gate 19 is supplied to the data latch circuit 6, it launches the pin 1-map data block on the system bus 3 (fifth
Figure (E)). Further, the output of the flip-flop 20 is delayed by a delay time D3 by the delay line 21, thereby setting the memory REET command signal to a low level.

Note that when the unblank signal LIB is at a low level (FIG. 5(G)), the 4-bit counter 8 is always in a loaded state, while a high-level output is obtained from the carry end R/C (Fig. 5(G)). 5 (H)), shift 1 to register 7 are loaded with 16-bit parallel data output from data latch circuit 6. Furthermore, assuming that the laser printer 4 outputs the unblank signal UB and is ready to accept data, the 4-pin 1-counter 8 counts the video clock and makes the carry end R/C high every 16 clocks. level (Figure 5 (F))
, (II)). When the output of this carry end R/C is at a low level, the shift register 7 synchronizes the loaded 16-bit data with the video clock VC and converts it one bit at a time, that is, serial data SD
output to the laser printer 4 as

As mentioned above, one end of the carry of the 4-bit counter 8 R/
The output of C becomes a high level every 16 clocks of the video clock VC, and while the video clock VC is being counted by the 4-pin 1-counter 8, the unblank signal UB is at a high level.
Outputs from 1 to 9 are obtained. As a result, one end of carry R/C
When the rising edge P5 of the output of is obtained, OR gate 1
3, the memory 1 address update signal MS is obtained, and the next 16 bits of data are transferred to the bitmap memory 1.
It becomes possible to read from. This read operation is repeated while the unblank signal uB is at a high level, but the data transfer for the first scanning line ends when the unblank signal UB becomes a low level (see Fig. 4 (B)). . For the second scanning line and subsequent lines, all the readout of the pin 1 to map data is performed by the output of the carry end R/C of the 4 pin 1 counter 8 and the output of the AND gate 9 obtained based on the unrank signal UB. The read operation is repeated until the output OF'h'N of the line number counter 16 is obtained.

In the above embodiment, the number of bits of the parallel data is set to 16 bits, but it may be set to 8 bits or 12 bits depending on the configuration of the bitmap memory 1 and the system bus 3. There is no difference. However, if other pins are set from 1 to a number, the output of the carry end rl/C of the 4-bit counter 8 will be obtained every 8th clock, 12th clock, etc. of the video clock VC according to the number of bits. .

As described above, according to the present invention, image information is read out from a storage section that stores parallel data via a single system bus, and the read data is converted into serial data. In an image processing system configured to convert data into image data and transfer it to an image printer, an MA control circuit is provided to obtain a data transfer completion signal for the screen to be created based on the control signal used in the image printer. An image processing system that eliminates the need for a special sensor and its attached circuits to complete the transfer, reduces the installation space, and allows for the optimal configuration of the interface between an image printer such as a laser printer and the system bus. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an image processing system to which the present invention is applied; FIG. 2 is a time chart illustrating the relationship between various signals exchanged between the interface shown in FIG. 1 and the laser printer; Fig. 3 is a circuit diagram illustrating the I) MA control circuit according to the present invention, Fig. 4 is a time chart illustrating the operation of the DMA control circuit when the system bus @ 1:00 p.m., and Fig. 5 is a circuit diagram of the image data. 3 is a time chart illustrating details of a read operation. ■ - Map memory (storage unit), 2...Interface, 3...System bus, 4...Laser printer (image printer), 16...Line number counter.

Claims (2)

[Claims] (1) A storage unit that stores image information as parallel data, an interface that reads out the parallel data in the storage unit via the system bus and converts the parallel data into serial data, and a storage unit that stores the serial data transferred from the interface. While printing an image in synchronization with the image clock signal, it outputs a horizontal synchronizing signal for each scanning line of the screen created by the image printer 1-, and also determines the image data acceptance period for each scanning line. In an image processing system equipped with an image printer that outputs an unranked signal, when the pulses of the horizontal synchronizing signal are counted and the pulses are repeated by the number of scan lines of the screen to be created, image data is generated. 1. An image processing system comprising: a DMA control circuit provided in an interface connected between the system bus and the image printer; (2) The image processing system according to claim 1, wherein the counter runs an edge of an unblank signal instead of a pulse of a horizontal synchronizing signal.