JP2998666B2 - Serial Digital Data Format Conversion Method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial digital data format conversion method for converting serial digital data transferred according to a certain format into another format.

[0002]

2. Description of the Related Art Conventionally, in order to perform bit conversion and rate conversion of serial digital data, serial data is once converted into parallel data, and the parallel data is converted using a bit conversion or rate conversion circuit. later,
It was converted to serial data again.

FIG. 3 is a functional block diagram showing the prior art. Hereinafter, description will be made based on this drawing.

[0004] First, by entering the serial digital data S ₁₁ to the serial / parallel conversion IC 101, converted into parallel data. Subsequently, the parallel data is converted into a desired format by the bit conversion and rate conversion IC 102. Finally, before outputting the converted again into serial data as serial digital data S ₁₂ by the parallel / serial conversion IC 103.

[0005]

However, the prior art has the following problems.

[0006] The first problem is that a circuit for performing serial / parallel conversion once and converting it into serial again and its control are required. The reason is that serial
This is because the processing is performed after the digital data is once converted into the parallel digital data.

A second problem is that in the case of data rate conversion, if the phase relationship between the input and output is asynchronous, a memory is required in the middle, so that the control is further complicated. The reason is that it is necessary to hold data between input and output, and it is necessary to consider the delay amount of each IC when the number of memories increases.

[0008]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a serial digital data format conversion method which can simplify a circuit configuration and a control method.

[0009]

According to the present invention, there is provided a serial communication device.
The format conversion method for digital data is serial
・ Data input terminal for inputting digital data, write
Write reset control terminal for inputting reset signal
Write enable control input terminal
Clock control to input the write clock signal
Terminal, data output to output serial digital data
Input terminal, read reset to input read reset signal
Control terminal, read rice to input read enable signal
Cable control terminal and output enable signal
Output enable control terminal and read clock
Providing a read clock control terminal for inputting signals
More writing and reading to be controlled asynchronously,
First-in / first-out memory (hereinafter "F
IFO memory ". ) Using the write reset
Signal, write enable signal and write clock signal
More, after writing the serial digital data to the first-in first-out memory in accordance with the format, the read reset signal, Lee
Output enable signal, output enable signal and
The serial clock written by the
Digital data is read from the first-in / first-out memory in accordance with another format. Format conversion includes bit conversion and rate conversion

In the present invention, the format conversion of serial digital data is performed only by controlling the input / output of the FIFO memory. Therefore, the number of ICs to be controlled
Only the number of O memories is sufficient, and in addition to this, there is no need to worry about latch errors due to differences in timing between different ICs.

[0011]

FIG. 1 is a functional block diagram showing an embodiment of the present invention. Hereinafter, description will be made based on this drawing.

The FIFO memory 10 has a data input terminal 1, a write reset control terminal 2, a write enable control terminal 3, a write clock control terminal 4, a data output terminal 5, a read reset control terminal 6, a read enable control terminal 7, an output By providing the enable control terminal 8 and the read clock control terminal 9, writing and reading can be controlled asynchronously. Also,
The data output terminal 2 is connected to a pull-down resistor 12.

The serial digital data S1 is FI
When input to the FO memory 10, the serial digital
The data is written into the FIFO memory 10 by a write reset signal S2, a write enable signal S3, and a write clock signal S4 that match the format of the data S1.

The data written in the FIFO memory 10 includes a read reset signal S6, a read enable signal S7 for matching the format of the data to be output,
The serial digital data S is converted by the output enable signal S8 and the read clock signal S9.
2 is output from the FIFO memory 10. At this time, the output of data having an unstable level is prevented by the pull-down resistor 12.

FIG. 2 is a timing chart showing the operation of the FIFO memory 10. Hereinafter, description will be given based on FIG. 1 and FIG.

First, a general concept will be described. When continuous serial digital data S1 is input from the data input terminal 1 to the FIFO memory 10, the write reset signal S2 is dropped to "L" once for several blocks, and the write enable signal S3 is changed to "L" only in a section where data exists. L ", and the data is recorded in the FIFO memory 10 by the write clock signal S4 along the input data.

The data recorded in the FIFO memory 10 is
When the read reset signal S6 is dropped to "L" and the read enable signal S7 and the output enable signal S8 are dropped to "L", data can be obtained from the data output terminal 5 as data in accordance with the read clock signal S9. .

The rate conversion can be performed as shown in FIG. 2 by changing the read clock signal S9 and the read enable signal S7 on the read side to the write side. In the bit conversion, in the case of bit reduction, only the necessary bits are output by setting the output enable signal S8 to the "H" level only for the bit portion that reduces the output enable signal S8. At this time,
The masked period is undefined as data, but is fixed at “L” by the pull-down resistor 12.

Next, a lower concept will be described. When serial 4-bit serial digital data S1 is input from the data input terminal 1 to the FIFO memory 10, the write reset signal S2 is set to start the data A1 so that three of the data A1, B1 and C1 form one block. Immediately before, the write clock signal S4 is dropped to "L" for one clock,
The write enable 13 is fixed at "L".

At this time, in order to obtain the output data from the data output terminal 5 with the intermittent upper 3 bits and the transfer rate doubled from the data output terminal 5, the read reset signal S6 is output immediately before the data is output by one clock of the read clock signal S9. Drop to minute "L". Thereby, the read enable signal S
7 is set to "L" for four clocks to output the output enable signal S8.
At the same time, if it is set to "L", bit conversion and rate conversion of the serial digital data S1 are possible.

[0021]

The first advantage is that the circuit configuration and control method can be simplified because only one FIFO memory is required for the format conversion of serial digital data. The reason is that writing and reading of the FIFO memory are asynchronous, so that input and output can be separately controlled as serial digital data without conversion to parallel digital data.

A second advantage is that control is easy and accurate for bit conversion and rate conversion of serial digital data. The reason is that the IC
Is a single FIFO memory, and it is not necessary to take into account matching between ICs.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the FIFO memory of FIG. 1; FIG. 2 [1] shows serial digital data (input data); FIG. 2 [2] shows a write reset signal; [3] shows a write enable signal, and FIG. 2 [4] shows a write clock signal.
[5] shows serial digital data (output data), and FIG. 2 [6] shows a read reset signal.
[7] shows a read enable signal, and FIG. 2 [8] shows an output enable signal.

[9] indicates a read clock signal.

FIG. 3 is a functional block diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 data input terminal 2 write reset control terminal 3 write enable control terminal 4 write clock control terminal 5 data output terminal 6 read reset control terminal 7 read enable control terminal 8 output enable control terminal 9 read clock control terminal 10 FIFO memory 12 pull-down resistor S1 Serial digital data (input data) S2 Write reset signal S3 Write enable signal S4 Write clock signal S5 Serial digital data (output data) S6 Read reset signal S7 Read enable signal S8 Output enable signal S9 Read clock signal

Claims (3)

(57) [Claims] 1. A serial digital data format conversion method for converting serial digital data transferred according to a certain format into another format, wherein a data input terminal for inputting the serial digital data.
Reset control to input the write reset signal
Pin, write enable to input write enable signal
Control pin, write clock signal input
Output pin, serial digital data
Data output terminal, lead for inputting read reset signal
Reset control terminal, reset for inputting the read enable signal
Mode enable control terminal, output enable signal
Output enable control terminal and lead for inputting
Equipped with a read clock control terminal for inputting a clock signal
You can control the writing and reading asynchronously by Rukoto
The write reset signal, the write enable signal, and the
After writing the serial digital data into the first-in / first-out memory in accordance with the format thereof by the write clock signal, the read reset signal, read enable signal,
The output enable signal and the read clock signal
And reading the written serial digital data from the first-in / first-out memory in accordance with another format. (2)The serial digital data
Data from the data input terminal to the first-in
When input to the last out memory,
Once the write reset signal is dropped to "L" and the data
The write enable signal drops to “L” only during the section
And the write clock signal along the input data
The first-in first-out memory
Record the data The read reset signal is dropped to “L” and the read
The enable signal and the output enable signal
While falling to “L”, the read clock signal According to the issue
First-in first-out data
From the data output terminal
Output, The serial digital data format according to claim 1.
Conversion method. 3. The read clock signal and the read rice signal.
Cable, the write clock signal and the write enable signal.
Perform rate conversion by changing the
Or reduce the output enable signal
By setting only the bit portion to “H”, the bit
3. The method according to claim 2 , wherein a bit conversion is performed .