JPH027284A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit provided with an output circuit in which no read error of data is generated by providing an output buffer circuit to read out the output of a latch circuit to the outside by a readout signal from the outside, and a NOR circuit to take the NOR of the clock signal of an internal logic circuit and the readout signal and to drive the latch circuit. CONSTITUTION:The content of a memory circuit 10 is written on a latch 30 by a signal after a clock (phi) passes a NOT gate 40. At this time, when a high level as the signal to read out the data is inputted to the NOR gate 40, the output of the NOR gate 40 goes to a low level, and the data in the latch 30 is held, and also, is outputted to the outside via an output buffer 20. Here, even when the readout signal arrives at a time when new data is inputted to the latch 30 by the clock (phi), and the output of the NOR gate 40 is fixed at the low level, and latching is prohibited, dispersion in the delay of input is scarcely generated since the latch 30 exists inside the integrated circuit. In such a way, it is possible to realize the integrated circuit possible to perform the readout of the data stably by an asynchronous signal from the outside.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit configuration of a logic integrated circuit.

[Conventional technology]

There is a demand for reading the stored contents of a logic circuit inside an integrated circuit, which operates according to a synchronous clock, from the outside asynchronously with respect to the clock of this integrated circuit.

The present invention realizes an integrated circuit that can stably read data during data reading in such a case.

Figure 3 shows an example of a conventional circuit configuration in such a case, which consists of a memory circuit 10 and an output buffer 20, and the memory circuit IO is connected to the internal logic, and when the contents change, it is output from the internal logic at a timing synchronized with the internal clock. data is stored.

The contents of the storage circuit 10 are output to the outside through the output buffer 20. In this example, output buffer 20 is controlled by an external read signal. Therefore, the contents of the memory circuit 10 are outputted regardless of the timing of the internal logic.

[Problem to be solved by the invention]

Since the read signal applied to the output buffer 20 from the outside is an asynchronous signal from the outside, the contents of the memory circuit 10 may be written while the data is being read. For example, in a system that latches the read result in an external latch at the end of the read signal, when reading data consisting of multiple bits, due to variations in the output delay of each bit, even the data before rewriting may be different from the data after rewriting. This may result in unspecified data (ie, undefined data) being read.

SUMMARY OF THE INVENTION An object of the present invention is to obtain an integrated circuit with an output circuit free from errors in data reading.

[Means to solve the problem]

According to the present invention, there is provided an internal logic circuit, a latch circuit that latches the contents of the internal logic circuit, an output buffer circuit that reads out the output of the latch circuit to the outside using a read signal from the outside, and a clock signal and a read signal of the internal logic circuit. An integrated circuit is obtained, which includes a NOR circuit that performs a NOR operation with the NOR circuit and drives a latch circuit.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, including a memory circuit IO, an output buffer 20, a latch 30, and a NOR gate 4.
Contains 0. The memory circuit 10 is connected to internal logic, and when the contents change, they change at a timing synchronized with the internal clock.

The contents of this memory circuit 10 are input to a latch 30. The input to latch 30 is controlled by the output of NOR gate 40. A clock φ and a data read signal, which are signals synchronized with the basic clock of the internal logic and whose cycle is faster than the rewriting of the memory circuit IO, are input to the NOR game 40. This data read signal is generated from, for example, a chip select signal and a read signal for the integrated circuit. The output buffer 20 has the latch 30 as an input, and its output to the outside is controlled by a read signal.

Next, the circuit operation will be explained.

Normally, the contents of the memory circuit 10 are written into the latch 30 with a signal after the clock φ passes through the NOR gate 40.

Here, the high level is NOR as a data read signal.
When entering the gate 40, the output of the NOR gate 40 becomes low level, and the data in the latch 30 is held and output to the outside through the output buffer 20.

Here, when a read signal arrives while new data is being input to the latch 30 by the clock φ, the output of the NOR gate 40 is fixed at a low level, and the latch 30 is prohibited from latching the signal from the storage circuit 10. However, since the latch 30 is in an integrated circuit and there is almost no variation in input delay, the above-mentioned problem is unlikely to occur. The embodiment shown in FIG. 2 further takes this variation into consideration, and the NOR gate 4
By using the result of sampling an external read signal by the latch 50 with the clock φ as the read signal inputted to 0, the prohibition of the read signal and the writing of the latch 40 are synchronized.

〔Effect of the invention〕

As described above, the present invention can realize an integrated circuit that can stably read data using an asynchronous signal from the outside.

[Brief explanation of the drawing]

FIG. 1 is a block diagram according to one embodiment of the present invention, and FIG. 2 is a block diagram according to another embodiment of the present invention. FIG. 3 is a block diagram showing a conventional readout circuit. 10...Memory circuit, 20...Output buffer, 30...Latch circuit, 40...N
OR gate, 50...Latch circuit. jρ：Rat 壬

Claims (1)

[Scope of Claims] 1. A memory circuit having a built-in logic circuit that operates based on a clock signal and whose contents change depending on the operation of the internal circuit, and at least a part of the memory contents of the memory circuit are controlled by the operation of the logic circuit. In an integrated circuit that can be read from the outside by an external signal asynchronous to the clock signal, the contents of the memory circuit are read to the outside via a latch that is read by a signal synchronized with the clock signal, and the signal reading of this latch is inhibited by the external signal. 2. The integrated circuit according to claim 1, wherein the prohibition of reading of the latch is performed using a signal obtained by sampling the external signal with a signal synchronized with the clock signal.