JPH06150663A - Storage circuit - Google Patents

Abstract

PURPOSE:To start writing in a built-in storage circuit capable of reading and writing sequential file access within a display driving circuit, etc., without the waiting time. CONSTITUTION:A flip-flop group constituting an address selecting shift register 5 is composed of a flip-flop 1 with a set terminal and flip-flops 2-4 with reset terminals. A writing demand signal 15 is inputted to the flip-flop with a set terminal as a setting signal and to the flip-flops 2-4 with reset terminals as a resetting signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a readable / writable memory circuit capable of changing addresses in order.

[0002]

2. Description of the Related Art Conventionally, since a display data storage circuit incorporated in a display drive circuit has to read data in order at all times during display, random access is not required, and an address to be accessed is not required. Just shift in order. In the case of random access, a decoding circuit is required to generate an address selection signal from the input address signal, but a shift register may be used to shift addresses in order. Therefore, the display data drive circuit may have a considerably small circuit scale.

Also, when rewriting data, not all of the data is normally rewritten, but all of the data is rewritten. Therefore, if the start address is detected, the data can be input at the same time as the address switching timing. You can rewrite data in order without worrying about it.

[0004]

However, in the case of the above-mentioned conventional memory circuit, the start address must be detected when rewriting data, which causes a problem of waiting time.

It is an object of the present invention to enable a sequential file access readable / writable storage circuit built in a display drive circuit or the like to start writing without waiting time.

[0006]

According to the present invention, there are provided first to Nth flip-flops whose outputs are respectively connected to first to Nth (N is an integer of 2 or more) address selection signal lines. In a readable / writable memory circuit including a shift register for address selection, one set signal terminal of the first to Nth flip-flops and one of the first to Nth flip-flops A storage circuit is obtained in which a supply line for a write request signal is connected to the reset signal terminals of the remaining flip-flops.

Further, according to the present invention, a memory circuit is obtained in which one of the first to Nth flip-flops is the first flip-flop.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory circuit according to an embodiment of the present invention. The memory circuit of this embodiment includes a shift register 5 for address selection. The shift register 5 includes a flip-flop with a set (hereinafter referred to as “FF with S”) 1 and flip-flops 2 to 4 with reset (hereinafter referred to as “FF with R”). The outputs of the FF1 with S and the F2 to 4 with R are the address selection lines 11 to 14,
In addition, they are connected to the select gates in the memory cells 6 to 9, respectively. The memory cells 6 to 9 have bit lines 16 and 1 respectively.
7, a pair of MOS transistors 18 and 19 that form the selection gate, and inverters 20 and 21 that are provided between them. Incidentally, illustration of the inside of the memory cells 7 to 9 is omitted for convenience.

The front-stage clock φ1 and the rear-stage clock φ2 are input to the S-FF 1 and the R-FFs 2 to 4, respectively. The write request signal 15 is applied to the set signal of the FF 1 with S and the reset signal of the FFs 2 to 4 with R.
Are input respectively.

FIG. 2 is a timing chart showing the operation of the memory circuit of the embodiment. The operation of the embodiment will be described with reference to FIG. First, when the output of the FF with R 2 is “H”, the FF with S 1 and the other FFs 3 and 4 with R are outputs “L”. Then, the selection gate of the storage cell 7 connected to the FF with R 2 via the address selection line 12 is opened, and the data of the storage cell 7 is read out via the bit lines 16 and 17.

Further, at this time, in response to the input of "H" of the clock .phi.1 of the preceding stage, the FF with R 3 fetches the output "H" of the FF with R 2 in the preceding stage. Next, when the "H" input of the latter clock φ2 is received, the data "H" of the former stage is transmitted to the latter stage of the FF with R 3 and becomes the output "H". At this time, FF2 with R
Similarly, the preceding stage data is transmitted to the succeeding stage and becomes the output'L '.

As described above, the FF 1 with S and the FFs 2 to 4 with R take in data to the preceding stage by inputting the'H 'of the preceding clock φ1, and inputting the data of the preceding stage to the succeeding data of the'H' of the latter clock φ2. And the output changes.
Therefore, the'H 'data is synchronized with the'H' input of the latter clock φ2, and the FF with R → FF3 with R → F with R
F4 → FF with S1 → FF2 with R are shifted in order. Further, at this time, when the write request signal 15 is input, the S-FF 1 is set and the output becomes “H” regardless of the state immediately before. Further, the FFs 2 to 4 with R are reset, and the output becomes “L”. Then, thereafter, every time "H" of the subsequent clock φ2 enters, the "H" data sequentially shifts the FFs 2 to 4 with R and the FF 1 with S.

In this way, the address is determined by inputting the write request signal 15, and the addresses are sequentially shifted in synchronization with the post-stage clock φ2. Therefore, it suffices to write the write data in synchronization with the latter clock φ2 without worrying about the address.

[0014]

As described above, in the memory circuit of the present invention, the write request signal is used as a set signal for one of the flip-flop groups forming the shift register for address selection and as a reset signal for the other flip-flops. Respectively. Therefore, by inputting the write request signal, the flip-flops are always shifted in the correct order regardless of the immediately preceding state, and the address can be set to a fixed address. As a result, there is no need to detect the start address when rewriting data, and writing can be started without waiting time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the memory circuit of FIG.

[Explanation of symbols]

 1 Flip-flop with set 2 to 4 Flip-flop with reset 5 Shift register 6 to 9 Storage cell

Claims (2)

[Claims] 1. A read comprising an address selection shift register having first to N-th flip-flops whose outputs are respectively connected to first to N-th (N is an integer of 2 or more) address selection signal lines. In a writable memory circuit, one set signal terminal of the first to Nth flip-flops and a reset signal terminal of the remaining flip-flops of the first to Nth flip-flops are provided. A memory circuit characterized in that a supply line for a write request signal is connected. 2. The memory circuit according to claim 1, wherein one of the first to Nth flip-flops is the first flip-flop.