JP2824089B2 - Semiconductor storage element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A readable / writable semiconductor memory element, which aims at shortening the static test time and guaranteeing the long-term static property, and capable of reading and writing binary data. A main storage element, a first gate for supplying binary data on a data line to the main storage element in response to a write signal, and a content of the main storage element on the data line in response to a read signal A second gate to read and write binary data, a third gate to supply binary data on the data line to the auxiliary storage element in response to a test write signal, In response, a fourth gate for supplying the contents of the auxiliary storage element onto the data line, and for supplying the contents of the main storage element to the auxiliary storage element in response to a refresh read signal. In response to the fifth gate and the refresh write signal,
A sixth gate for supplying the contents of the auxiliary storage element to the main storage element.

The present invention relates to a readable and writable semiconductor memory device.

[Related Art] Once written, a storage element constituting a register or a RAM cannot be rewritten for a long period of time, and if the contents change carelessly, it may become important. For example, a telephone number and the like are written in an internal memory of a one-chip microcomputer used for a telephone, but once written, the contents are usually not rewritten for a long period of time. This stored content changes due to poor staticity,
If the opponent is away, you will not be able to communicate many times. In addition, if the contents of the interrupt bits and the interrupt vector of the status register among the internal registers of the CPU change due to the staticity failure, it causes runaway.

However, it is practically impossible to perform a long-term static test on all the semiconductor memory devices.

FIG. 6 shows a sequence of a static test of a readable / writable semiconductor memory device. It is assumed that this semiconductor memory device has a normal mode operating at a power supply voltage V _{CC H} and a low power consumption mode operating at a power supply voltage V _{CC L} lower than this voltage.

First, data "1" is written to all the storage elements at the power supply voltage V _{CC H} , and then, it is waited for the time T to elapse at the power supply voltage V _{CC L} in order to test whether this data can be held for a certain time. This waiting time T is usually several tens ms to several hundred ms.

After a lapse of time T, data is read from each storage element, and it is checked whether or not the content is "1", and then "0" is written to the storage element. Such processing is executed for all the storage elements.

Next, after waiting for the time T to elapse as described above, data is read from each storage element and it is checked whether or not the content is '0'.

Next, contrary to the above-described case, a test in which writing and reading operations are performed at the power supply voltage V _{CC L} and a predetermined time T elapses at the power supply voltage V _{CC H} is performed in the same manner as above.

For example, if the storage capacity of a semiconductor storage device is 1 Kbyte,
The total time for writing, reading, and checking data is about 40 ms, which is relatively short.

[Problems to be Solved by the Invention] However, for example, when T = 500 ms, the total waiting time is as long as 2 seconds. Moreover, this test does not guarantee staticity at T> 500 ms.

An object of the present invention is to provide a semiconductor memory device that can reduce the staticity test time and can guarantee long-term staticity in view of the above problems.

[Means for Solving the Problems] FIG. 1 shows the principle configuration of the present invention.

In the drawing, reference numeral 1 denotes a storage element, and 2 denotes an auxiliary storage element, which can read and write binary data.

G1 is a first gate, and supplies binary data on the data line S to the main storage element 1 in response to a write signal.

G2 is a second gate, which supplies the contents of the main storage element 1 onto the data line S in response to a read signal.

G3 is a third gate, which supplies binary data on the data line S to the auxiliary storage element 2 in response to a test write signal.

G4 is a fourth gate, and supplies the contents of the auxiliary storage element 2 to the data line S in response to the test read signal.

G5 is a fifth gate, which supplies the contents of the main storage element 1 to the auxiliary storage element 2 in response to the refresh read signal.

G6 is a sixth gate, which supplies the contents of the auxiliary storage element 2 to the main storage element 1 in response to the refresh write signal.

[Operation] (1) In the case of the normal mode In the case of the normal mode, the third gate G3 and the fourth gate
G4 is closed.

Writing of data on the data line S to the main storage element 1 is performed as follows.
This is performed by opening only the first gate G1.

This data holding is performed with the first to fourth gates closed.
This is performed by alternately opening the fifth gate and the sixth gate. However, the fifth gate is opened first. Thereby, the contents of main storage element 1 are written to auxiliary storage element 2, then the contents of auxiliary storage element are written to main storage element, and this is repeated. That is, the contents of the main storage element 1 are refreshed.

Therefore, even if the holding time of the main storage element 1 is short, if the refresh cycle is longer than this period, the contents are kept held. As a result, the staticity test only needs to test the staticity during the period, and the test time can be greatly reduced.

Reading of the contents of the main storage element 1 onto the data line S is performed by opening only the second gate G2.

(2) In the test mode In the test of the main storage element 1 alone, data is written to the main storage element 1 by opening only the first gate, and then the contents of the main storage element 1 are read by opening only the second gate G2. By checking whether or not this matches the write data.

Similarly, the test of the auxiliary storage element 2 alone is performed by the third gate G3
Only the fourth gate G4 is opened to read out the contents of the auxiliary storage element 2, and it is checked whether this matches the write data.

The write test from the main storage element 1 to the auxiliary storage element 2
This is performed as follows. That is, data different from each other is written in the main storage element 1 and the auxiliary storage element 2,
Only the gate G5 is opened to write the contents of the main storage element 1 to the auxiliary storage element 2. Next, only the fourth gate G4 is opened to read the contents of the auxiliary storage element 2 and check whether this matches the data written in the main storage element 1, in other words, whether the contents of the auxiliary storage element 2 have been inverted. Check if.

The write test from the auxiliary storage element 2 to the main storage element 1
This is performed as follows. That is, data different from each other is written in the auxiliary storage element 2 and the main storage element 1,
Only the gate G6 is opened to write the contents of the auxiliary storage element 2 to the main storage element 1. Next, only the second gate G2 is opened to read the contents of the main storage element 1 and check whether this matches the data written in the auxiliary storage element 2, in other words, whether the contents of the main storage element 1 have been inverted. Check if.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

 FIG. 2 shows a configuration of the semiconductor element storage element.

This semiconductor memory element includes a main memory circuit 10 and an auxiliary memory circuit.
20 is a pair, and data is read and written between each other.

In the main memory circuit 10, the input side of the main flip-flop 11
Is connected to a precharge line S via a three-state inverter 12 to be held in the write signal W, the output side of the main flip-flop 11, the input side of the buffer flip-flop 14 via the three-state inverter 13 to be held in the clock phi ₁ The output side of the buffer flip-flop 14 is connected to the NM through the NOR gate 15 opened by the read signal R.
Connected to the gate of OSFET16. The NMOSFET16 is connected between a precharge line S and ground, pre-charge line S is connected to the power supply line V _DD via a PMOSFET17 to be opened in a clock phi _1. The precharge line S is one wiring constituting a data bus.

The auxiliary storage circuit 20 has an output side of the auxiliary flip-flop 21 connected to an input side of the main flip-flop 11 via a three-state inverter 22 opened by the refresh write signal RW. The output side of step 11 is the refresh read signal
They are connected via a three-state inverter 23 whose ratio is equal to 2 by RR. Also on the input side of the auxiliary flip-flop 21, the output side of the buffer flip-flop 24, the three-state inverter 25 to be held in the test write signal TW ₂
The precharge line S is connected to the input side of the buffer flip-flop 24 via the test write signal TW ₁
And is connected via a three-state inverter 26 which is opened at the same time. Further, the output side of the auxiliary flip-flop 21 is connected to the gate of the NMOSFET 28 via the NOR gate 27 opened by the test read signal TR, and the NMOSFET 28 is connected between the precharge line S and the ground.

Each of the flip-flops 11, 14, 21 and 24 is configured by connecting two inverters in a loop.

Clock phi ₁ and clock phi ₂ is FIG. 3 (A),
A two-phase clock having the same frequency as shown in FIG.
Clock phi ₁ is used as the charging of the pre-charge line S, the clock phi ₂ is used for the discharge of the pre-charge line S. The above-mentioned gate control signals are shown in FIGS. 3 to 5 relating to the description of the operation.
₁ and φ ₂ .

Next, the operation of the present embodiment configured as described above will be described.

(1) Operation in Normal Mode FIG. 3 shows a timing chart in the normal mode. In this mode, the test write signals TW ₁ and TW ₂ and the test read signal TR are always at H level, and the three-state inverters 26 and 25 and the NOR gate 27 remain closed. Hereinafter, description will be made in the order of the numbers in the figure.

Writing of the data D to the main flip-flop 11 and holding of its contents are performed as follows.

Precharge line S is charged by the clock phi _1, at the same time when the data D to the pre-charge line S at the next clock phi ₂ is supplied, and the three-state inverter 12 is opened by the write signal W, have any of the data D Written in the main flip-flop 11. At the time of this writing, the refresh write signal RW remains at the H level, and the three-state inverter 22 is closed.

Next, the three-state inverter 23 is opened by the refresh read signal RR, the contents of the main flip-flop 11 are written to the auxiliary flip-flop 21, and then the three-state inverter 22 is opened by the refresh write signal RW, and the auxiliary flip-flop is opened. The contents of the flip-flop 21 are written into the main flip-flop 11.

Reading of such data between the main flip-flop 11 and the auxiliary flip-flop 21, that is, refreshing of the content of the main flip-flop 11 is repeated thereafter.

Accordingly, even if short retention time of the main flip-flop 11, which continues to hold its contents as long as the clock phi ₁ of the cycle over. As a result, the static test is
May be tested for static properties between the period of the clock phi _1, it can significantly reduce the test time.

Incidentally, the three-state inverter 13 is periodically opened by the clock phi _1, thereby contents of the main flip-flop 11 is written into the buffer flip-flop 14.

Reading of data D from main flip-flop 11 is the same as in the prior art, and is performed as follows.

After the clock phi ₁ is precharge line S is charged, and the NOR gate 15 is opened in the read signal R, the contents of the buffer flip-flop 14 via the NOR gate 15 NMOSFET
Supplied to 6 gates. As a result, the charge on the precharge line S is not discharged when the content of the main flip-flop 11, that is, the content (output) of the buffer flip-flop 14 is "1", and passes through the NMOSFET 16 when it is 0. Discharged to ground.

(2) From the auxiliary flip-flop 21 to the main flip-flop
FIG. 4 shows the operation of test mode in which data is written to main flip-flop 11. Data D is written to main flip-flop 11 and its contents are read out. 5 is a timing chart in the case of reading, then writing the contents of the auxiliary flip-flop 21 to the main flip-flop 11, and then reading the contents.

In this test mode, the refresh mode signal RR is always at the H level and the three-state inverter 23 is kept closed as shown in FIG. That is, the content of the auxiliary flip-flop 21 is not affected by the content of the main flip-flop 11.

The writing of data D to the main flip-flop 11 is the same as shown in FIG. 3, respectively, and the reading of the content of the main flip-flop 11 is the same as that shown in FIG. The description is omitted. After this read, it is checked whether the read data from the main flip-flop 11 is equal to the write data to the main flip-flop 11.

Writing and reading of data D to and from the auxiliary flip-flop 21 are performed as follows.

Clock phi ₁ in the precharge line S is charged, at the same time when the data D to the pre-charge line S at the next clock phi ₂ is supplied, the pre-charge line the three-state inverter 26 is opened in the test write signal TW ₁ data on S is written into the buffer flip-flop 24, then the three-state inverter 25 in the test write signal TW ₂ is opened the contents of the buffer flip-flop 24 is written into the auxiliary flip-flop 21.

The contents of auxiliary flip-flop 21 are read out as follows.

'At the same time the write operation of the above, is charged precharge line S by the clock phi _1, NOR gate 27 then the test read signal TR is opened the contents of the auxiliary flip-flop 21 NMOS via the NOR gate 27
The data is supplied to the gate of the FET 28 and read on the precharge line S.

After this read, it is checked whether the read data from the auxiliary flip-flop 21 is equal to the write data to the auxiliary flip-flop 21.

Main flip-flop with contents of auxiliary flip-flop 21
Writing to and reading from 11 are performed as follows.

The three-state inverter 22 is opened by the refresh write signal RW, and the contents of the auxiliary flip-flop 21 are written to the main flip-flop 11.

The contents of the main flip-flop 11, clock phi ₁ in the three-state inverter 13 is written to the buffer flipflop 14 is opened is charged precharge line S at the same time, then the NOR gate 15 is opened in the read signal R Thus, the contents of buffer flip-flop 14 are read onto precharge line S in the same manner as described above.

After this read, it is checked whether the read data from the main flip-flop 11 is equal to the write data to the auxiliary flip-flop 21, that is, whether the contents of the main flip-flop 11 are inverted.

(3) Main flip-flop 11 to auxiliary flip-flop
FIG. 5 shows the operation of test mode in which data is written to main flip-flop 11. Data D is written to main flip-flop 11 and its contents are read out. Next, data D is written to auxiliary flip-flop 21 and its contents are read. 9 is a timing chart in the case of reading, then writing the contents of the main flip-flop 11 to the auxiliary flip-flop 21 and then reading the contents.

In this test mode, the refresh write signal RW is always at the H level, and the three-state inverter 22 is kept closed, as shown in FIG. That is, the contents of the main flip-flop 11 are not affected by the contents of the auxiliary flip-flop 21.

Are the same as those in FIG. 4, and the description thereof will be omitted. However, the write data used is the reverse of the case of FIG.

Auxiliary flip-flop with contents of main flip-flop 11
Writing to and reading from 21 is performed as follows.

The three-state inverter 23 is opened by the refresh read signal RR, and the contents of the main flip-flop 11 are written to the auxiliary flip-flop 21.

'At the same time, the precharge line S is charged. Next, the NOR gate 27 is opened by the test read signal TR, and the contents of the auxiliary flip-flop 21 are read onto the precharge line S in the same manner as described above.

After this read, it is checked whether the read data from the auxiliary flip-flop 21 is equal to the write data to the main flip-flop 11, that is, whether the content of the auxiliary flip-flop 21 is inverted.

As described above, the staticity test of the semiconductor memory device is performed in a short time without requiring the waiting time T as shown in FIG. 6, and the long-term staticity is guaranteed.

Although the storage element of this embodiment has a more complicated configuration than the conventional storage element, for example, if this embodiment is applied to an internal register of a CPU, the number of storage elements is relatively small, so that the CPU
Overall, the complexity of the configuration is not a problem, and the benefits of increased reliability are much greater. In addition, this embodiment
Even when applied to a RAM, the RAM itself is relatively inexpensive when used in a device that requires high reliability, so even if the price is doubled, the overall advantage is greater.

In this embodiment, the three-state inverter 13, the buffer flip-flop 14, the NOR gate 15, and the NMOSFET 16
And a second gate, and the three-state inverter 26
, The buffer flip-flop 24 and the three-state inverter 25 constitute a third gate, but exclude the three-state inverter 13 and the buffer flip-flop 14 and / or exclude the buffer flip-flop 24 and the three-state inverter 25 However, no particular problem arises.

[Effects of the Invention] As described above, in the semiconductor memory device according to the present invention, the refresh operation is normally performed between the main memory device and the auxiliary memory device, and the main memory device alone, the auxiliary memory device alone, and both are used during the test. Since it is possible to read and write data between memory cells, sufficient staticity tests can be performed, and the static test time can be shortened. In addition, long-term staticity can be guaranteed. This greatly contributes to improving the reliability of the semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of a semiconductor memory device according to the present invention. 2 to 5 relate to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device, FIG. 3 is a timing chart in a normal mode, and FIG. 4 is an auxiliary flip-flop. FIG. 5 is a timing chart of a test mode for writing data from the main flip-flop 11 to the main flip-flop 11, and FIG. 5 is a timing chart of a test mode for writing data from the main flip-flop 11 to the auxiliary flip-flop 21. FIG. 6 is an explanatory view of a static test of a semiconductor memory device according to a conventional example. In the figure, 10 is a main memory circuit 11 is a main flip-flop 12, 13, 22, 23, inverters 25 and 26 are three-state inverters 14, 24 are buffer flip-flops 16, 28 are NMOSFETs 17, PMOSFETs 20 are auxiliary memory circuits 21 Is a three-state inverter

Claims (1)

(57) [Claims] 1. A main storage element (1) capable of reading and writing binary data, a first gate (G1) for supplying binary data on a data line to the main storage element in response to a write signal, A second gate (G2) for supplying the contents of the main storage element onto the data line in response to a signal, an auxiliary storage element (2) capable of reading and writing binary data, and a test write signal, A third gate (G3) for supplying binary data on the data line to the auxiliary storage element, and a fourth gate (4) for supplying the content of the auxiliary storage element on the data line in response to a test read signal A fifth gate (G5) that supplies the contents of the main storage element to the auxiliary storage element in response to a refresh read signal; and stores the contents of the auxiliary storage element in the main storage in response to a refresh write signal. A sixth gate (G6) for supplying the element; The semiconductor memory device characterized by having