JP2001167082A - Synchronous integration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous integration circuit facilitated in time shortening and control without necessity to clear contents in a memory before starting synchronous integration. SOLUTION: This circuit is provided with an adder 8 for adding an external signal entry and a feedback signal inputted to a pair of input terminals and a memory 9 for inputting the added output of this adder 8 to a data input terminal writing the output, reading out this output and feeding it back to the adder 8. The write and read addresses of the memory 9 are available from an address counter 10. Besides, a 2:1 selector 13 is provided on the feedback path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous integration circuit, and more particularly to a correlation value output integration circuit of a digital matched filter.

[0002]

2. Description of the Related Art One of basic circuits for performing arithmetic processing of digital data is an integrating circuit. A conventional example of such an integrating circuit is disclosed in, for example, "Spread code synchronization determination circuit for spread spectrum communication" in Japanese Patent Application Laid-Open No. 2-14634.
83777 and the like.

[0003]

However, in such a conventional integration circuit, the supplementary timing circuit and the integration number control circuit are independent, and the integration of the integrator is controlled by the number of integrations. The timing of the beginning and end is unknown. Further, in order to start the integration operation, a memory called a line memory is initialized to "0" in advance, and then data reading and writing are performed. Furthermore, when transferring the integrated data to the low-speed memory, stop the integrating operation,
The address control was switched to operate at low speed. Therefore,
To continue the integration from that point, the memory had to be initialized, and a blank time occurred to accumulate successive events, which was only valid for certain events. Furthermore, even if an overflow occurs in the integration result, the result is not rescued, and thus the result may include an error.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronous integrating circuit which overcomes or alleviates the above-mentioned problems of the prior art. That is, it is not necessary to clear (initialize) the contents of the memory before starting the synchronous integration, and it is possible to shorten the time and to provide a synchronous integration circuit which can eliminate an error caused by overflow. is there.

[0005]

According to the present invention, there is provided a synchronous integrating circuit for adding an external signal input to a pair of input terminals and a feedback signal, and an output of the adder to a data input terminal. A memory for inputting, writing, and reading a memory output from a data output terminal as a feedback signal of an adder; an address counter for receiving a first clock and generating a write address and a read address of the memory;
And a clock distribution circuit that receives the first clock and generates a second clock and a third clock for writing and reading the memory, respectively.

According to a preferred embodiment of the synchronous integrating circuit,
A 2: 1 selector for selecting a memory output read from the memory or "0" is provided in a feedback path between the memory and the adder. Further, a count counter for receiving the carry bit of the address counter is provided, and switching of the 2: 1 selector is controlled by the output of the count counter. The number counter receives a number setting signal from the outside.

Further, according to a preferred embodiment of the synchronous integrating circuit, a flip-flop which receives an output of the address counter and operates by a third clock is provided to obtain the above-mentioned write address of the memory. Also, the third clock is delayed by a predetermined time T1 from the first clock, and the second clock is the same cycle delayed by a predetermined time T2 from the third clock.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a synchronous integration circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a synchronous integration circuit according to the present invention. This specific synchronous integrating circuit includes an adder 8, a memory 9, an address counter 10, a flip-flop (F / F) 12, and 2:
It comprises a 1 (2 input 1 output) selector 13 and a clock distribution circuit 14.

An external signal input is input to one input terminal 1 of the adder 8, and a 2: 1 selector 1 is input to the other input terminal.
3 is input. The addition output of the adder 8 is input to a data input terminal of the memory 9. Clock terminal 3
1 is input to the address counter 10 and the clock distribution circuit 14.
The clock distribution circuit 14 receives the second clock signal (CLK2) and the third clock signal (CLK
3) is generated. The output of the address counter 10 is directly input to the read address terminal of the memory 9 and F
/ F12 is input to the write address terminal of the memory 9.

The clock terminal 5 of the F / F 12 has
The third clock signal (CLK) from the clock distribution circuit 14
3) is input. Further, the second clock signal (CLK2) and the third clock signal (CLK3) from the clock distribution circuit 14 are input to the write clock terminal and the read clock terminal of the memory 9, respectively. A memory output is read from the data output terminal 2 of the memory 9 and input to one input terminal of the 2: 1 selector 13,
A fixed value "0" is input to the other input terminal, thereby completing the synchronous integration circuit of the present invention.

As described above, the memory 9 has two input / output means, and executes writing and reading according to the output of the F / F 12 and the address counter 10, respectively. The clock distribution circuit 14 generates a third clock (CLK3) having a certain delay time T1 and a third clock (CLK3) with respect to the first clock (CLK1) for operating the address counter 10.
It is configured to output a second clock (CLK2) having a certain delay time T2 from the clock (CLK3).

Next, the operation of the synchronous integration circuit of the present invention shown in FIG. 1 will be described. The address counter 10 sequentially counts (counts) by the first clock (CLK1), and the third clock (C) input to the read clock terminal 4R at the address generated by the address counter 10
LK3), the data written (stored) in the memory 9 is read out from the data (memory) output terminal 2 as a memory output. The memory output data read in this manner is input to the other input terminal of the adder 8 via the 2: 1 selector 13. This adder 8
The memory output data selected by the 2: 1 selector 13 and the external input signal input to the input terminal 1 are added and input to the data input terminal of the memory 9.

Next, the memory 9 receives the addition output from the adder 8 at a data input terminal, and outputs the third clock (C
LK3) at the write address based on the output of the F / F 12 and the second clock (CLK2) input to the write clock terminal 4W of the memory 9 at the write address.
Is written to. As a result, the memory output data of the sequential read address and the external signal input data input to the input terminal 1 are sequentially added and written to the write address of the memory 9.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the synchronous integration circuit according to the present invention. still,
The same reference numerals are used for the components corresponding to the components in FIG. 1 for convenience. The synchronous addition circuit shown in FIG. 2 includes an adder 8, a memory 9, an address counter 10, a number counter 11, an F / F 12, a 2: 1 selector 13, and a clock distribution circuit 14. In other words, FIG.
The number of times counter 11 is added as compared with the synchronous integrating circuit of the first embodiment.

The adder 8 has an external signal input to one input terminal 1 and a 2: 1 input to the other input terminal.
(2 inputs, 1 output) Memory 9 as output from selector 13
And outputs the result to the data input terminal of the memory 9. The memory 9 is, for example, a FIFO (first-in first-out) memory in which the number of bits per address and the address length are determined in advance in accordance with the use state, and the write operation and the read operation are performed independently.
The address counter 10 can scan all addresses of the memory 10 and has a number of stages determined by the number of addresses of the memory 9. The address counter 10 operates by a first clock (CLK1) input to the clock terminal 5. Further, the clock distribution circuit 14 generates the second clock (CLK2) and the third clock (CLK3) which are distributed with a time difference from the first clock (CLK1), as in the case described above.

The number counter 11 is an address counter 1
A carry bit (CR) of 0 is input, and this is counted. When this count value is equal to the set value of the number of synchronous integrations set and input from the terminal 7, the output signal is input to the selection terminal S of the 2: 1 selector 13, and the input terminal is changed from the B terminal in the normal state to the A terminal. Switching to the terminal, the selected signal is output from the output terminal Y. Since the memory output data of the memory 9 is input to the B terminal and the fixed value “0” is input to all bits to the A terminal, the contents of the memory 9 are obtained from the memory output terminal 2 as a memory output. Further, the address counter 10 and the number counter 11 are reset by a reset signal input from a reset (RESET) terminal 6.

The F / F 12 latches the address generated by the address counter 10, that is, the address from which the memory 9 is read out, at the third clock (CLK3), and inputs the latched address to the write address terminal of the memory 9.

Next, the operation of the synchronous integration circuit of FIG.
This will be described with reference to the timing chart of FIG.
FIG. 3 shows the read address and write address of the memory 9, the first to third clocks (CLK1 to CLK3), and the timing of the output signal of each circuit block. That is, FIG. 3A shows the first clock signal (CLK1),
(B) is the read address from the address counter 10, (c) is the third clock signal (CLK3), and (d) to (g) are the signal MD, signal MD ', external signal D and signal D', (h), respectively. ) Indicates the write address of the memory 9 and (i) indicates the second clock signal (CLK2). Here, it is assumed that the addresses of the memory 9 are set from 1 to 1024.

First, the first clock (C) shown in FIG.
LK1), the address counter 10 operates, and FIG.
The read address of (b) is generated. This read address is temporarily set to the address “001” and is given to the memory 9. Further, a third clock (CLK3) shown in FIG.
Is given as a read clock. This read clock (CLK3) has a relationship of rising with a delay of T1 time from the change point of the read address. A memory output signal (hereinafter, "001") from the data output terminal 2 of the memory 9
The memory output data at the address is referred to as “MD001”. This memory output signal “MD001” is input to the B input terminal of the 2: 1 selector 13 as described above.
The selection signal input of the control (selection input) terminal S is set from the number counter 11 so as to select the B input. Accordingly, as shown in FIG. 3E, the signal “MD′001” is output from the output terminal Y to the other input terminal of the adder 8.

On the other hand, as shown in FIG. 3 (f), an external input signal "D001" is input to the input terminal 1 of the adder 8 in synchronization with the third clock (CLK3). This is because the adder 8 performs an addition operation on the signal MD ′ from the 2: 1 selection circuit 13 and then outputs the data “D′ 001” as shown in FIG.
Becomes a write data input signal to the memory 9. Writing of the write data input signal "D'001" to the memory 9 is performed by the address counter 1 as shown in FIG.
0 generated by the third clock CLK
At the rise of 3), the data is latched by the F / F 12 and given to the memory 9. Here, the write data “D′ 001” and the write address are synchronized with the third clock (CLK3), so that the “001” -th data is prepared to be stored at the write address “001”. Next, as shown in FIG. 3 (i), a second clock (CLK2) delayed by the time T2 from the rising of the third clock (CLK3) and having the same cycle as the third clock is applied, and the rising of the clock (CLK2) is performed. At the timing, the data "D'0
01 ”is written in the memory 9.

With this second clock (CLK2),
When data "D'001" is written in
The address on the read side of (b) has already been advanced by one, and is "00".
Note that the read address (see FIG. 3B) does not match or match the write address (see FIG. 3H).

When the above operation is continued and the address counter 10 counts from "001" to the final address value of "1024", the address counter 10 outputs a carry bit and advances the count value of the number counter 11 by one. . The count counter 11 sends a control signal to the control terminal S of the 2: 1 selector 13 when the count value becomes equal to the set value of the synchronous integration count of the count setting terminal 7. So 2:
The 1 selector 13 selects the input of the A terminal (that is, “0”), all the bits “0” are input to the adder 8 from the output terminal Y, and the next new data is written. Memory 9
Is output from the memory output terminal 2 to the outside, and the content of the counter 11 is set to "0".

When a new data string is written into the memory 9, the address counter 10 issues a carry and advances the number counter 11 from "0" to "1". When the content of the frequency counter 11 is no longer "0", the frequency counter 1
1 switches the input of the 2: 1 selector 13 to the B terminal and stops the output of the memory 9 to the outside.

Next, with reference to the timing chart of FIG. 4, the operation when the number counter 11 of FIG. 2 is "000" will be described. In FIG. 4, (a) shows the first clock (CLK
1) and (b) are read addresses from the address counter 10, (c) is a third clock (CLK3), (d) is a memory output signal MD, and (e) is an output signal of the 2: 1 selector 13. . FIG. 4F shows the input terminal 1 of the adder 8.
(G) is the output signal D ′ of the adder 8,
(H) is the write address of the memory 9, (j) is the counter value of the number counter 11, and (i) is the second clock (CLK2), which is the same as in FIG.

When a reset signal is input to the RESET terminal 6 and the number counter 11 is initialized to "000", the 2: 1 selector 13 selects the input of the A terminal. Therefore, the adder 8 outputs the Y signal of the 2: 1 selector 13 which is “0”.
All terminal outputs “0” and an external input signal of the input terminal 1, for example, “D001” are added and calculated. This allows
External signal input "D"
"001" is input to the memory 9 as it is. As a result, there is an advantage that the time for initializing the contents of the memory 9 to “0” can be saved.

When the external signal input "D001" is appropriately converted to a two's complement format and this circuit is used,
Signals near “0” are averaged by positive and negative, and the protruding numerical value such as the correlation value is farther from the vicinity of “0”. Therefore, if only a positive number is indicated, the memory easily overflows due to the noise level. According to this method, the number of bits of the memory can be reduced.

The preferred embodiment of the synchronous integrating circuit according to the present invention has been described in detail. However, it should be understood by those skilled in the art that the present invention should not be limited to only the specific embodiments, and various modifications can be made without departing from the gist of the present invention.

[0029]

As is apparent from the above description, according to the synchronous integration circuit of the present invention, when the output of the adder is written to the memory as it is, the polarity is inverted to the minimum value when the output exceeds the maximum value indicated by the memory. Can be prevented. The reason is that when two sets of data are added (including minus), the output data of the adder is generated when an overflow / underflow occurs.
This is because a data error can be prevented by fixing and outputting the maximum value indicated by the memory or the minimum value indicated by the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a synchronous integration circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the synchronous integration circuit according to the present invention.

FIG. 3 is a timing chart showing the operation timing around the memory of the synchronous integration circuit according to the present invention.

FIG. 4 is a timing chart showing the operation around the memory when the output of the number counter of the synchronous integration circuit according to the present invention is "000";

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External signal input terminal 2 Memory output terminal 6 Reset input terminal 7 Synchronous integration number setting input terminal 8 Adder 9 Memory 10 Address counter 11 Number counter 12 Flip-flop (F / F) 13 2: 1 selector 14 Clock distribution circuit

Claims (6)

[Claims] An adder for adding an external signal input and a feedback signal respectively input to a pair of input terminals, and an added output of the adder is input to a data input terminal, written, and read from the data output terminal. A memory that uses a memory output as the feedback signal to the adder; an address counter that receives a first clock and generates a write address and a read address of the memory; and that receives and receives the first clock and writes and reads the memory. And a clock distribution circuit that generates a second clock and a third clock. 2. The memory output read from the memory or "0" on a feedback path between the memory and the adder.
2. The synchronous integration circuit according to claim 1, further comprising a 2: 1 selector for selecting a signal. 3. The synchronous integration circuit according to claim 2, further comprising a number counter for receiving a carry bit of said address counter, wherein switching of said 2: 1 selector is controlled by an output of said number counter. 4. The synchronous integrating circuit according to claim 3, wherein said number counter receives a number setting signal from outside. 5. The memory according to claim 1, wherein a flip-flop which receives an output of said address counter and operates with said third clock is provided to obtain said write address of said memory. Synchronous integration circuit. 6. The third clock is delayed from the first clock by a predetermined time T1, and the second clock is delayed by the third clock.
6. The synchronous integrating circuit according to claim 1, wherein the clocks have the same cycle and are delayed by a predetermined time T2 from the clock.