JPH11338854A - Synchronous integration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous integration circuit with which it is not necessary to clear the contents of a memory before the start of synchronous integration, and time reduction and control are facilitated. SOLUTION: This circuit is provided with an adder 8 for adding an external signal input and a feedback signal and a memory 9 for inputting the added output to a data input, writing it, reading it and feeding it back to the adder 8. The write and read addresses of the memory 9 are provided from an address counter 10. On a feedback path, a 2:1 selecting part 13 is provided for inputting and selecting the memory output of the memory 9 and '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous integrating circuit, and more particularly to a correlation output integrating circuit of a digital matched filter.

[0002]

2. Description of the Related Art One of basic circuits for performing arithmetic processing of digital data is an integrating circuit. An example of a conventional integrating circuit is
For example, JP-A-2-14634 and JP-A-2-8377
No. 7 discloses this.

[0003]

However, in the conventional integration circuit, the supplementary timing generation circuit and the integration number control circuit are independent, and the integration of the integrator is controlled by the number of integrations. And the timing of the end was unknown.

In order to start an operation, a memory called a line memory is first initialized to "0", and then data is read and written. Further, when transferring the integrated data to the low-speed memory, the integrating operation is stopped and the address control is switched to perform the low-speed operation. That is, in order to continue the integration from there, the memory had to be initialized, and a blank time occurred to integrate continuous events, which was effective only for specific events. Further, even if an overflow occurs in the integration result, the result is not rescued, so that the result may include an error.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronous integrating circuit which does not require clearing of memory contents before starting synchronous integrating, can reduce time, and can prevent errors caused by overflow. It is in.

[0006]

In order to solve the above-mentioned problems, a facsimile apparatus according to the present invention employs the following characteristic configuration.

(1) An adder for adding an external signal input and a feedback signal, and a memory for inputting an added output of the adder to a data input terminal and returning a memory output read from the data output terminal to the adder. In the synchronous integration circuit including
A synchronous integration circuit comprising: an address counter that receives a first clock and generates a write and read address of the memory; and a clock distribution circuit that receives the first clock and generates a write and read clock of the memory.

(2) A data output terminal of the memory and a 2: 1 selector for selecting a memory output read from the memory or "0" on a feedback path of the adder. (1)
Synchronous integration circuit.

(3) The synchronous integration circuit according to (2), further comprising a number counter for receiving the carry bit of the address counter, and controlling the 2: 1 selecting section based on the output of the number counter.

(4) The synchronous integration circuit according to (3), wherein the number counter receives a number setting signal from outside.

(5) The write address of the memory is obtained via a flip-flop that receives an output of the address counter, which is the read address (1).
(2) The synchronous integration circuit according to (3) or (4).

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a synchronous integration circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

First, a description will be given with reference to FIG. FIG.
1 shows a block diagram of a preferred embodiment of a synchronous integration circuit of the present invention. This synchronous integrating circuit includes an adder 8 having one input connected to an input terminal 1 to which an external signal input is input, an output of the adder 8 being input to a data input, a second clock CLK2 and a third clock. CLK3 is the write CLK
A memory 9 is input to the terminal 4W and the read CLK terminal 4R, and outputs a memory output from the data output terminal 2.

A two-input one-output selection circuit (hereinafter referred to as a 2: 1 selection unit) for selecting the memory output and the "0" input.
The output of 13 is input to the other input of the adder 8. Further, the first clock CLK1 is input to a terminal 3, and this terminal 3 is connected to the clock distribution circuit 14 and the address counter 10. The clock distribution circuit 14 controls the first clock C
A second clock CLK2 and a third clock CLK3 are generated based on LK1. The output of the address counter 10 is
The read address of the memory 9 and the flip-flop (hereinafter referred to as F / F) 12 are input.

The third clock CLK 3 output from the clock distribution circuit 14 is input from the terminal 5 to the F / F 12, and the output of the F / F 12 is input to a write address of the memory 9.

The operation of the synchronous integration circuit shown in FIG. 1 will be described.
The address counter 10 sequentially counts according to the first clock CLK1, and the data written in the memory 9 is read by the address generated by the address counter 10 and the third clock CLK3 input to the read clock terminal 4R. The memory output data of this memory 9 is 2:
The signal is input to the adder 8 via the 1 selector 13. The adder 8 adds the memory output data of the memory 9 via the 2: 1 selector 13 and the external signal input input to the input terminal 1.

Next, the memory 9 receives the addition output data of the adder 8 at the data input terminal, and outputs the address latched by the third clock CLK3 and the write CLK terminal 4W of the memory 9.
Is written into the memory 9 by the second clock input to the memory 9. As a result, the memory output data of the sequential read address and the input data input to the external signal input terminal 1 are sequentially added and written to the write address of the memory 9.

Next, another embodiment of the synchronous integration circuit of the present invention will be described with reference to FIG. Note that the same reference numerals are used for the circuit terminals as in the synchronous integration circuit of FIG.

The adder 8 has an external signal input 1 and a 2-input 1
The outputs from the output selection unit (2: 1 selection unit) 13 are added and output. The memory 9 that receives the output of the adder 8 as a data input is such that the number of bits per address and the total address length are determined in advance in accordance with the state of use, and the write operation and the read operation are performed independently.

The address counter 10 is capable of operating all addresses of the memory 9.
The number of stages is determined by the number of addresses of the memory 9. The address counter 10 operates by the first clock CLK1 input to the clock terminal 5. Further, the clock distribution circuit 14 receives the first clock CLK1 and generates a second clock CLK2 and a third clock CLK3 that distribute the clock with a time difference from the first clock CLK1 input in synchronization with the data.

The carry bit of the address counter 10 is inputted and counted. If the counted value is equal to the set number of the synchronous integration times 7 set and inputted from the terminal 7, the contents of the memory 9 are transferred from the memory output terminal 2 to It has a number counter 11 for outputting. An address counter 1 is reset by a reset signal input from a reset (RESET) terminal 6.
0 and the counter 11 are reset.

The 2: 1 selector 13 is connected to the memory output terminal 2 of the memory 9 and selects a B terminal to which the memory output data of the memory 9 is input, and an A terminal to which "0" is input. And a Y terminal for outputting input data of the A or B terminal. When the number counter 11 is "0", the terminal A is selected and all bits "0" are output from the Y terminal. 2: 1
The Y output of the selector 13 is input to one input terminal of the adder 8 as described above.

The F / F 12 stores the address (read address of the memory 9) generated by the address counter 10 as a third address.
The signal is latched by the clock CLK3 and input to the write address of the memory 9.

Next, the operation of the synchronous integration circuit of FIG.
This will be described in detail with reference to FIG.
FIG. 3 shows the read address of the memory 9, the write address, the clocks CLK1 to CLK3, and the timing of the output signal of each circuit unit. Here, if the address is 1
It is assumed that the number is set to 1024.

First, the first clock CL shown in FIG.
At K1, the counter 10 operates from the address, and FIG.
The read address of (b) is generated. This read address is temporarily set to the address “001” and is given to the memory 9. Further, a third clock CLK3 is provided as a read clock (see FIG. 3C). The read clock CL is delayed by T1 time from the read address change point.
K3 rises (see FIG. 3C). A memory output signal from the data output terminal 2 of the memory 9 (hereinafter, referred to as a memory output signal)
The output data at address "001" is referred to as "MD001."
Is output (see FIG. 3D).

The output signal "MD001" is input to the B input of the 2: 1 selection unit 13. The selection signal input S to the 2: 1 selection unit 13 is a number counter for selecting the B input. 11 is set. Therefore, “MD′001” is output from the Y output of the 2: 1 selector 13,
The signal is input to one input terminal of the adder 8 (see FIG. 3E).

On the other hand, the input signal “D” of the external signal input terminal 1
001 ”(see FIG. 3 (f)) is input in synchronization with the third clock CLK3, subjected to an addition operation in the adder 8, and then written into the memory 9 as data“ D′ 001 ”and becomes a data input signal (FIG. 3). (G)).

The write data input signal “D ′” to the memory 9
001 "is written in the third clock C using the write address generated by the address counter 10 (see FIG. 3H).
At the rise of LK3, it is latched by the F / F12 and applied to the memory 9. Here, since the write data “D′ 001” and the write address are synchronized with the third clock CLK3, the “001” -th data is the write address “00”.
1 ". Next, the third clock C
A second clock CLK2 (see FIG. 3 (i)) having the same cycle as that of LK3 and delayed by time T2 is applied, and data "D'001" is written into the memory 9 at the rising edge of the clock.

When the data "D'001" is being written into the memory 9 by the second clock CLK2, the address on the read side (see FIG. 3B) has already advanced by one to "00".
2 ", and there is no conflict between the read address (b) and the write address (h).

When the address counter 10 has counted from "001" to "1024", it issues a carry bit and advances the contents of the number counter 11 by one. Number counter 1
When the content (count value) is equal to the number setting of the number setting terminal 7, 1 sends the control signal S to the 2: 1 selection unit 13 to select the A input. Therefore, all 0s are input to the adder 8 from the Y output of the 2: 1 selector 13, and the writing of the next new data is started. The added data is output from the data output terminal 2 of the memory 9 to the outside, and the content of the number counter 11 is set to “0”.

When a new first data string is written into the memory 9, the address counter 10 issues a carry and advances the number counter 11 from "0" to "1". When the content of the frequency counter 11 is no longer "0", the frequency counter 11
Sets the input of the 2: 1 selector 13 to the B input and stops the output of the memory 9 to the outside.

Next, referring to the time chart of FIG.
The operation when the number-of-times counter 11 is “000” will be described. When a reset signal is input to the RESET terminal 6 and the number counter 11 is initialized to “000”, 2:
The 1 selector 13 selects the A input. Therefore, the adder 8
Performs an addition operation of all “0”, which is the Y output of the 2: 1 selection unit 13 that is “0”, and an external input signal, for example, “D001”. Thus, the external signal input “D001” is input to the memory 9 as it is without taking in undefined or unnecessary data. As a result, there is an advantage that the time for initializing the contents of the memory 9 to “0” can be saved.

When the external signal input "D001" is appropriately converted to a two's complement format and this circuit is used, "0" is obtained.
The signals in the vicinity are averaged by +-, and the protruding numerical value such as the correlation value is farther from the vicinity of "0". Therefore, if only positive numbers are used, the memory easily overflows due to the noise level. According to this, the number of bits of the memory can be reduced.

Although the preferred embodiment of the synchronous integration circuit of the present invention has been described in detail above, the present invention should not be limited to such a fixed embodiment, but various modifications and changes are possible. It can be easily understood by traders.

[0035]

As will be understood from the above description, according to the synchronous integration circuit of the present invention, the following various remarkable effects can be obtained.

First, since a synchronous circuit is used, the timing control of address management, reading and writing is automatically performed. When synchronous integration of fixed-length data is performed, if there is a start signal, the subsequent data No external control is required for the input and output of.

Second, the contents of the memory read by the memory circuit are fed back to the input, and the first one cycle is "0".
Is returned to eliminate unnecessary elements, so that it is not necessary to reset the memory even when recording new data.

Thirdly, a result of adding the input data and the data read from the memory includes a prevention circuit so that overflow does not occur, and there is no error in the addition result.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of a synchronous integration circuit of the present invention.

FIG. 2 is a block diagram of another embodiment of the synchronous integration circuit of the present invention.

FIG. 3 is a timing chart illustrating an operation of the synchronous integration circuit of FIG. 2 in a first case.

FIG. 4 is a timing chart illustrating an operation of the synchronous integration circuit of FIG. 2 in a second case.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External signal input terminal 2 Data output terminal 8 Adder 9 Memory 10 Address counter 11 Number counter 12 Flip-flop (F / F) 13 2: 1 selection part 14 Clock distribution circuit CLK1 First clock CLK2 Second clock (write clock) CLK3 Third clock (read clock)

Claims (5)

[Claims] An adder for adding an external signal input and a feedback signal, and an added output of the adder input to a data input terminal;
A synchronous integration circuit including a memory that feeds back a memory output read from a data output terminal to the adder; an address counter that receives a first clock and generates a write and read address of the memory; And a clock distribution circuit for generating a write and read clock for the memory. 2. A data output terminal of said memory and a 2: 1 selector for selecting a memory output read from said memory or "0" on a feedback path of said adder. 2. The synchronous integration circuit according to 1. 3. The synchronous integration circuit according to claim 2, further comprising a number counter for receiving a carry bit of said address counter, and controlling said 2: 1 selecting section based on an output of said number counter. 4. The synchronous integrating circuit according to claim 3, wherein said number counter receives a number setting signal from outside. 5. The synchronous integration according to claim 1, wherein said write address of said memory is obtained via a flip-flop which receives an output of said address counter as said read address. circuit.