JPH02213929A - Converter for data transfer speed - Google Patents

Abstract

PURPOSE:To prevent the line shifts and the color slurring of a color printer by using a control circuit which starts the parallel/serial conversion after the arrangement of conversion data and a monitoring circuit which monitors the state of the parallel/serial or serial/parallel conversion. CONSTITUTION:A conversion data monitoring circuit 102 monitors what number of bits of conversion data are stored in a serial/parallel conversion circuit 404 based on the NB-bit set value 106. This monitoring information is sent to a control circuit 103, and the circuit 404 is controlled by the output of the circuit 103. An NB data monitoring circuit 104 monitors what number of the NB data are sent to the outside based on the NB-bit set value. Then the next NB data is stored in a parallel/serial conversion circuit (2) 407 at every parallel/serial conversion by NB bits. Thus it is possible to control the data transfer speed with high fidelity and high reliability to the vertical and horizontal synchronous signals sent from a printer and the external clock signal. Then the line shifts can be corrected and the printing jobs are ensured with high contrasts to the wide range of printing conditions.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer rate conversion device, and in particular, to convert data at high speed and with high reliability between a serial signal processing device and a parallel signal processing device with different transfer speeds. The present invention relates to a speed control device for performing transfer.

[Conventional technology]

In recent years, in multifunction printer systems such as those seen in desktop publishing, image data read by an image scanner and video data printed by an optical printer are handled as serial signals, and once transfer begins, these serial signals are On the other hand, the central processing unit (hereinafter referred to as CPU) that controls one image data handles it in units of 8 bits or 16.32 bits, so it is necessary to perform serial/parallel and parallel/serial conversion of the data. For example, regarding the so-called parallel/serial conversion that transfers data from the CPU to an optical printer, the transfer speed of the parallel signal per word sent by the CPU is Dp (word 7 seconds), and the number of bits (in bytes) of the parallel signal is NB (bits/word), and if the transfer rate of the serial signal sent to the optical printer is Ds (bits/second), then s must hold true. However, in a multi-function printer system, the transfer speeds of the two systems are different, so generally equation (1) does not hold true.

Therefore, conventionally, as shown in FIG. 2, a buffer memory 202 (hereinafter BM
) and write data to BM in advance.
Data is read out gradually to eliminate the difference in transfer speed between the two. In other words, the write data 205 of BM
is the write address 2 under software control from the CPU.
09, and the read data 206 is transferred under hardware control at the read address 210 of the address generation circuit 211 based on the external clock 208 from the optical printer. Further, the read data 206 is converted into serial data 207 by a parallel/serial converter 203 and transferred to an optical printer 204. When using this BM, B
If the transfer rate of data written to M is Dw (7 seconds per word) and the speed of data read is DR (7 seconds per word), - Generally speaking, the following must hold true: If Dw = DR, BM is unnecessary. However, as mentioned above, this does not hold true in a multifunction printer system. However, if there is a BM, Dw>DR
It becomes possible to transfer continuous serial signals to the outside.

Figure 3 shows the signal control time sequence of the BM in Figure 2. BM write and read control is based on the vertical synchronization signal 31 (page synchronization signal) and horizontal synchronization signal 33 (line synchronization signal) from the printer. This is done line by line. First, 1 in advance on BM.
6th line data a (write data 32) is written under program control using the horizontal synchronization signal of the first line.

The previous data a (read data 35) is read out by hardware control based on the printer's clock 34, and at the same time, the next line data b is written to the BM.The read data is converted into parallel/serial data. It is synchronized with the printer's clock and transferred to the optical printer.

As described above, in the BM, writing is performed under software control using a program, and reading is performed asynchronously under hardware control using an external clock.

[Problem to be solved by the invention]

The data transfer speed Dw in the equation (2) depends on the CPU machine cycle, memory access time, etc., and the transfer speed Ds to the destination printer is a unique value determined by the printer model. Therefore, when serial signals are sent to the printer continuously at high speed, the relationship in equation (2) must be satisfied.

Figure 4 shows the 8M202 in Figure 2 and the blade array/serial converter 2o3.
An arbitrary bit number setting circuit 401 is placed between the circuits (similar to the parallel/serial conversion circuit (2) 407), and the bit width of NB can be arbitrarily set to perform speed control.

FIG. 5 is a signal processing time sequence of FIG. 4. B
As mentioned above, writing is controlled by software using a program, and reading is controlled by the clock signal 2 of the optical printer.
This is performed under hardware control according to the read address 210 created by the control circuit 405 based on 08. Data 206 read from the BM as shown in FIG. 51 is temporarily held in a latch circuit.

Thereafter, the parallel/serial conversion circuit (1) 403 performs parallel/serial conversion on every 8 bits as shown in 52, and the data is stored in the serial/parallel conversion circuit 404 one bit at a time as shown in 53. When Nts bits of data are stored in the serial/parallel conversion circuit, only NB bits are transferred to the parallel/serial conversion circuit (2), and then parallel/serial conversion is performed as shown in 54 using an external clock. The converted serial signal 207 is sent to the optical printer 2
Sent to 04.

The serial/parallel conversion circuit 404 has a configuration typified by a shift register. FIG. 6 shows the progress in which data is accumulated in this serial/parallel conversion circuit. However, the maximum value of NB was set to 32 bits, and NB was set to 20 bits. Before data is input, random data like A is stored. Each time data is sent from the parallel/serial conversion circuit <1) 403, the data is stored like B and C, and when the nth data is input, it becomes like D. Then, when 20 bits (1 to 20) are transferred as shown in E, the 20 bits from the bottom are transferred to the parallel/serial conversion circuit (2).
Because it will be transferred to.

At the beginning of the serial signal, meaningless data is transferred,
This causes line misalignment, resulting in the phenomenon that the end of the character on the first line appears at the beginning of the second line. This can occur with faxes and printers. Furthermore, in the case of color printers, line misalignment can also cause color misalignment.

Furthermore, one picture is divided into quarters and printed.

If you try to create an enlarged version of the original picture by joining together the individual prints, if the lines are misaligned, the joining will be poor.

An object of the present invention is to provide a data transfer rate conversion device that corrects this line shift and enables clear printing under a wide range of printing conditions.

[Means to solve the problem]

The above object is achieved by performing the following processing with the configuration shown in FIG. FIG. 7 shows the progress of processing in the serial/parallel conversion circuit 404 when NB is 20 bits.
First, as shown in Figure 7B, 32 bits of data (1~
32) after storing.

The 20-bit parallel data (1 to 20) is transferred to the parallel/serial conversion circuit (2) 407, and parallel/serial conversion is started. During that time, data is transferred bit by bit from the parallel/serial conversion circuit (1) 403, and when 20 bits of serial data (1 to 20) are transferred as shown in Figure 7C, the parallel/serial conversion circuit (2) is transferred. ) to the next 20 bits of parallel data (21~
32, 1 to 8) are transferred. Furthermore, when the next 20 bits of serial data (21 to 32, 1 to 8) are transferred from the parallel to serial conversion circuit (1) as shown in Figure 7, the parallel to serial conversion circuit (1)
20-bit parallel data (9 to 2
8), the serial signal 207 is transferred to the printer as needed.

FIG. 8 shows the processing time sequence of FIG.

In the process of FIG. 7B, the vertical synchronization signals 81 and 108 are valid (
during the period from when the horizontal synchronizing signals 82, 107 of the first line are input (T).

time), and after inputting the first line.

The process continues as shown in FIGS. 7C and 7D. here.

The time To from when the vertical synchronization signal becomes valid until the horizontal synchronization signal of the first line is input varies depending on the optical printer or external device.

If the process in Figure 7B is performed within the time using an external clock,
It may not be completed. Also, depending on the model, the external clock may be sent continuously at any time, or it may be sent only while data is being transferred, as shown in Figure 8 84.
In the latter case, the process shown in Figure 7B cannot be performed. Therefore, an oscillation source (internal clock 109) is provided internally to perform serial/parallel conversion independently without being affected by the printer clock or vertical and horizontal synchronization signals. Perform processing.

Furthermore, in the configuration of FIG. 1, as shown in FIG. 5, a conversion data monitoring circuit (l O2
) and an NB data monitoring circuit (104,) for monitoring parallel data (hereinafter referred to as NB data) subjected to parallel/serial conversion by the parallel/serial conversion circuit (2) as shown in 54 in FIG.
have. Further, the control circuit (103) is a circuit for receiving information from the conversion data monitoring circuit and controlling the operation shown in FIG. 7B and the operations after C.

[Effect]

In FIG. 1, the process B in FIG. 7 is performed as follows. When the vertical synchronization signal 10B becomes valid, based on the information of the conversion data monitoring circuit 102.

A read signal 105 is generated from the control circuit 103.

Data (8 bits) is read from the BM. This data is temporarily stored in the parallel/serial conversion circuit (1) 403 and is immediately converted into parallel/serial. - The force control circuit 103 controls the serial/parallel conversion circuit 404 and stores the data parallel/serial converted by the parallel/serial conversion circuit (1) one bit at a time, as shown in FIG. 7B. Bit data is filled.

When the horizontal synchronization signal 107 of the first line is input, the load signal 101 created based on the external clock 208 by the NB data monitoring circuit 104 converts the data 406 for NB bits into the parallel/serial conversion circuit (2). 407 and start parallel/serial conversion. By performing such control.

It becomes possible to transfer correct data from the start of conversion of NB data.

Next, the control at C and after C in FIG. 7 is as follows.

The conversion data monitoring circuit monitors how many bits of conversion data are stored in the serial/parallel conversion circuit based on the N8 bit setting value 106. This information is sent to the control circuit, and the output of the control circuit controls the serial/parallel conversion circuit. In addition, the NB data monitoring circuit monitors how many bits of NB data have been transferred to the outside based on the NB bit setting value, and
Every time B bits are parallel-to-serial converted, the next NB data is stored in the parallel-to-serial conversion circuit (2) using a load signal created based on an external clock. By performing such control, the information is sent from the printer. It is possible to control the data transfer rate faithfully and reliably with respect to vertical and horizontal synchronization signals and external clock signals.

〔Example〕

An embodiment of the present invention is shown in FIG. 9 below. Series in Figure 1
The parallel conversion circuit 404 is a decoder 901 and a flip-flop circuit (hereinafter referred to as F/F) 902 in FIG. 9, and the conversion data monitoring circuit 102 is also a counter (1) 905 . Counter (2) 906 and comparator (1) 907,
The NB data monitoring circuit 104 corresponds to a counter (3) 903 and a comparator (2) 904, respectively. As a specific example, assume that the NB bit setting value 106 is 20 bits.

It is assumed that 32 F/Fs are prepared. Therefore, the counter (1) is a 32-decimal number corresponding to the prepared F/F.

Counters (2) and (3) are 20 of the NB bit setting value.
It is a forward counter.

First, when the vertical synchronization signal 108 first becomes effective, the readout signal 105 output from the control circuit 1.03 causes the BM
Read data from parallel/serial conversion circuit (1) 403
temporarily held. After that, parallel/serial conversion is performed immediately.
/F (1) is stored in order. At this time, the control circuit outputs the information of the counter (1) and controls the decoder. The output of the decoder is input to the gate terminal of each F/F, and it is selected in order from F/F (1), and stops after storing data as shown in Figure 7B up to F/F (32). .

After that, when the horizontal synchronization signal 107 of the first line is input, 20-bit data (outputs of F/Fs (1) to (20)) is transferred to the parallel/serial conversion circuit (2), and the parallel/serial conversion circuit (2) is transferred to the parallel/serial conversion circuit (2). Start serial conversion. From this point on, the control circuit instructs the decoder to open only the gate of F/F (32), the counter (2) receives the conversion data, and the counter (3) receives the N
Start monitoring B data.

FIG. 10 shows the signal flow from this point on.

Data read out from the BM as 10 is converted into serial data as 11 by a parallel/serial conversion circuit (1). This data is first stored in F/F (32), and
/F (32) data is transferred to F/F (31), F/F
The data in (31) is shifted to the next F/F in order, such as F/F (30). Then, when the 20-bit data is transferred as shown in FIG. 10 and 12 and becomes as shown in FIG.
8) is stored in the parallel/serial conversion circuit (2), and 20-bit parallel/serial conversion is performed as shown in FIG. 10.

Then, by repeating one or more processes that start the transition to the next state shown in the seventh diagram, it is possible to transfer data to the optical printer that is valid from the time the transfer is started.

Another embodiment is shown in FIG. 11, in which the parallel/serial conversion circuit (2) 407 in FIG. 1 is the F/F 902 and selector 120 in FIG. Comparator (1) 907. The Ns data monitoring circuit 104 corresponds to a counter (2) 903 and a comparator (2) 904, respectively. As a specific example, as in the previous case, the NB bit is 20 bits and the F/F is 3.
Prepare two. Counters (1) and (2) are.

It is a 20-decimal counter with an NB bit setting value of 106.

The signal flow and the operation of each circuit are not significantly different from those in FIG. First, the selector 120 can be arbitrarily connected to the output terminal of each F/F using the Ns bit setting value. In this example, since Ns is 20 bits, the output of the 20th F/F (1) from the MSB is pointing to. The serial/parallel converter circuit 404 has a configuration typified by a shift register, and the data output from the parallel/serial converter (1) 403 is MS B (Most Significant
ant Bit) side, and each time data is transferred, LSB (Least Significant
nt Bit) side. In FIG. 9, when the vertical synchronization signal 108 becomes valid, 32-bit conversion data is first stored in the serial/parallel conversion circuit, but in this example, 20-bit conversion data is sufficient. When the horizontal synchronizing signal 107 of the first line is input, the previous 20 bits of data are transferred to the 12th line.
As shown in Figure B, NB data is stored in F/Fs (20) to (1).

FIG. 12 schematically shows the data flow of each F/F, and the arrows indicate the outputs of the selectors. The NB data stored in each F/F is shifted in the order of C, D, and E in FIG. 12 by an external clock, and the shifted data is output from the selector in order. Then, when shifted by 20 bits, the next NB data is F/F (20)
~(1), and continue the series of processing. Other than that, the functions and control methods of each control circuit are the same as in FIG. 9.

As described above, in Figure 9, 32-bit conversion data is set in the serial/parallel conversion circuit as an initial setting, and then
Although control was performed for each 0 bit, in this example, it is sufficient to process data every 20 bits from the beginning, and the conversion data monitoring circuit only needs one counter.

The two embodiments constructed based on FIG. Correct data is transferred from the moment parallel/serial conversion starts, so color shifts in color printers and line shifts in FAXs and printers are corrected.

〔Effect of the invention〕

When performing parallel/serial conversion in data transfer between a transmitting means such as a CPU that handles parallel signals and a receiving means that handles serial signals such as an optical printer, the serial data sent to the receiving means must be sent accurately.

According to the present invention, a control circuit for organizing conversion data and then starting parallel/serial conversion, and a monitoring circuit for monitoring the state of parallel/serial or serial/parallel conversion of data are provided, as shown in FIG. By performing the processing shown in , it is possible to perform highly reliable data transfer rate conversion faithfully to the transfer lock and vertical and horizontal synchronization signals from the printer.

Furthermore, the correct data is transferred from the start of the conversion.

It is possible to prevent line misalignment seen in faxes and printers and color misalignment seen on color printers, and it is also possible to print a single sample in sections and connect them to obtain an enlarged sample.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of the present invention, Fig. 2 is a diagram showing a conventional speed conversion example, Fig. 3 is a diagram showing the control time sequence of Fig. 2, and Fig. 4 is a conventional arbitrary bit number setting method. , FIG. 5 is a diagram showing the processing time sequence of FIG. 4, FIG. 6 is a diagram showing the operation transition of the converted data of FIG. 4, and FIG. 7 is a diagram of the operation transition of the converted data of FIG. 1. 8 is a diagram showing the processing time sequence of FIG. 1, FIG. 9 is a diagram showing an embodiment of the present invention, FIG. 10 is a diagram showing the processing time sequence of FIG. 9, and FIG. 11 is a diagram showing the processing time sequence of FIG. 12 is a diagram showing another embodiment of the present invention, and FIG. 12 is a diagram showing the operation transition of the N8 data in FIG. 11. 101... Load signal, 102... Conversion data monitoring circuit, 103... Control circuit, 104... Ns data monitoring circuit, 105... Read signal, 106... N
B bit setting value, 107...Horizontal synchronization signal, 108...
...Vertical synchronization signal, 201...CPU, 202...
Buffer memory, 203... Parallel/serial converter, 20
7...Serial signal, 208...External clock, 211
...Address generation circuit, 401...Arbitrary bit number setting circuit, 402...Latch circuit, 403...Parallel
Serial conversion circuit (1), 404...Serial/parallel conversion circuit, 405...Control circuit, 406...NB bit, 4
o7...Parallel/serial conversion circuit (2), 901...Decoder, 902...Flip-flop, 903...
Counter (3). 904... Comparator (2), 905... Counter (1), 906... Counter (1), 907...
Comparator 120...Selector. Figure FLh release date 735 $E and output date ysr (3 pages - 7 pages) Souyu 11th edition, 1st edition) 52 wJ3 Figure 5'L Figure 4 Figure 6 Figure 7 Q7 Take Take Te'taha Convex Figure 9 0 Old period parking 1 Kihaya Kokuden 41q & 2 Outer enclosure 7 7N 'L row/Snoring 'I East healing full No. 80 Figure 10 I Figure 11 A Figure 12 ε

Claims (1)

[Claims] 1. The interface of the composite printer system is a data transfer rate converter consisting of a buffer memory (BM) and a parallel/serial converter, and the number of parallel signals is changed between the BM and the parallel/serial converter to convert the signal. An arbitrary bit number setting circuit that changes the transfer speed is provided, and the arbitrary bit number setting circuit includes a parallel-to-serial conversion (P/S) circuit (1) and a P/S circuit (2) having the same function as the parallel-to-serial converter. , serial/parallel conversion (S/
P) Circuit and control circuit, conversion data monitoring circuit, N_B
8 or 16 from the transmitting means, consisting of a data monitoring circuit;
The data read in 32 bits is temporarily stored in the BM, and the output data of the BM is stored in the 8 bits in the arbitrary bit number setting circuit.
Or P/S circuit with 16 or 32 bit parallel input (
1), the serial data of the P/S circuit (1) is transmitted to the S by the control of the conversion data monitoring circuit and the control circuit.
- Store one bit at a time in the P circuit, and after filling the S/P circuit with data, store only N_B bits in the P/S circuit (2
) to start P/S and send serial data to the printer, while continuously storing data in the S/P circuit and
The P/S circuit (2) is activated by the signal created by the N_B data monitoring circuit every time _B bits are sent.
1. A data transfer speed converting device characterized in that speed control is performed by repeatedly performing a process of storing new parallel data, performing P/S again, and transmitting the data to a printer.