JPH06143695A - Printing apparatus - Google Patents

Abstract

PURPOSE:To improve the processing speed and save the memory by outputting data of one line while executing OR of data of a plurality of lines in accordance with the reduction rate in the sub scanning direction. CONSTITUTION:When the reduction rate is set, e.g. at 0.75 in a register 1 through a data bus 13 by a CPU, the values of registers 1, 3 are added in an adder 2 to be 0.75. The output value 0.75 of the adder is latched by an output pulse signal 23 in the register 3. The value O.75 of the register 3 is added to the value 0.75 in the register 1, whereby a carry signal 17 is turned to a level L. As a result, 0.5 is an output 16 of the adder 2. An output of a flipflop 4 is in the level L for two lines, and turned to a level H for succeeding lines. The data resulting from ORing of the data of two lines is transferred in video signals. In other words, four lines is transferred as three lines in video signals, whereby the reduction rate 75% is achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus for converting bit map image data read from a memory into a video signal and outputting the video signal.

[0002]

2. Description of the Related Art Conventionally, in a printer having a structure in which character information sent from a host computer or the like is developed as a bit image in an internal memory and then the bit image is read and output, there is a case where reduced printing is performed. , The reduced bit image in memory must be expanded and output again.

[0003]

Therefore, in the conventional printer, it is necessary to store the original bit image to be reduced and the reduced bit image in the memory, which increases the memory capacity and increases the cost. There was a flaw.
Further, there is a drawback that a reduction processing time is required when reducing the size.

The present invention avoids an increase in memory capacity,
An object of the present invention is to provide a printing apparatus that can obtain reduced image data in real time.

[0005]

According to the present invention, a reduction rate setting register for setting a reduction rate, an addition means for sequentially adding reduction rates, and a carry signal from the addition means are sampled by a main scanning synchronization signal. Sampling means, a pulse generator which is activated by a main scanning direction transfer end signal, and which generates a predetermined pulse signal from the sampling result, and an addition result which stores the addition result immediately before the addition by the pulse signal. Storage means, a DMA request controller that generates a request to activate the DMA a predetermined number of times based on the sampling result, and a first data storage means that stores data by DMA transfer that is cleared to "0" from the sampling result. Second data storage means for always storing data by DMA transfer;
A logical sum means for taking a logical sum of the first data storage means and the second data storage means is provided, and one line is processed while performing logical sum processing of data for a plurality of lines according to the reduction ratio in the sub-scanning direction. By outputting as image data, it is possible to obtain a reduced image when converting the image data into a video signal.

[0006]

1 is a block diagram showing an image data sub-scanning direction reduction unit of a printing apparatus according to an embodiment of the present invention.

The register 1 is for setting the reduction rate by the data bus 13 of the CPU (not shown), and the output 14 of the register 1 is input to the adder 2.

The output result 16 of the adder 2 is latched in the register 3 by the output pulse signal 23 of the pulse generator 5. And the output 15 of the register 3 is
It becomes the input of the adder 2 and the output pulse signal 23 is the CPU
The value is cleared to 0 by the clear signal 12 according to the command from.

The adder 2 adds the value set in the register 1 and the value set in the register 3 to obtain a carry signal 1
When 7 is carried, it is set to level L, and when there is no carry, it is set to level H. The carry signal 17 is sampled by the flip-flop 4 at the rising edge of the main scanning synchronization signal 18.

The scan end signal 19 is in the main scanning direction 1
This is a signal which becomes a level L when the conversion of the bit image data for lines into a video signal is completed, and the pulse generator 5 changes the level L of the scan end signal 19 when the output of the flip-flop 4 is a level H. Receiving 1 pulse, the output of flip-flop 4 is at level L
At this time, 2 pulses are output as the output pulse signal 23.

The video clock 21 is output when the printable area (see FIG. 5) is reached in the main scanning direction and converts parallel data into serial data.
The advance counter 6 starts down-counting with this input clock, and the parallel-serial converter (P / S converter) 8 converts parallel data into serial data with this input clock and outputs it as a video signal 32. To do.

The hexadecimal counter 6 receives the clear signal 12
Thus, the level is cleared to L. At this time, the carry signal 24 becomes the level L, and the P / S converter 8 receives the level L of the carry signal 24 and receives the data bus 31.
The content of is taken in as parallel data inside.

DMA request controller (DMAR
When the EQ controller 7 receives the rising edge of the DMA request enable signal (DMAEN signal) 20 to the level H and the rising edge of the carry signal 24 of the hexadecimal counter 6 to the level H, the first DMA request signal (DREQ1). To level L. The DMA controller (not shown) controls the signal level H of DREQ1.
When receiving the data, the DMA operation is started, and when the data 28 is determined from the image memory, the DMA acknowledge (DACK) signal 22 is set to the level L to respond.

The DMAREQ controller 7 uses the DACK
Upon receiving the signal 22, the data latch clock signal 27 is set to level H, the data on the image data 28 is fetched into the register 11, and the DREQ1 signal 25 is set to level H to notify the DMA controller of the end of the DMA operation.
When the output 33 of the flip-flop 4 is at level H, the DMAREQ controller 7 sets the second DMA request 2 (DREQ2) signal at level L to set DREQ1.
The same operation as the signal 25 is performed.

The register 10 latches the data latched by the register 11 with the same data latch clock signal 27 as the register 11, and the OR circuit 9 registers the register 1 with the data.
The output data bus 29 of 1 and the output data bus 9 of the register 10 are ORed, and the output data bus 31 is
It becomes the parallel data of the P / S converter 8. Further, the register 11 is cleared to 0 when the clear signal 12 is at the level L, and the register 10 outputs the output 3 of the flip-flop 4.
When 3 is level L, it is cleared to 0.

Next, the operation of this embodiment will be described.
FIG. 2 is a timing chart showing signal timing in the main scanning direction of the present embodiment, and FIG. 3 is a timing chart showing signal timing in the sub scanning direction.

The CPU first outputs a clear signal 12 to clear the contents of the register 3, hexadecimal counter and register 11 to zero. Next, the CPU sets the reduction rate in the register 1 through the data bus 13. The format of the data set here is fixed point, as shown in FIG. Assuming that the reduction ratio is 0.75, FIG.
(B) is set. In the adder 2, the values of the registers 1 and 3 are added, and here, 0.75 + 0 = 0.7.
It becomes 5.

The main scanning synchronizing signal 18 is sent from the printing unit, and the carry signal 1 of the adder 2 is sent to the flip-flop 4 by the flip-flop 4.
7 is sampled, but since the value of the output 16 is 0.75 here, the carry signal 17 is at the level H, and therefore the level H is output as the output 33.

Next, the CPU sets the DMAEN signal 20 to the level H. In response to this, the DMAREQ controller 7 sets the DREQ1 signal 25 to the level L and requests the DMA controller to activate the DMA (S2).

The DMA controller receives the DREQ1 signal, activates the DMA, and when the data is confirmed on the image memory data bus 28, sets the DACK signal 22 to the level L (S3). The DMAREQ controller 7 is
When receiving the level L of the DACK signal 22, the data latch clock 27 is set to the level H, and the data on the image memory data bus 28 is latched in the register 11 (S
5). After that, the DMAREQ controller 7
The Q1 signal 25 is set to level H and the data latch clock 27 is set to level L. When the DREQ1 signal 25 becomes level H, the DMA controller sends DACK
The signal 22 is set to level H, and the DMA transfer is completed.

Since the output 33 of the flip-flop 4 is at the level H, the DMAREQ controller 7 has the DREQ.
2 signal 26 is set to level L, and the DMA controller is requested again to start DMA (S6). DREQ1 signal 25
, A DMA cycle similar to that of level L is performed, and the processing ends (S7).

When the print area is reached, the video clock signal 21 is output and the carry signal 24 of the hexadecimal counter 6 is output.
Is the level L, the output data 31 of the OR circuit 9 is taken into the P / S converter and output as the video signal 32 (S8). The data taken in here is the logical sum of the data taken in the registers 10 and 11 by the DREQ1 signal 25 and the DREQ2 signal 26.

The hexadecimal counter 6 has a video clock 21.
Is counted and the carry signal 24 is set to level H. In response to this, the DMAREQ controller 7 changes the DREQ1
Signal 25 is set to level L, DMA activation is requested, and D
The REQ2 signal 26 is set to level L to request DMA activation, and the data to be sent as the next video signal is taken into the register 11 and the register 10 (S9, S10).

In the hexadecimal counter 6, the video clock 2
When 1 is counted and 16 is counted, carry signal 24 is set to level L again and data is taken into P / S converter 8 (S11).

Although the above is repeated in the main scanning direction, if the level L of the carry signal of the adder 17 is sampled by the flip-flop 4 and the output 33 thereof is the level L, the DREQ2 signal 26 is not generated. Since the contents of register 10 are cleared to 0, register 11
The data latched by is taken into the P / S converter 8.

Next, regarding the timing in the sub-scanning direction,
This will be described with reference to FIG.

When the one-line video transfer is completed in the main scanning direction, the scan end signal becomes level H (S
100). The pulse generator 5 receives this and outputs the pulse signal 23, but the output 3 of the flip-flop 4
Since 3 is the level H, it is output twice (S100, S
101). In S100, the output pulse signal 23 latches the output value 0.75 of the adder 2 in the register 3. Therefore, the value of register 3 = 0.75 and register 1
Value of 0.75 is added to carry signal 17 at level L
And the result 0.5 becomes the output 16 of the adder 2. S1
The same applies to 01. At the time when the next one-line video transfer is completed, the output 33 of the flip-flop 4 is at the level L, so that only one pulse of the pulse signal 23 is output (S102).

The same operation is performed, and for the two lines, the output of the flip-flop 4 is at the level L and the output of the flip-flop 4 is at the level H for the following lines.
Video data is obtained by taking the logical sum of the line data. In other words, 4 lines are converted into 3 lines and video is transferred, resulting in a reduction rate of 75%.

In the above embodiment, the data bus 13 of the CPU and the image memory data bus 28 are described separately, but they may be shared.

Further, in the above embodiment, the register for latching the image data is composed of a two-stage pipeline, but DREQ1 and DREQ are used as the respective latch clocks.
It may be configured in parallel by providing a latch clock corresponding to 2.

In the above embodiment, the case of using the hexadecimal counter has been described, but this is adapted to the bus width of 16 bits of the image memory data bus. If the image memory data bus is 8 bits, it is octal. Counter, 32
For bits, a counter corresponding to the bus width of the image memory data bus, such as a 32-bit counter, is used.

[0032]

As described above, according to the present invention,
Upon completion of video transfer in the main scanning direction, depending on the reduction rate, it is determined whether to transfer the next main scanning by one line or by performing logical OR processing on a plurality of lines at the same time, and then transfer the video. Therefore, the reduction processing by the CPU and the reduced image memory are not required, the processing speed can be improved, and the memory can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing signal timing in the main scanning direction of the above embodiment.

FIG. 3 is a timing chart showing signal timing in the sub-scanning direction of the above embodiment.

FIG. 4 is a schematic diagram showing a data format when a reduction rate is set in the above embodiment.

FIG. 5 is a schematic diagram showing an example of a main scanning direction and a sub scanning direction of an image.

[Explanation of symbols]

 1 ... Reduction rate setting register, 2 ... Adder, 3 ... Addition result storage register, 5 ... Pulse generator, 6 ... Hexadecimal counter, 7 ... DMA request controller, 8 ... P / S converter, 10, 11 ... Image data Storage register.

Claims (2)

[Claims] 1. A printing apparatus for converting image data into a video signal and outputting the video signal, wherein data of a plurality of lines is logically ORed and output as one line of data in accordance with a reduction ratio in the sub-scanning direction. Characteristic printing device. 2. A reduction rate setting register for setting a reduction rate, an addition means for sequentially adding reduction rates, and a sampling means for sampling a carry signal from the addition means by a main scanning synchronization signal. A pulse generator activated by a main scanning direction transfer end signal to generate a predetermined pulse signal from the sampling result, and an addition result storage means for storing the addition result immediately before the addition by the pulse signal. , A DMA request controller that issues a request to activate the DMA a predetermined number of times from the result of the sampling, and a DMA that is cleared to 0 from the result of the sampling
First data storage means for storing data by transfer;
A printing apparatus comprising: a second data storage means for always storing data by DMA transfer; and a logical sum means for taking a logical sum of the first data storage means and the second data storage means.