JPH08139257A - Surface mount semiconductor device - Google Patents
Surface mount semiconductor deviceInfo
- Publication number
- JPH08139257A JPH08139257A JP6271967A JP27196794A JPH08139257A JP H08139257 A JPH08139257 A JP H08139257A JP 6271967 A JP6271967 A JP 6271967A JP 27196794 A JP27196794 A JP 27196794A JP H08139257 A JPH08139257 A JP H08139257A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- semiconductor device
- lead
- tip
- bent portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、面実装型半導体装置に
関し、特に、高集積度の半導体チップを封止したパッケ
ージの側面から、狭いピッチで複数のリードが引き出さ
れている面実装型半導体装置に適用して有効な技術に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type semiconductor device, and more particularly to a surface mount type semiconductor device in which a plurality of leads are drawn out at a narrow pitch from a side surface of a package in which a highly integrated semiconductor chip is sealed. The present invention relates to a technique effectively applied to a device.
【０００２】[0002]
【従来の技術】ＬＳＩのように高集積度の半導体チップ
を封止したパッケージの側面から、狭いピッチで複数の
リードが引き出された面実装型半導体装置を、ボード
（基板）に半田付けによって面実装してボード製品が組
み立てられている。2. Description of the Related Art A surface mount type semiconductor device in which a plurality of leads are drawn out at a narrow pitch from a side surface of a package in which a highly integrated semiconductor chip such as an LSI is sealed is soldered to a board (substrate). The board product is assembled and assembled.
【０００３】このような面実装型半導体装置は、例えば
ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）と称さ
れる方形状のパッケージが用いられて、このパッケージ
の４つの側面から狭いピッチで複数のリードが引き出さ
れており、あるいはＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎ
ｅ Ｐａｃｋａｇｅ）と称される長方形状のパッケージ
が用いられて、このパッケージの対向する２つの側面か
ら狭いピッチで複数のリードが引き出されている。In such a surface-mounting type semiconductor device, for example, a rectangular package called QFP (Quad Flat Package) is used, and a plurality of leads are drawn out at a narrow pitch from four side surfaces of this package. Or SOP (Small Outlin
A rectangular package referred to as an e package) is used, and a plurality of leads are drawn out at a narrow pitch from two opposing side surfaces of the package.
【０００４】この面実装型半導体装置のパッケージの側
面から引き出されている複数のリードの先端の形状は、
ガルウィング型、Ｊ型、Ｉ型等に形成されて、これら先
端がボードの端子に半田付けされるようになっている。The shapes of the tips of the plurality of leads drawn out from the side surface of the package of the surface mount type semiconductor device are as follows.
It is formed into a gull wing type, a J type, an I type, etc., and these tips are soldered to the terminals of the board.
【０００５】前記のようなボード製品は、デバッグの目
的でロジックアナライザのような測定装置を用いて、性
能の測定が行われる。このようなボード製品の測定にあ
たっては、ボード上に実装されている面実装型半導体装
置の各リードに対して、測定装置の測定用プローブを接
触させた状態で、半導体チップに対して測定用信号が供
給される。The performance of the board product as described above is measured by using a measuring device such as a logic analyzer for the purpose of debugging. When measuring such board products, the measurement signal of the semiconductor chip is measured while the measurement probe of the measurement device is in contact with each lead of the surface-mounted semiconductor device mounted on the board. Is supplied.
【０００６】測定装置による測定の結果、デバッグの対
象になった面実装型半導体装置は、リードの半田付け部
分を溶融してボードから取り外される。As a result of the measurement by the measuring device, the surface-mounted semiconductor device which is the object of debugging is removed from the board by melting the soldering portion of the lead.
【０００７】[0007]
【発明が解決しようとする課題】前記測定装置によって
ボード製品を測定するにあたっては、面実装型半導体装
置の各リードに対して測定用プローブを確実に接触させ
ることが不可欠の条件となる。しかしながら、前記のよ
うなＱＦＰ、ＳＯＰ等のパッケージを採用している従来
の面実装型半導体装置では、そのパッケージの側面から
複数のリードが狭いピッチで引き出されているので、こ
れら各リードに対して測定用プローブを確実に接触させ
るのは極めて困難になっている。When measuring a board product by the above-mentioned measuring device, it is an indispensable condition to make sure that the measuring probe is brought into contact with each lead of the surface mounting type semiconductor device. However, in the conventional surface mount type semiconductor device adopting the package such as QFP or SOP as described above, a plurality of leads are drawn out at a narrow pitch from the side surface of the package, and therefore, for each of these leads. It is extremely difficult to make sure that the measuring probe is brought into contact.
【０００８】また、それに伴って、狭いピッチで引き出
されている隣接リード同士が測定用プローブによって短
絡されるおそれが生ずる。Along with this, there is a possibility that adjacent leads drawn out at a narrow pitch are short-circuited by the measuring probe.
【０００９】本発明の目的は、複数のリードに対して測
定用プローブを確実に接触させることが可能な面実装型
半導体装置を提供することにある。An object of the present invention is to provide a surface mounting type semiconductor device in which a measuring probe can be reliably brought into contact with a plurality of leads.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
【００１２】本発明の面実装型半導体装置は、半導体チ
ップを封止したパッケージの側面から前記半導体チップ
の電極と導通する複数のリードを隣接して引き出した面
実装型半導体装置において、前記複数のリードは、各々
の先端に引き出し方向に沿ってループ状に屈曲した屈曲
部を有している。The surface-mounting semiconductor device of the present invention is a surface-mounting semiconductor device in which a plurality of leads that are electrically connected to the electrodes of the semiconductor chip are adjacently drawn out from the side surface of the package in which the semiconductor chip is sealed. The lead has a bent portion that is bent in a loop shape along the pulling direction at each tip.
【００１３】[0013]
【作用】上述した手段によれば、本発明の面実装型半導
体装置は、パッケージの側面から引き出されている複数
のリードは、各々の先端に引き出し方向に沿ってループ
状に屈曲した屈曲部を有しているので、各リードに対し
て測定用プローブを確実に接触させることが可能とな
る。According to the above-mentioned means, in the surface-mounting type semiconductor device of the present invention, the plurality of leads drawn out from the side surface of the package have bent portions bent in a loop shape along the pulling direction at the tips of the leads. Since it has, it becomes possible to bring the measuring probe into contact with each lead.
【００１４】[0014]
【実施例】以下図面を参照して本発明の実施例を説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
【００１５】（実施例１）図１は本発明の実施例１によ
る面実装型半導体装置を示す上面図で、図２は図１の一
部分を拡大して示す斜視図、図３は図２のＡ方向から見
た側面図である。実施例１による面実装型半導体装置１
は、半導体チップを封止した例えばＱＳＰからなるパッ
ケージ２の４つの側面から、半導体チップの電極と導通
する複数のリード３が隣接して引き出されている。(Embodiment 1) FIG. 1 is a top view showing a surface mount semiconductor device according to Embodiment 1 of the present invention, FIG. 2 is an enlarged perspective view of a part of FIG. 1, and FIG. It is the side view seen from the A direction. Surface mount semiconductor device 1 according to the first embodiment
The plurality of leads 3 that are electrically connected to the electrodes of the semiconductor chip are adjacently drawn out from the four side surfaces of the package 2 made of, for example, QSP that seals the semiconductor chip.
【００１６】複数のリード３は、各々の先端に引き出し
方向に沿ってループ状に屈曲した屈曲部４を有してい
る。ここで、複数のリード３は、その先端の屈曲部４の
形状が交互に異なるように配置され、図２に示すよう
に、一方のリード３の先端の屈曲部４の高さＨ１と、他
方のリード３の先端の屈曲部４の高さＨ２とが交互に異
なる（Ｈ１＜Ｈ２）ように各屈曲部４は形成される。な
お、各屈曲部４の底面は等しい高さに形成されている。
これによって、複数のリード３の隣接したもの同士の先
端の屈曲部４の形状は互いに異なるように配置されてい
る。Each of the leads 3 has a bent portion 4 at the tip thereof, which is bent in a loop shape along the pulling direction. Here, the plurality of leads 3 are arranged so that the shapes of the bent portions 4 at the tips thereof are alternately different, and as shown in FIG. 2, the height H1 of the bent portions 4 at the tip of one lead 3 and the other Each bent portion 4 is formed so that the height H2 of the bent portion 4 at the tip of the lead 3 is alternately different (H1 <H2). The bottom surface of each bent portion 4 is formed to have the same height.
As a result, the shapes of the bent portions 4 at the tips of the adjacent ones of the plurality of leads 3 are arranged to be different from each other.
【００１７】次に実施例１による面実装型半導体装置１
の製造方法を図４を参照して工程順に説明する。Next, the surface mount semiconductor device 1 according to the first embodiment.
The manufacturing method will be described in the order of steps with reference to FIG.
【００１８】まず、図４（Ａ）に示すように、複数のリ
ード３及び半導体チップを搭載すべきタブ５を有するよ
うに所望のパターンに形成された、例えばＦｅ−Ｎｉ合
金からなるリードフレーム６を用意する。この場合、特
にリード３の長さを長く設定した形状のリードフレーム
を６を用いるようにする。これは、この後でリード３の
先端に屈曲部４を形成するためである。First, as shown in FIG. 4A, a lead frame 6 made of, for example, a Fe--Ni alloy formed in a desired pattern so as to have a plurality of leads 3 and a tab 5 on which a semiconductor chip is to be mounted. To prepare. In this case, the lead frame 6 having a shape in which the length of the lead 3 is set to be long is used. This is because the bent portion 4 is formed at the tip of the lead 3 after this.
【００１９】次に、図４（Ｂ）に示すように、リードフ
レーム６のタブ５上にＬＳＩチップからなる半導体チッ
プ７を例えばシリコーンゴムのような高熱伝導性接着剤
によって搭載した後、半導体チップ７の電極８と対応し
たリード３との間に例えばＡｕ線からなるワイヤ９をボ
ンディングする。Next, as shown in FIG. 4B, after mounting the semiconductor chip 7 made of an LSI chip on the tab 5 of the lead frame 6 with a high thermal conductive adhesive such as silicone rubber, the semiconductor chip is mounted. A wire 9 made of, for example, an Au wire is bonded between the electrode 8 of No. 7 and the corresponding lead 3.
【００２０】続いて、図４（Ｃ）に示すように、リード
フレーム６を例えばトランスファモールド装置にセット
して、樹脂成型を行って、タブ５、半導体チップ７、ボ
ンディングワイヤ９及びリード３の内端をパッケージ２
によって封止する。これにより、複数のリード３の外端
はパッケージ２の側面に引き出されたことになる。Subsequently, as shown in FIG. 4C, the lead frame 6 is set in, for example, a transfer molding apparatus, and resin molding is performed, so that the tab 5, the semiconductor chip 7, the bonding wire 9 and the lead 3 are formed. Package the end 2
Sealed by. As a result, the outer ends of the leads 3 are pulled out to the side surface of the package 2.
【００２１】次に、図４（Ｄ）に示すように、パッケー
ジ２の側面から引き出されている複数のリード３を例え
ばプレス装置にセットして、整形を行うことにより、図
２に示すように一方のリード３の先端の屈曲部４の高さ
Ｈ１と、他方のリード３の先端の屈曲部４の高さＨ２と
が交互に異なるように各屈曲部４を形成する。これによ
って、実施例１による面実装型半導体装置１が完成す
る。Next, as shown in FIG. 4 (D), a plurality of leads 3 drawn out from the side surface of the package 2 are set in, for example, a pressing device and shaped to perform shaping as shown in FIG. Each bent portion 4 is formed such that the height H1 of the bent portion 4 at the tip of one lead 3 and the height H2 of the bent portion 4 at the tip of the other lead 3 are alternately different. As a result, the surface mount semiconductor device 1 according to the first embodiment is completed.
【００２２】このような実施例１によれば次のような効
果が得られる。According to the first embodiment, the following effects can be obtained.
【００２３】（１）パッケージ２の側面から引き出され
ている複数のリード３は、各々の先端に引き出し方向に
沿ってループ状に屈曲した屈曲部４を有しているので、
この面実装型半導体装置１を実装したボード製品の測定
を行う場合、測定用プローブを容易にその屈曲部４に接
触させることができるため、各リード３に対して測定用
プローブを確実に接触させることができる。(1) Since the plurality of leads 3 drawn out from the side surface of the package 2 have the bent portions 4 which are bent in a loop shape along the pulling direction at each tip,
When measuring a board product on which the surface-mounted semiconductor device 1 is mounted, the measuring probe can be easily brought into contact with the bent portion 4, so that the measuring probe is surely brought into contact with each lead 3. be able to.
【００２４】（２）隣接する複数のリード３のうち、一
方のリード３の先端の屈曲部４の高さＨ１と他方のリー
ド３の先端の屈曲部４の高さＨ２とが異なるように各屈
曲部４が形成されているので、隣接するリード同士は屈
曲部４の形状が互いに異なっているため、隣接するリー
ド３が狭いピッチで配置されていても、実質上ピッチ間
隔が広がるようになって、測定用プローブによって隣接
するリード同士が短絡するおそれがなくなる。(2) Among a plurality of adjacent leads 3, the height H1 of the bent portion 4 at the tip of one lead 3 and the height H2 of the bent portion 4 at the tip of the other lead 3 are different from each other. Since the bent portions 4 are formed, the shapes of the bent portions 4 of the adjacent leads are different from each other. Therefore, even if the adjacent leads 3 are arranged at a narrow pitch, the pitch interval is substantially widened. As a result, there is no possibility that adjacent leads are short-circuited by the measuring probe.
【００２５】（３）複数のリード３の先端に屈曲部４を
形成することで、リード面積が増加するので、半導体チ
ップ７で発生した熱の放熱効果を向上することができ
る。(3) Since the lead area is increased by forming the bent portion 4 at the tips of the plurality of leads 3, the heat radiation effect of the heat generated in the semiconductor chip 7 can be improved.
【００２６】（実施例２）図５は本発明の実施例２によ
る面実装型半導体装置を示す上面図で、図６は図５の一
部分を拡大して示す斜視図、図７は図６のＡ方向から見
た側面図である。実施例２による面実装型半導体装置１
は、複数のリード３は、各々の先端に引き出し方向に沿
ってループ状に屈曲した屈曲部４を有している。ここ
で、複数のリード３は、その先端の屈曲部４の形状が交
互に異なるように配置され、図６に示すように、一方の
リード３の先端の屈曲部４の引き出し方向に沿った位置
（距離）Ｌ１と、他方のリード３の先端の屈曲部４の引
き出し方向に沿った位置（距離）Ｌ２とが交互に異なる
ように各屈曲部４は形成される。なお、各屈曲部４の底
面は等しい高さに形成されている。これによって、複数
のリード２の隣接したもの同士の先端の屈曲部４の形状
は互いに異なるように配置されている。(Embodiment 2) FIG. 5 is a top view showing a surface mount semiconductor device according to Embodiment 2 of the present invention, FIG. 6 is an enlarged perspective view of a part of FIG. 5, and FIG. It is the side view seen from the A direction. Surface mount semiconductor device 1 according to the second embodiment
The plurality of leads 3 each have a bent portion 4 bent in a loop shape along the pulling direction at the tip thereof. Here, the plurality of leads 3 are arranged so that the shapes of the bent portions 4 at the tips thereof are alternately different, and as shown in FIG. 6, the positions of the tips of one of the leads 3 along the pull-out direction of the bent portions 4 Each bent portion 4 is formed such that the (distance) L1 and the position (distance) L2 along the pulling direction of the bent portion 4 at the tip of the other lead 3 are different from each other. The bottom surface of each bent portion 4 is formed to have the same height. Thereby, the shapes of the bent portions 4 at the tips of the adjacent ones of the plurality of leads 2 are arranged to be different from each other.
【００２７】このような実施例２によれば次のような効
果が得られる。According to the second embodiment, the following effects can be obtained.
【００２８】（１）パッケージ２の側面から引き出され
ている複数のリード３は、実施例１と同様に、各々の先
端に引き出し方向に沿ってループ状に屈曲した屈曲部４
を有しているので、この面実装型半導体装置１を実装し
たボード製品の測定を行う場合、測定用プローブは容易
にその屈曲部４に接触するため、各リード３に対して測
定用プローブを確実に接触させることができる。(1) The plurality of leads 3 drawn out from the side surface of the package 2 are bent at the tips of the leads 3 in a loop shape along the drawing direction, as in the first embodiment.
Therefore, when measuring a board product on which the surface-mounted semiconductor device 1 is mounted, the measurement probe easily contacts the bent portion 4, so that the measurement probe is attached to each lead 3. It is possible to make sure contact.
【００２９】（２）隣接する複数のリード３のうち、一
方のリード３の先端の屈曲部４の引き出し方向に沿った
位置Ｌ１と他方のリード３の先端の屈曲部４の引き出し
方向に沿った位置Ｌ２とが異なるように各屈曲部４が形
成されているので、隣接するリード同士は屈曲部４の形
状が互いに異なっているため、隣接するリード３が狭い
ピッチで配置されていても、実質上ピッチ間隔が広がる
ようになって、測定用プローブによって隣接するリード
同士が短絡するおそれがなくなる。(2) Among a plurality of leads 3 adjacent to each other, a position L1 along the drawing direction of the bent portion 4 at the tip of one lead 3 and a drawing direction of the bent portion 4 at the tip of the other lead 3 are provided. Since the bent portions 4 are formed so as to be different from the position L2, the shapes of the bent portions 4 of the adjacent leads are different from each other. Therefore, even if the adjacent leads 3 are arranged at a narrow pitch, it is substantially the same. Since the upper pitch interval is widened, there is no possibility that adjacent leads are short-circuited by the measuring probe.
【００３０】（３）実施例１と同様に、複数のリード３
の先端に屈曲部４を形成することで、リード面積が増加
するので、半導体チップ７で発生した熱の放熱効果を向
上することができる。(3) Similar to the first embodiment, the plurality of leads 3
Since the lead area is increased by forming the bent portion 4 at the tip of the, the heat dissipation effect of the heat generated in the semiconductor chip 7 can be improved.
【００３１】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３２】例えば、前記実施例ではパッケージ２がＱ
ＦＰから構成した例で説明したが、これに限らずＳＯＰ
のような他のパッケージで構成した場合でも、同様に適
用することができる。また、複数のリード３の先端に形
成する屈曲部４の形状は、完全に閉じられた形状でなく
ともほぼループ状になっていれば特定の形状にこだわる
必要はない。例えば円形に近い形状でも、方形に近い形
状になっていても良い。For example, in the above embodiment, the package 2 is Q
Although the example has been described by using the FP, the SOP is not limited to this.
Even if it is configured with another package such as, the same can be applied. Further, the shape of the bent portion 4 formed at the tips of the plurality of leads 3 does not have to be a particular shape as long as it is a substantially loop shape even if it is not a completely closed shape. For example, it may have a shape close to a circle or a shape close to a square.
【００３３】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である面実装
型半導体装置の製造技術に適用した場合について説明し
たが、それに限定されるものではない。本発明は、少な
くともパッケージの側面から狭いピッチで複数のリード
が引き出されている条件のものには適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the surface mounting type semiconductor device which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. The present invention can be applied to at least the condition where a plurality of leads are drawn out at a narrow pitch from the side surface of the package.
【００３４】[0034]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３５】パッケージの側面から狭いピッチで複数の
リードが引き出されている面実装型半導体装置を実装し
たボード製品の測定を行う場合、各リードに対して測定
用プローブを確実に接触させることができる。When a board product mounted with a surface-mounted semiconductor device in which a plurality of leads are drawn out at a narrow pitch from the side surface of the package is measured, the measurement probe can be surely brought into contact with each lead. .
【００３６】隣接するリードが狭いピッチで配置されて
いても、測定用プローブによって隣接するリード同士が
短絡されるおそれがなくなる。Even if the adjacent leads are arranged at a narrow pitch, there is no possibility that the adjacent leads are short-circuited by the measuring probe.
【図１】本発明の実施例１による面実装型半導体装置を
示す上面図である。FIG. 1 is a top view showing a surface mount semiconductor device according to a first embodiment of the present invention.
【図２】図１の一部分を拡大して示す斜視図である。FIG. 2 is an enlarged perspective view showing a part of FIG.
【図３】図２のＡ方向から見た側面図である。FIG. 3 is a side view seen from the direction A in FIG.
【図４】本発明の実施例１による面実装型半導体装置の
製造方法を示すもので、（Ａ）乃至（Ｄ）は断面図であ
る。4A to 4D are sectional views showing a method of manufacturing a surface mount semiconductor device according to Embodiment 1 of the present invention.
【図５】本発明の実施例２による面実装型半導体装置を
示す上面図である。FIG. 5 is a top view showing a surface-mounted semiconductor device according to a second embodiment of the invention.
【図６】図５の一部分を拡大して示す斜視図である。FIG. 6 is a perspective view showing a part of FIG. 5 in an enlarged manner.
【図７】図６のＡ方向から見た側面図である。FIG. 7 is a side view as seen from the direction A in FIG.
１…半導体装置、２…パッケージ、３…リード、４…リ
ードの屈曲部、５…タブ、６…リードフレーム、７…半
導体チップ、８…半導体チップの電極、９…ボンディン
グワイヤ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Package, 3 ... Lead, 4 ... Lead bending part, 5 ... Tab, 6 ... Lead frame, 7 ... Semiconductor chip, 8 ... Semiconductor chip electrode, 9 ... Bonding wire.
Claims (4)
面から前記半導体チップの電極と導通する複数のリード
を隣接して引き出した面実装型半導体装置において、前
記複数のリードは、各々の先端に引き出し方向に沿って
ループ状に屈曲した屈曲部を有することを特徴とする面
実装型半導体装置。1. A surface mount semiconductor device in which a plurality of leads, which are electrically connected to electrodes of the semiconductor chip, are adjacently drawn from a side surface of a package in which a semiconductor chip is sealed, and the plurality of leads are drawn to respective tips. A surface-mounted semiconductor device having a bent portion that is bent in a loop shape along a direction.
は、前記先端の屈曲部の形状が互いに異なって配置され
ていることを特徴とする請求項１記載の面実装型半導体
装置。2. The surface mounting type semiconductor device according to claim 1, wherein adjacent ones of the plurality of leads are arranged such that the shape of the bent portion of the tip is different from each other.
は、一方のリードの先端の屈曲部の高さと他方のリード
の先端の屈曲部の高さとが、互いに異なって配置されて
いることを特徴とする請求項２記載の面実装型半導体装
置。3. The adjacent ones of the plurality of leads are arranged such that the height of the bent portion at the tip of one lead and the height of the bent portion at the tip of the other lead are different from each other. The surface mount semiconductor device according to claim 2.
は、一方のリードの先端の屈曲部の引き出し方向に沿っ
た位置と他方のリードの先端の屈曲部の引き出し方向に
沿った位置とが、互いに異なって配置されていることを
特徴とする請求項２記載の面実装型半導体装置。4. The adjacent ones of the plurality of leads have a position along a pulling direction of a bent portion at the tip of one lead and a position along a pulling direction of a bent portion at the tip of the other lead. 3. The surface mount semiconductor device according to claim 2, wherein the surface mount semiconductor devices are arranged differently from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6271967A JPH08139257A (en) | 1994-11-07 | 1994-11-07 | Surface mount semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6271967A JPH08139257A (en) | 1994-11-07 | 1994-11-07 | Surface mount semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08139257A true JPH08139257A (en) | 1996-05-31 |
Family
ID=17507309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6271967A Withdrawn JPH08139257A (en) | 1994-11-07 | 1994-11-07 | Surface mount semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08139257A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007122516A3 (en) * | 2006-04-26 | 2008-04-03 | Cotco Luminant Device Ltd | Apparatus and method for use in mounting electronic elements |
| JP2008258617A (en) * | 2007-03-30 | 2008-10-23 | Seoul Semiconductor Co Ltd | Led package with metal pcb |
| US7675145B2 (en) | 2006-03-28 | 2010-03-09 | Cree Hong Kong Limited | Apparatus, system and method for use in mounting electronic elements |
| US7821023B2 (en) | 2005-01-10 | 2010-10-26 | Cree, Inc. | Solid state lighting component |
| US8049230B2 (en) | 2008-05-16 | 2011-11-01 | Cree Huizhou Opto Limited | Apparatus and system for miniature surface mount devices |
| US9722158B2 (en) | 2009-01-14 | 2017-08-01 | Cree Huizhou Solid State Lighting Company Limited | Aligned multiple emitter package |
| US9793247B2 (en) | 2005-01-10 | 2017-10-17 | Cree, Inc. | Solid state lighting component |
| US10256385B2 (en) | 2007-10-31 | 2019-04-09 | Cree, Inc. | Light emitting die (LED) packages and related methods |
| US10622522B2 (en) | 2014-09-05 | 2020-04-14 | Theodore Lowes | LED packages with chips having insulated surfaces |
| US10892383B2 (en) | 2007-10-31 | 2021-01-12 | Cree, Inc. | Light emitting diode package and method for fabricating same |
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-
1994
- 1994-11-07 JP JP6271967A patent/JPH08139257A/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821023B2 (en) | 2005-01-10 | 2010-10-26 | Cree, Inc. | Solid state lighting component |
| US9793247B2 (en) | 2005-01-10 | 2017-10-17 | Cree, Inc. | Solid state lighting component |
| US7675145B2 (en) | 2006-03-28 | 2010-03-09 | Cree Hong Kong Limited | Apparatus, system and method for use in mounting electronic elements |
| US7635915B2 (en) | 2006-04-26 | 2009-12-22 | Cree Hong Kong Limited | Apparatus and method for use in mounting electronic elements |
| WO2007122516A3 (en) * | 2006-04-26 | 2008-04-03 | Cotco Luminant Device Ltd | Apparatus and method for use in mounting electronic elements |
| JP2008258617A (en) * | 2007-03-30 | 2008-10-23 | Seoul Semiconductor Co Ltd | Led package with metal pcb |
| US10892383B2 (en) | 2007-10-31 | 2021-01-12 | Cree, Inc. | Light emitting diode package and method for fabricating same |
| US10256385B2 (en) | 2007-10-31 | 2019-04-09 | Cree, Inc. | Light emitting die (LED) packages and related methods |
| US11791442B2 (en) | 2007-10-31 | 2023-10-17 | Creeled, Inc. | Light emitting diode package and method for fabricating same |
| US8049230B2 (en) | 2008-05-16 | 2011-11-01 | Cree Huizhou Opto Limited | Apparatus and system for miniature surface mount devices |
| US9722158B2 (en) | 2009-01-14 | 2017-08-01 | Cree Huizhou Solid State Lighting Company Limited | Aligned multiple emitter package |
| US11210971B2 (en) | 2009-07-06 | 2021-12-28 | Cree Huizhou Solid State Lighting Company Limited | Light emitting diode display with tilted peak emission pattern |
| US10622522B2 (en) | 2014-09-05 | 2020-04-14 | Theodore Lowes | LED packages with chips having insulated surfaces |
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
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