JPH11233709A - Semiconductor device, its manufacture and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable narrowing lead pitch by alternately protruding upper step leads and lower step leads from two steps of height on the respective side surfaces of a package, along the lead arrangement direction. SOLUTION: A semiconductor device 1 has an external structure where a plurality of leads 3 are protruded from both side surfaces of a package 2 which is oblong and flat. Lead groups protruded from the respective side surfaces of the package 2 are constituted of upper step leads 4 and lower step leads 5 which are alternately protruded from two steps of height on the side surfaces of the package 2, along the lead arrangement direction. A plurality of the leads 3 protruded from one side surface are arranged protruding in order in a staggered shape, and manufactured so as not to generate interference between the respective leads 3, so that lead pitch of the lead groups can be more narrowed than a lead pitch working marginal value in the work of a lead frame, and the narrowing of lead pitch of the semiconductor device or miniaturization of a semiconductor device due to miniaturization of the package can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and an electronic device. More particularly, the present invention relates to a technology effective when applied to a technology of manufacturing a semiconductor device which can be miniaturized by reducing a lead pitch.

[0002]

2. Description of the Related Art Semiconductor devices such as ICs and LSIs have high performance,
The number of terminals (referred to as leads and pins) has increased due to the higher integration.

A resin-sealed semiconductor device has an external shape in which a plurality of leads protrude from the peripheral surface of an insulating resin package. A semiconductor chip is located inside the package, and electrodes of the semiconductor chip and inner ends of the leads are electrically connected by connection means for electrically connecting, for example, conductive wires.

Further, the shape of the lead protruding from the package is a butt lead, gull wing, J lead, or the like.

On the other hand, a lead frame is used for manufacturing a resin-sealed semiconductor device. The lead frame generally has a structure in which a plurality of desired lead patterns are arranged in series along a strip-shaped metal plate. The lead frame is formed by pressing or etching a thin metal plate.

For the processing of the lead frame, see, for example, “Nikkei Micro Device” published by Nikkei BP, August 1988.
The monthly issue is published on August 1, the same year, and is described on pages 54 to 60. This document describes the press limit of the lead frame.

On the other hand, in a semiconductor device having a structure in which the number of electrodes of a semiconductor chip is large, a composite lead frame (such as a two-step lead frame) in which a plurality of lead frames are partially or wholly overlapped is used for manufacturing the semiconductor device. ing.

[0008] For example, Japanese Patent Application No. Hei 5-200585 discloses a semiconductor device in which two lead frames are stacked and the inner lead portion of one lead frame is fixed to the inner lead portion of the other lead frame. Is disclosed. That is, in the semiconductor device having this structure, the inner leads have two layers and the outer leads have one layer.

[0009]

In the lead frame punching process, for example, the lead pitch is about 80% of the plate thickness, which is the minimum processing size in mass production. Therefore, if a generally used lead frame material having a plate thickness is used, the minimum value of the lead pitch is naturally determined.

The number of leads is increasing due to the multifunctionality and high integration of semiconductor devices. As a result, the package size increases with the increase in the number of pins, and the electronic device incorporating these semiconductor devices also increases in size.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of achieving a reduction in lead pitch.

Another object of the present invention is to reduce the size of an electronic device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of typical inventions disclosed in the present application. (1) A package, a semiconductor chip located inside the package, a plurality of leads extending side by side inside and outside the package, and electrically connecting an inner end of the lead and an electrode of the semiconductor chip. A lead group protruding from each side surface of the package, the upper lead and the lower lead protruding alternately along the lead arrangement direction from two levels of height of the side surface of the package. It is composed of One of the protruding lengths of the upper and lower leads is longer and the other is shorter. The positions of the mounting ends of the molded leads formed at the protruding tips of the upper and lower leads are arranged in a staggered manner. The shapes of the formed lead portions of the upper lead and the lower lead are different from each other. The shape of the molded lead portion of the upper lead and the lower lead is a combination of one or two of butt lead, gull wing, J lead, and Z lead. For example, the molded lead portion of the lower lead having a short protruding length is a J lead, and the molded lead portion of the upper lead having a long protruding length is a gull wing. Further, the upper lead and the lower lead are adhesively connected to each other in the package by an insulating connecting body.

Such a semiconductor device is manufactured by the following method. A lower lead frame having a tab on which a semiconductor chip is mounted, the tip of the inner lead being close to the peripheral edge of the tab, and the tip of at least a part of the inner lead being fixed to the lower lead frame in an overlapping manner; Preparing an upper lead frame that is located above the tab and the outer leads are configured to be displaced above the outer leads of the lower lead frame; anda semiconductor chip on the tab of the lower lead frame. Fixing, electrically connecting the electrodes of the semiconductor chip and the respective leads of the lower lead frame, overlapping the upper lead frame on the lower lead frame and partially fixing the two-stage lead frame. Manufacturing step, electrically connecting the electrodes of the semiconductor chip and the respective leads of the upper lead frame. Forming a package by covering the tab, the semiconductor chip, the connection means, and the tip of the lead with an insulating resin; cutting and removing an unnecessary portion of the two-stage lead frame; Forming a lead projecting from the package into a predetermined shape, wherein the two-stage lead frame is such that a group of leads projecting from each side surface of the package is arranged in a lead arrangement direction from a two-stage height of the side surface of the package. The upper lead and the lower lead are formed so as to alternately protrude along the upper lead and the lower lead. At the time of forming the lead, the upper lead and the lower lead are formed so that the protruding length becomes alternately longer and shorter. Molding is performed so that the positions of the mounting ends of the molding leads formed in the portions are in a staggered arrangement. The leads are formed such that the shapes of the forming leads of the upper lead and the lower lead are different from each other.
In the lead forming, the protruding length of the upper lead is made longer and the forming lead portion at the protruding tip is formed into a gull wing, and the protruding length of the lower lead is shortened and the forming lead portion at the protruding tip is formed as a J lead. The lower lead frame and the upper lead frame are fixedly bonded to each other by an insulating connecting member.

An electronic device incorporating the semiconductor device has the following configuration. A package, a semiconductor chip located inside the package, a plurality of leads extending side by side inside and outside the package, and connection means for electrically connecting an inner end of the lead and an electrode of the semiconductor chip. Wherein the lead group projecting from each side surface of the package in the semiconductor device alternately protrudes along the lead arrangement direction from a two-stage height of the package side surface. Mounting a molded lead portion formed at the protruding tip portions of the upper and lower leads, one of which is longer and the other has a shorter length. The end positions are arranged in a staggered pattern. The shapes of the formed lead portions of the upper lead and the lower lead are different from each other. The upper lead has a long gull wing and the lower lead has a short protrusion and a J lead.

According to the above means (1), (a) the upper lead and the lower lead are alternately projected from the two heights of each side surface of the package, and the projecting length of the upper lead and the lower lead is determined. Since the length of each lead is short and long, and the positions of the mounting ends of the molded leads are arranged in a staggered manner so that both leads do not interfere with each other, the lead pitch of the lead group is greater than the lead pitch processing limit value in lead frame processing. Can be reduced, and the lead pitch of the semiconductor device can be reduced. As a result, in the semiconductor device, it is possible to increase the number of pins in a package of the same size or downsize the package with the same number of pins.

(B) Since the lead pitch of the semiconductor device can be narrowed, in an electronic device incorporating this semiconductor device, when the package size of the semiconductor device is reduced, the mounting area of the semiconductor device can be reduced. The size of the electronic device can be reduced.

(C) Since the lead pitch of the semiconductor device can be narrowed, a semiconductor device having a large number of leads (pins) can be incorporated in an electronic device incorporating the semiconductor device, and the electronic device has high functionality. And so on.

(D) Since the mounting ends of the leads of the semiconductor device are arranged in a staggered manner, no failure occurs due to the contact between the bonding materials in the mounted state, and the reliability of the electronic device is improved.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIGS. 1 to 14 are diagrams relating to a semiconductor device according to an embodiment (Embodiment 1) of the present invention and an electronic device incorporating the semiconductor device.

As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment has an elongated flat package 2 in appearance.
The structure is such that a plurality of leads 3 protrude from both side surfaces. The lead group protruding from each side surface of the package 2 is composed of an upper lead 4 and a lower lead 5 which protrude alternately from the two heights of the side surface of the package 2 along the lead arrangement direction. That is, the plurality of leads 3 protruding from one side surface are sequentially protruded in a staggered manner.

The protruding lengths of the upper lead 4 and the lower lead 5 are longer on one side and shorter on the other. The protruding length is a length from the package 2 to an end (protruding end) extending linearly in the horizontal direction, as shown in FIG. The projecting length of the lower lead 5 is g, which is short and long. That is, the upper lead 4 and the lower lead 5 are longer or shorter.

The shapes of the formed lead portions 4a and 5a formed at the protruding tips of the upper lead 4 and the lower lead 5 are different from each other. For example, the shape of the molded lead portion 4a of the upper lead 4 is a gull wing, and the shape of the molded lead portion 5a of the lower lead 5 is a J lead.
That is, the outer lead 4c of the upper lead 4 is a gull-wing type, and the outer lead 5c of the lower lead 5 is a J-lead type.

In the gull wing, the mounting end 4b is located on the extension side of the protruding end of the lead 3, and in the J lead, the mounting end 5b is located inside the protruding end of the lead 3, so that the upper lead 4 and the lower lead 5 are located. The arrangement of the mounting ends 4b and 5b is staggered (see FIG. 1).

Since the protruding lengths of the upper lead 4 and the lower lead 5 are different, the arrangement of the protruding ends is also staggered when viewed from above. As a result, the arrangement of the mounting ends becomes staggered even if the shapes of the molding leads are the same.

FIG. 1 is a perspective view showing a mounting structure in which the semiconductor device 1 of the first embodiment is mounted, that is, a part of an electronic device 10. FIG. 4 is a schematic view showing a footprint 12 for mounting the semiconductor device 1 on a mounting board 11 of the electronic device 10.

Since the footprints 12 correspond to the mounting ends 4b and 5b of the semiconductor device 1, the footprints 12 are arranged in a staggered pattern.

As shown in FIG. 3, the mounting ends 4b, 5
b is fixed (mounted) to the footprint 12 of the mounting board 11 via the solder 13.

In the first embodiment, the molding leads 4a, 5
Although a is a gull wing and a J-lead, a combination of other types (shapes) may be used. That is, butt lead,
One or two types of gull wings, J leads and Z leads may be used. However, even in this case, it is necessary to form a staggered arrangement so that adjacent leads are not short-circuited by the solder bridge in the mounting portion.

As shown in FIGS. 2 and 3, the semiconductor device 1 has a tab 6 in the package 2 and a semiconductor chip 7 is fixed on the tab 6 by a bonding material (not shown).

The tip of the inner lead 5 d of the lower lead 5 is close to the periphery of the tab 6. The tip of a part of the inner lead 4d of the upper lead 4 extends above the semiconductor chip 7, and the tip of the part of the inner lead 4d is located above the peripheral edge of the semiconductor chip 7.

The inner ends of the leads 3 (the upper leads 4 and the lower leads 5) (the inner ends of the inner leads 4d and 5d).
And the electrodes (not shown) of the semiconductor chip 7 are electrically connected by connecting means. That is, they are specifically connected by conductive wires 9. The electrical connection means may have another configuration.

Also, leads 3 (inner leads 4d, 5d) extending in two steps in the package 2
Are bonded and connected by an insulating connecting body 8. For example, the connecting body 8 is formed of an insulating resin tape having a sticky surface.

Here, as shown in FIGS. 3 and 4, an example of dimensions of each part such as a lead and a footprint related to mounting will be described.

The footprints 12 are arranged in two rows on both sides of the package 2 of the semiconductor device 1, respectively.
Are arranged side by side, and the other row is arranged so as to be displaced at a half pitch (a) with respect to one row, and is arranged in a staggered manner. Therefore, the dimension of b is half of the pitch a of the footprints 12 in one row. If a is 0.30 mm, b becomes 0.15 mm.

The length of the footprint 12 is e (= 0.95 mm) for the gull wing lead and d (= 1.50 mm) for the J lead.

The width of the footprint 12 is the same for the gull wing lead and the J lead, and c (= 0.
30 mm).

The distance f between the footprints 12 arranged in a zigzag pattern and located in the oblique direction is 0.30.
mm.

The protruding length h of the upper lead 4 is 0.4
0 mm, and the protruding length g of the lower lead 5 is 0.20 mm.

Due to the size of each part, the distance between the footprints 12 is at least 0.30 mm apart, thereby preventing the occurrence of a solder bridge at the time of mounting.

Next, a method of manufacturing the semiconductor device 1 according to the first embodiment will be described. In manufacturing the semiconductor device 1, a lower lead frame 30 shown in FIG. 6 and an upper lead frame 40 shown in FIG. 7 are used. These main and upper lead frames 30 and 40 are overlapped and connected during the manufacture of the semiconductor device and used as a two-stage lead frame 20 as shown in FIGS.

The lower lead frame 30 and the upper lead frame 40 are made of iron and have a thickness of about 0.15 to 0.1 mm.
It has a shape obtained by punching a nickel alloy plate or a copper alloy plate into a desired pattern by pressing. In addition, the outer dimensions of the lead frame frames 31 and 41 of the lower lead frame 30 and the upper lead frame 40 are the same, and when the two-stage lead frame 20 is used, it has a shape that does not hinder handling.

As shown in FIGS. 6 and 7, a pair of parallel extending outer frames 32, 41 are provided for the lead frame frames 31, 41.
42 and the pair of outer frames 32, 42
It has a frame structure formed by a pair of inner frames 33 and 43 extending in a direction orthogonal to 42.

A rectangular tab (support plate) 6 is arranged at the center of the lower lead frame 30, and no tab is provided at the center of the upper lead frame 40,
It has become.

That is, in the two-stage lead frame 20 of the first embodiment, the tab 6
Is present, and one of the features of the present invention is that the upper lead frame 40 has no tab.

The tab 6 at the center of the lower lead frame 30
Are supported by tab suspension leads 35 extending from the outer frame 32 as in the case of a general lead frame.
The outer end portion of the tab suspension lead 35 is bifurcated and connected to the outer frame 32 for the purpose of stress absorption. The tab 6 is formed one step lower.

On the other hand, a plurality of leads 3 extend from the inner frames 33 and 43 toward the center of the frame. The lead 3 of the upper lead frame 40 is also referred to as the upper lead 4 because it becomes the upper lead in the state of the two-stage lead frame 20. On the other hand, the lead 3 of the lower lead frame 30
Is also referred to as the lower lead 5 because it becomes the lower stage in the state of the two-stage lead frame 20.

The leads 3 projecting from the inner frames 33, 43
Each of them extends parallel to the outer frames 32 and 42 up to predetermined positions, but thereafter bends, and in the case of the lower lead frame 30, extends so that the leading end approaches the periphery of the tab 6.

In the case of the upper lead frame 40, a part extends above the tab 6. The rest extends above a position close to the periphery of the tab 6. Many extend above the tub 6 and extend above the semiconductor chip 7 fixed on the tub 6.

The lead 3 whose distal end is located above the tab 6 has an intermediate portion bent one step higher to provide a spring property. The tips of the leads 3 extending on the tabs 6 are connected to semiconductor chips 7 fixed on the tabs 6.
From the electrode position.

In the wire bonding to the leads in the upper lead frame 40, at the time of the wire bonding, each lead is elastically pushed down by a holding piece. The wire bonding is performed on the leads pressed against the surface of the semiconductor chip 7 or the leads supported on the protruding support pins provided on the stage of the wire bonding apparatus.

In the lead portions extending in parallel with each other, the leads 3 are connected by dams 36 and 46. The dams 36, 46 are arranged in parallel with the inner frames 33, 43, and the outer portions are outer frames 32, 42.
It is connected to. These dams 36 and 46 function as dams for preventing the melted resin from flowing out when the package 2 is formed by transfer molding.

The leads extending into the region sealed by the transfer mold are referred to as inner leads 4d and 5d, and the leads extending outside the leads are referred to as outer leads 4c and 5c.

The lower lead frame 30 and the upper lead frame 40 are bonded to each other by welding or an insulating connecting member to form the two-stage lead frame 20.

In the first embodiment, as shown in FIG. 9, the inner frames 33 and 43 and the inner leads 4d and 5d are adhesively connected by an insulating connecting body 8. The connecting body 8 is
For example, an insulating resin tape having a sticky surface.

The outer frames 32 and 42 have guide holes 3 of a plurality of types of patterns used for transporting and positioning the lower lead frame 30 and the upper lead frame 40.
7, 47 are provided.

Note that the lower lead frame 30 and the upper lead frame 40 are shown in FIG.
Although the number is greatly reduced, it is actually as large as one hundred and several hundred to several hundred.

Next, the manufacture of a semiconductor device using the lower lead frame 30 and the upper lead frame 40 will be described.

As shown in the flowchart of FIG. 5, the semiconductor device 1 prepares upper and lower lead frames (step 1).
01), die bonding to the lower lead frame (step 102), wire bonding to the lower lead frame (step 103), connection of the upper and lower lead frames (step 104), wire bonding to the upper lead frame (step 105), and molding (step 102). 10
6), dam cutting (step 107), solder plating (step 108), lead molding (lower lead frame)
(Step 109) and lead molding (upper lead frame) (Step 110).

That is, as shown in FIG. 6 (see FIG. 9), the semiconductor chip 7 is fixed on the tab 6 of the lower lead frame 30 by a conventional die bonding method (step 102).

Next, as shown in FIG. 6 (see FIG. 9),
By performing wire bonding, the lower lead frame 30
The tips of the inner leads 5d are connected to the respective electrodes (not shown) of the semiconductor chip 7 with the conductive wires 9 (step 103).

Next, as shown in FIGS. 8 and 9, the upper lead frame 40 is overlaid on the lower lead frame 30, and both lead frames are connected via the connector 8 (step 104).

The connecting body 8 is made of, for example, an insulating resin tape having an adhesive surface, and the inner frames 33 and 43 of the lower lead frame 30 and the upper lead frame 40.
The space between the inner leads 4d and 5d is adhesively connected.

Next, as shown in FIGS. 10 and 11, wire bonding is carried out, and the tip of the inner lead 4d of the upper lead frame 40 and the semiconductor chip 7 fixed on the tab 6 are not shown. Each electrode is connected by a conductive wire 9 (step 105).

At the time of this wire bonding, FIG.
As shown in FIG. 5A, the tip of the inner lead 4 d of the upper lead 4 of the upper lead frame 40 is in a state of floating by several tens to several hundreds μm from the surface of the semiconductor chip 7 fixed to the tab 6. Therefore, as shown in FIG. 12B, the holding piece 50 is lowered, and the tip of the floating inner lead 4d of the upper lead 4 is provided on the surface of the semiconductor chip 7 or the stage 51 of the wire bonding apparatus. The upper surface of the support pin 52 is elastically contacted, and wire bonding is performed in this state. Thus, the wire 9 is securely connected to the tip of the inner lead 4d of the upper lead 4.

FIG. 12C shows a state in which the pressing piece 50 is lifted and the pressing down of the inner lead 4 d of the upper lead 4 is released.

Next, as shown in FIG. 13, the assembled two-stage lead frame 20 is clamped to a mold 60 of a transfer molding apparatus to seal it. The molding die 60 includes a lower die 61 and an upper die 62, and has cavities 63 and 64 depressed in respective parting surfaces.

Further, since the lead rows in the two-stage lead frame 20 are constituted by the leads 3 of the lower lead frame 30 and the upper lead frame 40, they are arranged in a staggered arrangement as shown in FIG. The shape of the parting surfaces of the upper and lower dies 62 and 61 of the mold 60 is also such that the convex teeth 65 can clamp the leads 3 (upper lead 4 and lower lead 5) in a staggered arrangement and prevent leakage of resin. And the concave teeth 66 are alternately arranged.

In the lower mold 61 and the upper mold 62, the arrangement of the convex teeth 65 and the concave teeth 66 is shifted by a half pitch, and the upper lead 4 or the lower lead 5 is displaced by the distal end surface 65 a of the convex teeth 65 and the concave form of the concave teeth 66. It is designed to be sandwiched between the recess inner surfaces 66a.

Since the upper lead 4 and the lower lead 5 have a predetermined dimension, a slope 67 is formed between the convex teeth 65 and the concave teeth 66.

At the time of resin molding, the two-stage lead frame 20 is clamped between the upper and lower dies 62, 61, and then the mold space (cavities 63, 64) formed by the clamping is formed.
The space is formed by press-fitting an insulative resin melted from a gate (not shown) and performing transfer molding, and the tab 6, the semiconductor chip 7, the wire 9, the connecting body 8, and the inner leads of the upper and lower leads 4 and 5 are formed. Lead 4d, 5d
Is formed (step 106).

Next, the two-stage lead frame 20 is removed from the mold 60, and the dams 36 and 46 of the two-stage lead frame 20 are cut and removed by a cutting die (not shown) (step 107).

Next, solder plating is applied to the lead portions of the two-stage lead frame 20 projecting from the package 2 by an electric field plating device (not shown) (step 108).

Next, lead molding is performed using a lead molding die (not shown). For example, in the lead forming, after forming the lower lead 5 (lead 3) of the lower lead frame 30 (step 109), the upper lead 4 (lead 3) of the upper lead frame 40 is formed (step 110).

The lead may be formed at a time by a mold corresponding to the staggered leads 3 of the two-stage lead frame 20.

In the lead forming, the forming shape can be selected, but in the present invention, the mounting ends 4b, 5b of the upper lead 4 and the lower lead 5 at the time of mounting are arranged in a staggered arrangement.

Further, the protrusion length g of the lower lead 5 is reduced, and the protrusion length h of the upper lead 4 is increased. Due to the different protruding lengths, the position arrangement of the protruding ends also becomes a staggered arrangement. Therefore, even if both the upper lead 4 and the lower lead 5 are formed into the same shape, the mounting ends 4b,
The arrangement of 5b is a staggered arrangement.

In the first embodiment, the upper lead 4 is formed as a gull wing in order to widen the arrangement interval of the staggered arrangement.
The lower lead 5 is a J lead. As a result, FIG.
And the semiconductor device 1 as shown in FIG. 2 is manufactured.

According to the semiconductor device of the first embodiment and the electronic device incorporating the semiconductor device, the following effects can be obtained. (1) The upper leads 4 and the lower leads 5 are alternately protruded from the two heights of each side surface of the package 2, and
The projecting length of the upper lead 4 and the lower lead 5 is set to be longer and shorter respectively, and the positions of the mounting ends 4b, 5b of the molded leads 4a, 5a are arranged in a staggered manner so that the two leads do not interfere with each other. Therefore, the lead pitch of the lead group can be narrower than the lead pitch processing limit value in the processing of the lead frame, and the lead pitch of the semiconductor device 1 can be narrowed.

(2) According to the above (1), in the semiconductor device 1, the number of pins in a package of the same size or the size of the package with the same number of pins can be reduced.

(3) Since the lead pitch of the semiconductor device 1 can be reduced by the above (2), in the electronic device 10 incorporating the semiconductor device 1, when the package size of the semiconductor device 1 is reduced, In addition, the mounting area of the semiconductor device 1 can be reduced, and the size of the electronic device 10 can be reduced.

(4) Since the lead pitch of the semiconductor device 1 can be narrowed by the above (2), the electronic device 10 incorporating the semiconductor device 1 incorporates the semiconductor device 1 having a large number of leads (pins). Electronic device 1
It is possible to improve the functionality of the device.

(5) Since the mounting ends 4b and 5b of the leads 3 (the upper lead 4 and the lower lead 5) of the semiconductor device 1 are arranged in a staggered manner, the bonding material such as solder in the mounted state is not used. Failure due to contact does not occur, and the reliability of the electronic device 10 increases.

(Embodiment 2) FIG. 15 is a schematic sectional view showing a part of a mold 60 used for manufacturing a semiconductor device according to another embodiment (Embodiment 2) of the present invention.

In the second embodiment, in the convex teeth 65 and the concave teeth 66 of the lower mold 61 and the upper mold 62 of the mold 60, both inner surfaces of the concave inner surface 66a of the concave tooth 66 are
The side surface of the lower lead 5 substantially coincides with the extension of the side surface of the upper lead 4 because the vertical surface is a vertical surface with respect to the bottom surface of the recess inner surface 66a, and this vertical surface forms the side surface of the convex tooth 65 as it is. And staggered lead 3
The lead pitch of the (upper lead 4 and lower lead 5) can be made smaller than in the first embodiment.

As a result, it is possible to further reduce the lead pitch of the semiconductor device.

(Embodiment 3) FIG. 16 is an enlarged sectional view showing a part of a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

The semiconductor device 1 according to the third embodiment has a structure in which the upper lead 4 and the lower lead 5 are not connected inside the package 2.

Although not shown, the semiconductor device 1 of the third embodiment integrates the lower lead frame 30 and the upper lead frame 40 used in the first embodiment by spot welding at the lead frame frames 31 and 41. The two-stage lead frame 20 is used and manufactured using the two-stage lead frame 20.

In the third embodiment, since the connecting body 8 is not used, the number of parts can be reduced, the labor for bonding by the connecting body 8 can be omitted, and the two-step lead frame 20 can be formed by simple spot welding. Reduction of the manufacturing cost of the device 1 can be achieved.

In manufacturing the two-stage lead frame 20, the lower lead frame 30 and the upper lead frame 4
Since no connecting body is interposed between the two lead frames, the thickness of the two-stage lead frame 20 can be reduced by the amount not using the connecting body. As a result, the package 2 can be made thinner, and the semiconductor device 1 can be made thinner. Can be achieved.

As a result, the mounting height of the semiconductor device 1 is reduced, and the electronic device 10 can be made thinner.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, for example,
In the above embodiment, the upper lead 4 and the lower lead 5 are a combination of a gull wing and a J lead, but may be another combination.

For example, FIG. 17 is a diagram showing an example of a combination of the outer lead of the upper lead 4 and the lower lead 5 of the semiconductor device.

The six combinations A to F are shown. The upper stage is the shape of the outer lead on the outer side of the staggered arrangement, and is the shape of the upper stage lead 4 having a long protruding length.

The lower stage is the shape of the outer lead inside the staggered arrangement, and is the shape of the lower stage lead 5 having a short protruding length.

A type is a combination of butt leads, B type
For the type, the upper lead 4 is a butt lead and the lower lead 5
Is a combination with the upper lead 4 as the gull wing and the lower lead 5 as the butt lead. The D type is a combination with the upper lead 4 as the gull wing and the lower lead 5 as the J lead. The E type is an upper lead. The combination 4 is a Z lead (this name is given from the shape) and the lower lead 5 is a butt lead. The F type is a combination where the upper lead 4 is a Z lead and the lower lead 5 is a J lead.

The present invention relates to each side (four sides) of a rectangular package.
So-called QFP (Quad Flat Packag)
e) is also applicable. The present invention can be applied at least to the technology for manufacturing semiconductor devices and electronic devices.

[0100]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) The upper lead and the lower lead are alternately projected from the two heights of each side surface of the package, the projecting lengths of the upper lead and the lower lead are lengthened and shortened, respectively, and the mounting end of the molded lead portion is formed. Since the positions are arranged in a staggered manner and manufactured so that both leads do not interfere,
The lead pitch of the lead group can be narrower than the lead pitch processing limit value in the processing of the lead frame, and the lead pitch of the semiconductor device can be narrowed, or the semiconductor device can be downsized by downsizing the package. (2) By downsizing the semiconductor device, the size of the electronic device incorporating the semiconductor device can be reduced. (3) Since the lead pitch of the semiconductor device can be reduced, an electronic device incorporating this semiconductor device can incorporate a semiconductor device having a large number of leads (pins).
It is possible to enhance the functions of the electronic device. (4) Since the mounting ends of the leads of the semiconductor device are arranged in a zigzag pattern, no failure occurs due to the contact between the bonding materials in the mounted state, and the reliability of the electronic device is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a part of an electronic device according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a cross-sectional view illustrating the semiconductor device of the first embodiment.

FIG. 3 is an enlarged sectional view showing a part of the semiconductor device according to the first embodiment.

FIG. 4 is a schematic diagram showing a footprint on a mounting board of the electronic device of the first embodiment.

FIG. 5 is a flowchart illustrating a part of the method for manufacturing a semiconductor device according to the first embodiment;

FIG. 6 is a plan view showing a lower lead frame used for manufacturing the semiconductor device of the first embodiment.

FIG. 7 is a plan view showing an upper lead frame used for manufacturing the semiconductor device of the first embodiment.

FIG. 8 is a plan view of a two-stage lead frame in which the lower lead frame and the upper lead frame are integrated.

FIG. 9 is a sectional view of the two-stage lead frame.

FIG. 10 is a plan view showing a state in which wire bonding has been performed on the two-stage lead frame.

FIG. 11 is a sectional view showing a state in which wire bonding has been performed on the two-stage lead frame.

FIG. 12 is a cross-sectional view showing a state where the leads of the upper lead frame and the electrodes of the semiconductor chip in the two-stage lead frame are wire-bonded.

FIG. 13 is a cross-sectional view showing a transfer mold state in manufacturing the semiconductor device of the first embodiment.

FIG. 14 is a schematic sectional view showing a part of a mold used for manufacturing the semiconductor device of the first embodiment.

FIG. 15 is a schematic sectional view showing a part of a mold used for manufacturing a semiconductor device according to another embodiment (Embodiment 2) of the present invention.

FIG. 16 is an enlarged sectional view showing a part of a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

FIG. 17 is a diagram showing an example of a combination of outer leads of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Package, 3 ... Lead, 4 ... Upper lead, 4a ... Molded lead part, 4b ... Mounting end part, 4c
... Outer lead, 4d ... Inner lead, 5 ... Lower lead, 5a ... Molded lead part, 5b ... Mounting end part, 5c ... Outer lead, 5d ... Inner lead, 6 ... Tab, 7 ...
Semiconductor chip, 8 linked body, 9 wire, 10 electronic device, 11 mounting board, 12 footprint, 13 solder, 20 double lead frame, 30 lower lead frame, 31 and 40 upper lead Frame, 41: Lead frame, 32, 42: Outer frame, 33, 43: Inner frame, 3
5 ... tab suspension lead, 36, 46 ... dam, 37, 47 ...
Guide hole, 44: Spatial area, 50: Retaining piece, 51: Stage, 52: Support pin, 60: Mold, 61: Lower mold, 62: Upper mold, 63, 64: Cavity, 65: Convex tooth, 65a ... tip surface, 66 ... concave tooth, 66a ... hollow inner surface,
67 ... Slope.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Michiaki Sugiyama 3-1-1, Higashi Koigakubo, Kokubunji-shi, Tokyo Within Hitachi Ultra LSE Engineering Co., Ltd. 3-chome 1-1 Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Toshihiko Usami 64 Nagano, Tenno-cho, Tenno-cho, Minamiakita-gun, Akita Akita Electronics Co., Ltd. (72) Inventor Masachika Masuda 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (13)

[Claims] 1. A package, a semiconductor chip located inside the package, a plurality of leads extending side by side inside and outside the package, and an inner end of the lead and an electrode of the semiconductor chip electrically connected to each other. A lead group protruding from each side surface of the package, wherein an upper lead and a lower stage protruding alternately along a lead arrangement direction from two heights of side surfaces of the package. A semiconductor device comprising a lead. 2. The semiconductor device according to claim 1, wherein one of the projecting lengths of the upper lead and the lower lead is longer and the other is shorter. 3. A staggered position of mounting ends of molded leads formed at protruding tips of the upper lead and the lower lead. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the shapes of the upper and lower leads are different from each other. 5. The molded lead portion of the upper lead and the lower lead has a shape of one or two of a butt lead, a gull wing, a J lead, and a Z lead. The semiconductor device according to claim 4. 6. The semiconductor device according to claim 1, wherein the upper lead and the lower lead are adhesively connected to each other in the package by an insulating connecting member. . 7. A lower lead frame having a tab on which a semiconductor chip is mounted and a leading end of an inner lead being close to a peripheral edge of the tab, and a leading end of at least a part of the inner lead when fixed to the lower lead frame in an overlapping manner. Preparing an upper lead frame, wherein the upper lead frame is located above the tab of the lower lead frame and the outer leads are displaced above the outer lead of the lower lead frame; and Fixing the semiconductor chip on the upper part, electrically connecting the electrodes of the semiconductor chip and the respective leads of the lower lead frame, and partially fixing the upper lead frame on the lower lead frame. A step of fabricating a two-stage lead frame; Electrically connecting the leads, forming the package by covering the tab, the semiconductor chip, the connection means, and the tip of the lead with an insulating resin, and cutting and removing an unnecessary portion of the two-stage lead frame. And forming the leads protruding from the package into a predetermined shape, wherein the two-stage lead frame has a plurality of leads protruding from each side surface of the package at a two-stage height of the side surface of the package. From the upper lead and the lower lead that alternately protrude along the direction of the lead arrangement from the lead. Wherein the mounting ends of the forming leads formed at the protruding tip portions are formed so as to have a staggered arrangement. Production method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the upper and lower leads are formed so that the shapes of the formed leads are different from each other. 9. The shape of the molded lead portion of the upper lead and the lower lead is a bat lead, a gull wing,
9. The method of manufacturing a semiconductor device according to claim 7, wherein the lead is formed so as to be a combination of one or two of a lead and a Z lead. 10. The semiconductor device according to claim 7, wherein the two-stage lead frame is bonded and connected via an insulating connector at a lead portion in a region where the package is formed. 2. The method for manufacturing a semiconductor device according to claim 1. 11. A package, a semiconductor chip located inside the package, a plurality of leads extending side by side inside and outside the package, and electrically connecting an inner end of the lead and an electrode of the semiconductor chip. An electronic device mounted with a semiconductor device having connection means for connecting to the semiconductor device, wherein a lead group projecting from each side surface of the package in the semiconductor device is arranged in a lead arrangement direction from a two-stage height of the side surface of the package. The upper lead and the lower lead are formed at the protruding tip portions of the upper and lower leads, one of which is longer and the other of which is shorter. An electronic device, wherein the positions of the mounting ends of the molding leads are arranged in a staggered manner. 12. The electronic device according to claim 11, wherein the shapes of the molded leads of the upper lead and the lower lead are different from each other. 13. The molded lead portion of the upper lead and the lower lead has a combination of one or two of a bat lead, a gull wing, a J lead, and a Z lead. Alternatively, the electronic device according to claim 12.