JPH0797654B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0797654B2 JPH0797654B2 JP62106050A JP10605087A JPH0797654B2 JP H0797654 B2 JPH0797654 B2 JP H0797654B2 JP 62106050 A JP62106050 A JP 62106050A JP 10605087 A JP10605087 A JP 10605087A JP H0797654 B2 JPH0797654 B2 JP H0797654B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- well region
- forming
- mask
- cadmium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Light Receiving Elements (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】 〔概要〕 カドミウム・テルル(CdTe)の基板に所定パターンの水
銀・カドミウム・テルル(Hg1-XCdXTe)よりなる島状の
ウェル領域を形成し、該ウェル領域内にP−N接合を形
成してホトダイオードを形成し、前記島状領域を基板の
CdTe結晶で絶縁分離した構造の赤外線検知素子アレイの
製造方法であって、前記島状のウェル領域を形成後、Cd
Teの選択エッチング液を用いて基板のCdTe結晶を選択エ
ッチングして島状のHg1-XCdXTe結晶のウェル領域を基板
より浮き上がらせ、基板のCdTe結晶とウェル領域の境界
位置に段差を形成し、さらにこの段差の位置を基準とし
てウェル領域への逆導電型の不純物導入のためのマクス
を前記基板上に形成し、該マスクを用いて前記不純物原
子導入を行うように構成して、ウェル領域への逆導電型
不純物原子を導入するに際してのマスク合わせ工程を確
実に行い得るようにする。DETAILED DESCRIPTION OF THE INVENTION [Outline] An island-shaped well region made of mercury-cadmium-tellurium (Hg 1-X Cd X Te) having a predetermined pattern is formed on a cadmium-tellurium (CdTe) substrate, and the well region is formed. A P-N junction is formed inside to form a photodiode, and the island region is formed on the substrate.
A method of manufacturing an infrared detection element array having a structure in which insulation is performed using a CdTe crystal, wherein after the island-shaped well region is formed, CdTe is formed.
The CdTe crystal on the substrate is selectively etched using a selective etching solution of Te to lift the well region of the island-shaped Hg 1-X Cd X Te crystal from the substrate and form a step at the boundary position between the CdTe crystal and the well region of the substrate. Then, a mask for introducing impurities of opposite conductivity type into the well region is formed on the substrate with reference to the position of the step, and the impurity atoms are introduced by using the mask. (EN) A mask aligning step can be reliably performed when introducing an impurity atom of opposite conductivity type into a well region.
本発明は赤外線検知素子の製造方法に係り、特にCdTe基
板にホトダイードをアレイ状に形成する半導体装置の製
造方法に関する。The present invention relates to a method for manufacturing an infrared detecting element, and more particularly to a method for manufacturing a semiconductor device in which photodiodes are formed in an array on a CdTe substrate.
水銀・カドミウム・テルルよりなる化合物半導体基板に
ホトダイオードをアレイ状に配設した赤外線検知素子ア
レイは益々高密度化、多素子化が要望されている。この
多素子化が進む際、隣接する素子の間に入射したホトン
により発生したキャリアが双方の素子に流れこみ、その
双方の素子に流れこんだキャリアが、双方の素子で検知
した検知信号に影響を及ぼすクロストーク現象が発生す
る。このクロストーク現象を減少させるために、素子間
の電気的に絶縁分離するチャネルストップに該当する機
能を有するものが望まれている。An infrared detector array having photodiodes arranged in an array on a compound semiconductor substrate made of mercury, cadmium, and tellurium is required to have higher density and more elements. As the number of devices increases, carriers generated by photons entering between adjacent devices flow into both devices, and the carriers that flow into both devices affect the detection signals detected by both devices. A crosstalk phenomenon that causes In order to reduce this crosstalk phenomenon, it is desired to have a function corresponding to a channel stop that electrically insulates and separates elements.
そのため、CdTeの基板に水銀・カドミウム・テルル(Hg
1-XCdXTe)よりなる結晶を島状に形成してウェル領域を
形成し、このウェル領域に該ウェル領域と逆導電型の不
純物原子を導入してP−N接合を形成してホトダイオー
ドを形成する。そしてこのホトダイオードをエネルギー
バンドギャップが大きい基板形成材料、即ちCdTeの結晶
で素子分離する構造が採られている。Therefore, mercury, cadmium, tellurium (Hg
1-X Cd X Te) is formed into an island shape to form a well region, and an impurity atom having a conductivity type opposite to that of the well region is introduced into the well region to form a P-N junction to form a photodiode. To form. Then, a structure is adopted in which the photodiode is isolated by a substrate forming material having a large energy band gap, that is, a CdTe crystal.
従来、このような赤外線検知素子アレイを形成する場
合、第7図に示すようにCdTe基板1に形成した溝2内に
液相エピタキシャル成長方法等を用いてP型のHg1-XCdX
Teよりなる結晶を島状にウェル領域3として形成する。Conventionally, when forming such an infrared detecting element array, as shown in FIG. 7, a P-type Hg 1-X Cd X is formed in the groove 2 formed in the CdTe substrate 1 by using a liquid phase epitaxial growth method or the like.
Crystals of Te are formed in an island shape as the well region 3.
次いで第8図に示すように該基板上に所定パターンのホ
トレジスト膜4を形成し、このホトレジスト膜4をマス
クとして用いてイオン注入法により該ウェル領域3にN
型の不純物となるボロン(B)原子をイオン注入してN
型層5を形成してP−N接合を成形してホトダイオード
6を形成している。Next, as shown in FIG. 8, a photoresist film 4 having a predetermined pattern is formed on the substrate, and the photoresist film 4 is used as a mask to ion-implant the well region 3 with N.
By implanting boron (B) atoms, which become impurities of the
A mold layer 5 is formed and a P-N junction is formed to form a photodiode 6.
ところでこのホトレジスト膜4を所定のパターンに形成
しようとする場合、ウェル領域3は基板1の表面と同一
平面に形成されているため、この基板上にホトレジスト
膜4を所定のパターンに露光するためのホトマスクの位
置合わせをするための基準が無く、そのためホトマスク
を基板の所定の位置に位置合わせするための位置合わせ
マークを基板に別個に形成する必要があり、作業が煩雑
となる問題がある。By the way, when the photoresist film 4 is formed in a predetermined pattern, since the well region 3 is formed in the same plane as the surface of the substrate 1, it is necessary to expose the photoresist film 4 in a predetermined pattern on the substrate. Since there is no reference for aligning the photomask, it is necessary to separately form an alignment mark for aligning the photomask at a predetermined position on the substrate, which causes a problem of complicated work.
本発明は上記した問題点を除去し、ホトレジスト膜に露
光用マスクを位置合わせする際、露光用マスクの基準位
置の位置合わせ箇所が基板上に形成できるような半導体
装置の製造方法の提供を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems and provide a method of manufacturing a semiconductor device in which an alignment position of a reference position of an exposure mask can be formed on a substrate when aligning an exposure mask with a photoresist film. And
上記目的を達成するための本発明の半導体装置の製造方
法は、CdTe基板に所定パターンのHg1-XCdXTe層を用いて
ウェル領域を形成後、前記基板をCdTeの選択エッチング
液を用いて予め選択的にエッチングして前記ウェル領域
を突出させ、基板とウェル領域の境界に段差を形成する
工程と、該段差の位置を基準としてウェル領域への逆導
電型の不純物原子導入のためのマスクを前記基板上に形
成し、該マスクを用いて前記不純物原子導入を行う工程
を含んで構成される。A method for manufacturing a semiconductor device of the present invention to achieve the above object is to form a well region using a predetermined pattern of Hg 1-X Cd X Te layer on a CdTe substrate, and then use the substrate with a selective etching solution of CdTe. And selectively projecting the well region in advance to form a step at the boundary between the substrate and the well region, and for introducing an impurity atom of opposite conductivity type into the well region with reference to the position of the step. The method includes the steps of forming a mask on the substrate and introducing the impurity atoms using the mask.
CdTe結晶のみ選択的にエッチングし、Hg1-XCdXTe結晶は
エッチングしないようなエッチング選択比を有するエッ
チング液、即ち特願昭57−191058号に於いて本出願人が
出願したエッチング液にてP−N接合を形成するHg1-XC
dXTeのウェル領域を有するCdTe基板をエッチングする
と、CdTe結晶のみが選択的にエッチングされるので、ウ
ェル領域が基板より突出した状態となる。そのため基板
表面に対してウェル領域の境界に段差が形成されてウェ
ル領域の位置が鮮明になり、その段差の部分を逆導電型
不純物原子導入のためのマスク形成に当たっての位置合
わせマークとして用いる。そして形成されたマスクは前
記ウェル領域への不純物原子導入を容易かつ確実なもの
にする。An etching solution having an etching selection ratio that selectively etches only CdTe crystals and does not etch Hg 1-X Cd X Te crystals, that is, the etching solution filed by the applicant in Japanese Patent Application No. 57-191058. Hg 1-X C forming a P-N junction
When a CdTe substrate having a well region of d X Te is etched, only the CdTe crystal is selectively etched, so that the well region projects from the substrate. Therefore, a step is formed at the boundary of the well region with respect to the surface of the substrate, the position of the well region becomes clear, and the step portion is used as an alignment mark for forming a mask for introducing impurity atoms of the opposite conductivity type. The formed mask facilitates and surely introduces impurity atoms into the well region.
以下、図面を用いながら本発明の一実施例につき詳細に
説明する。An embodiment of the present invention will be described in detail below with reference to the drawings.
先ず第1図に示すようにCdTeの基板11上に所定パターン
のホトレジスト12を形成し、該ホトレジスト膜12をマス
クとして用いてブロム(Br2)とメチルアルコール(CH3
OH)の混合液よりなるエッチング液を用いて所定のパタ
ーンの溝13を形成する。First, as shown in FIG. 1, a photoresist 12 having a predetermined pattern is formed on a CdTe substrate 11, and bromine (Br 2 ) and methyl alcohol (CH 3 ) are used by using the photoresist film 12 as a mask.
A groove 13 having a predetermined pattern is formed by using an etching solution composed of a mixed solution of (OH).
次いで第2図に示すように該基板11上にP型のHg1-XCdX
Teよりなる結晶層14を液晶エピタキシャル成長方法を用
いて形成する。Then, as shown in FIG. 2, P-type Hg 1-X Cd X is formed on the substrate 11.
A crystal layer 14 made of Te is formed using a liquid crystal epitaxial growth method.
更に第3図に示すようにHg1-XCdXTeの結晶層14を研磨し
て基板11の表面を平坦にし、CdTeの基板11に島状のHg
1-XCdXTeのウェル領域15を所定のパターンに形成する。Further, as shown in FIG. 3, the Hg 1-X Cd X Te crystal layer 14 is polished to make the surface of the substrate 11 flat, and the island-shaped Hg is formed on the CdTe substrate 11.
The well region 15 of 1-X Cd X Te is formed in a predetermined pattern.
次いで第4図に示すように、該基板11を弗化水素酸(H
F)と硝酸(HNO3)と酢酸(CH3COOH)と水(H2O)とが
重量比で(2〜5):(3〜5):6:6の混合比になるよ
うに混合したエッチング液、即ち本出願人が、特願昭57
−191058号に於いて出願したエッチング液を用いてエッ
チングする。するとこのエッチング液はCdTeを選択的に
エッチングし、Hg1-XCdXTeの結晶はエッチングしなので
第4図に示すようにHg1-XCdXTeのウェル領域15が島状に
突出して形成され、このウェル領域15と基板11との境界
位置で段差が形成される。Then, as shown in FIG. 4, the substrate 11 is treated with hydrofluoric acid (H
F), nitric acid (HNO 3 ), acetic acid (CH 3 COOH) and water (H 2 O) are mixed in a weight ratio of (2-5) :( 3-5): 6: 6. Etching solution, that is, the applicant of the present invention,
Etching is carried out using the etching solution applied for in No. -191058. Then, this etching solution selectively etches CdTe and etches the Hg 1-X Cd X Te crystal, so that the well regions 15 of Hg 1-X Cd X Te project in island shapes as shown in FIG. A step is formed at the boundary between the well region 15 and the substrate 11.
更に第5図に示すようにこの基板上にホトレジスト膜16
を形成した後、該ホトレジスト膜16を所定のパターンに
形成する。このホトレジスト膜16のパターン形成する
際、この段差の位置で露光用マスクの基準位置を位置合
わせすると正確にかつ容易にマスク合わせができる。Further, as shown in FIG. 5, a photoresist film 16 is formed on the substrate.
Then, the photoresist film 16 is formed into a predetermined pattern. When the pattern of the photoresist film 16 is formed, if the reference position of the exposure mask is aligned with the position of this step, the mask alignment can be performed accurately and easily.
次いで第6図に示すように該ホトレジスト膜16をマスク
としてB原子をイオン注入してN型層17を形成する。Next, as shown in FIG. 6, B atoms are ion-implanted using the photoresist film 16 as a mask to form an N-type layer 17.
このようにすれば、マスクの位置合わせマークが基板上
に形成されているので位置合わせ作業が容易となり、ま
た精度良く半導体素子形成用パターンが得られる。By doing so, the alignment mark of the mask is formed on the substrate, the alignment work becomes easy, and the semiconductor element forming pattern can be obtained with high accuracy.
以上述べたように本発明の半導体装置の製造方法によれ
ば、マスクの位置合わせ場所が容易に形成でき得る効果
がある。As described above, according to the method for manufacturing a semiconductor device of the present invention, there is an effect that a mask alignment position can be easily formed.
第1図より第6図迄は本発明の半導体装置の製造方法の
工程を示す断面図、 第7図より第8図迄は従来の半導体装置の製造方法の工
程を示す断面図である。 図に於いて、 11はCdTe基板、12はホトレジスト膜、13は溝、14はHg
1-XCdXTeの結晶、15はウェル領域、16はホトレジスト
膜、17はN型層を示す。1 to 6 are sectional views showing the steps of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 7 to 8 are sectional views showing the steps of the conventional method for manufacturing a semiconductor device. In the figure, 11 is a CdTe substrate, 12 is a photoresist film, 13 is a groove, and 14 is Hg.
Crystals of 1-X Cd X Te, 15 are well regions, 16 is a photoresist film, and 17 is an N-type layer.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/306 B ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/306 B
Claims (1)
水銀・カドミウム・テルルからなるウェル領域を形成
し、該ウェル領域に該ウェル領域に対して逆導電型の不
純物原子を導入して光電変換素子を形成する方法に於い
て、 前記ウェル領域を形成後、前記基板を選択性エッチング
剤により選択的にエッチングして前記ウェル領域を該基
板表面より突出させ、基板を形成するカドミウム・テル
ルの結晶とウェル領域を形成する水銀・カドミウム・テ
ルルの結晶の境界位置に段差を形成する工程と、該段差
の位置を基準としてウェル領域への逆導電型の不純物原
子導入のためのマスクを前記基板上に形成し、該マスク
を用いて前記不純物原子導入を行う工程を設けたことを
特徴とする半導体装置の製造方法。1. A photoelectric conversion element is formed by forming a well region made of mercury, cadmium, tellurium in a predetermined pattern on a cadmium-tellurium substrate and introducing impurity atoms of a reverse conductivity type into the well region. In the method of forming, after forming the well region, the substrate is selectively etched by a selective etching agent to project the well region from the surface of the substrate, and a cadmium tellurium crystal and a well forming the substrate are formed. Forming a step at the boundary position of the mercury-cadmium-tellurium crystal forming the region, and forming a mask for introducing impurity atoms of the opposite conductivity type into the well region on the substrate based on the position of the step Then, a method of manufacturing a semiconductor device is characterized in that a step of introducing the impurity atoms is provided using the mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62106050A JPH0797654B2 (en) | 1987-04-28 | 1987-04-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62106050A JPH0797654B2 (en) | 1987-04-28 | 1987-04-28 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63271979A JPS63271979A (en) | 1988-11-09 |
JPH0797654B2 true JPH0797654B2 (en) | 1995-10-18 |
Family
ID=14423799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62106050A Expired - Lifetime JPH0797654B2 (en) | 1987-04-28 | 1987-04-28 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0797654B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5863825A (en) * | 1997-09-29 | 1999-01-26 | Lsi Logic Corporation | Alignment mark contrast enhancement |
JP4598306B2 (en) * | 2001-05-28 | 2010-12-15 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US9881874B2 (en) | 2015-12-01 | 2018-01-30 | Toshiba Memory Corporation | Forming method of superposition checking mark, manufacturing method of a semiconductor device and semiconductor device |
-
1987
- 1987-04-28 JP JP62106050A patent/JPH0797654B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63271979A (en) | 1988-11-09 |
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