JPH0771197B2 - Frame sync signal generator - Google Patents

Description

The present invention relates to a frame synchronization signal generation circuit for image signals,
In particular, it relates to a frame synchronization signal generation circuit for controlling the generation cycle.

[Conventional technology]

Conventionally, the circuit shown in FIG. 4 has been used as a frame synchronization signal generation circuit for generating a frame synchronization signal using a line clock and a frame pulse of an input image signal.

In FIG. 4, the conventional frame synchronization signal generation circuit is
The line clock LCLK applied to each line of the image signal via the line clock input terminal 12 is counted up, and similarly reset by the frame pulse FP applied to each frame of the image signal via the frame pulse input terminal 13. Line counter 1 and line counter 1
Of the decoder 2 for receiving the output value (the number of lines) CNT-Q of the frame synchronizing signal FRM from the frame synchronizing signal output terminal 13 when the number of lines becomes 0.

FIG. 5 shows a time chart when the frame synchronization signal generation circuit of FIG. 4 is applied to an NTSC system television signal. In the NTSC system, since one frame of the image signal is composed of 525 lines, the line counter 1 is composed of a 10-bit counter. The line counter 1 is shown in FIG. 5 (a).
The line clock LCLK shown in is counted sequentially from 0.
The line counter 1 is reset by the frame pulse FP (FIG. 5 (b)) applied once to 525 lines, and the number of lines CNT-Q becomes 0 (FIG. 5 (c)). Number of lines C
When NT-Q becomes 0, the decoder 2 detects this and outputs a frame synchronization signal FRM (Fig. 5 (d)). Normally, as shown in FIG. 5 (c), the line counter 1 is 0 to 524.
Count up to.

[Problems to be Solved by the Invention]

In the conventional frame sync signal generating circuit described above,
Since the frame synchronization signal FRM was output only on condition that the line counter 1 was reset by the frame pulse FP,
Even when the frame pulse FP is not input in a normal cycle, there is a problem that a frame synchronization signal is generated according to the frame pulse FP. For example, it is assumed that there are frame pulses having different phases in the frame period T as shown in FIGS. 6A and 6B, and one of them is input to the frame synchronization signal generating circuit shown in FIG. Initially, the first frame pulse IFP1 (Fig. 6 (a)) is used as a frame pulse input, and at time T1, the second frame pulse IFP2 (Fig. 6 (b)) is switched to, as shown in Fig. 6 (c). As shown, the frame pulse FP resets the line counter 1 at a cycle different from the normal cycle T. As a result, the decoder 2 also outputs the line synchronization signal in a cycle different from the normal cycle (sixth).
Figure (d)). In this case, it is determined whether the cycle of the frame synchronization signal at the time of switching the input signal is longer or shorter than the normal cycle according to the phase difference of the input image signal. Frame sync signal FR
M is a signal that is a reference in an image signal processing device (not shown), and in a normal device, processing of the device is started by inputting a frame synchronization signal FRM, and processing of the device is performed by the next frame synchronization signal FRM. Works to finish. Therefore, if the frame sync signal is given at a cycle longer than usual, the processing start interval only needs to be extended, but the frame sync signal FR is made shorter than the normal cycle.
When M is input, while processing the device,
In addition, the processing of the next device will be executed from the beginning. When the output signal of the image processing apparatus is received by another apparatus, there is a problem that the break of the processing is not recognized and the normal operation cannot be performed.

[Means for Solving the Problems]

An object of the present invention is to provide a frame sync signal generation circuit in which a frame sync signal is not generated in a cycle shorter than a predetermined cycle.

Therefore, the frame synchronization signal generation circuit of the present invention achieves the above-mentioned object by not resetting the line counter even if a frame pulse is given, when the value of the line counter does not reach a predetermined value. .

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the frame synchronization signal generating circuit of the present invention has a configuration in which a comparison circuit 3 and an AND gate 4 as a reset pulse generating circuit are added to the conventional example of FIG.

Next, the operation of the frame synchronization signal generating circuit of FIG. 1 will be described with reference to the time chart of FIG. Here, the image signal is an NTSC television signal, and the terminal of the comparison circuit 3
The number of comparisons entered in 14 is 523. Line counter 1
Counts the line clock LCLK (FIG. 2 (a)) supplied for each line of the image signal and outputs the value (the number of lines) CNT-Q. Number of lines CNT-Q is decoder 2
And to the comparison circuit 3. Decoder 2 is the number of lines
When CNT-Q becomes 0, the frame synchronization signal FRM (Fig. 2 (e)) is output. The comparison circuit 3 uses the number of lines CNT-Q.
Is compared with a predetermined comparison number (524 in this case) given through the comparison number input terminal 14, and if the number of lines CNT-Q is larger than the comparison number (525 or more), the logic "1" level is reversed. In the case (0 to 524), the reset inhibit signal INH of the logic "0" level is output (FIG. 2 (d)). On the other hand, the AND gate 4 receives the frame pulse FP (FIG. 2 (b)) supplied through the frame pulse input terminal 11 and the reset inhibit signal INH, and outputs its output signal to the line counter 1
It is applied to the reset terminal RST of. As a result, the comparison circuit 3 applies the reset inhibit signal INH of logic "0" to the AND gate 4 while the number of lines CNT-Q is 0 to 523, so that the AND gate 4 is turned off and the frame pulse FP Is input, the line counter 1 is not reset. on the other hand,
Reset prohibition signal IN when the number of lines CNT-Q becomes 524 or more
H changes to the logic "1" level and turns on the AND gate 4, so that the line counter 1 is reset at the next frame pulse FP. When the line counter 1 is reset, the number of lines CNT-Q becomes 0, and the decoder 2 detects this and generates a frame synchronization signal FRM, which is output via the frame synchronization signal output terminal 13.

Next, with reference to FIG. 3, the case where the frame pulse is input in a shorter cycle than usual will be described. Now the third
There is an image signal having frame pulses IFP1 and IFP2 with the same period T and different phases as shown in FIGS. (A) and (b), and the frame pulse and line clock generation circuit (not shown) is the first until time T2. Frame pulse IFP1
Assuming that an image signal having (Fig. 3 (a)) and an image signal having the second frame pulse IFP2 (Fig. 3 (b)) are selected from time T2, the frame pulse input terminal 11 is The frame pulse shown in FIG. 3 (c) is given.
Since the input frame pulse is switched at time T2, frame pulses are input at intervals shorter than the normal cycle T. However, since the line counter 1 has started counting up the line clock from time T0 at this time, the number of lines does not exceed the comparison number, and the reset inhibit signal IN
Since H is a logic "0" level and the AND gate 4 is turned off, the line counter 1 is not reset. The line counter 1 continues to count the line clock, and when the number of lines exceeds the comparison number, the comparison circuit 3 changes the reset prohibition signal INH to the logic "1" level. At the first frame pulse (time T3) input in this state, the line counter 1 is reset, the decoder 2 detects this and outputs the frame synchronization signal FRM, and at the same time, the reset inhibit signal INH is set to the logic "0" level. Become.

As described above, in the present invention, the line counter is not reset until the number of line clocks reaches a certain number, so that the frame synchronization signal can be generated at intervals shorter than the normal cycle. It is possible to realize a frame sync signal generation circuit that does not have a frame sync signal.

Further, in the embodiment, since the reset circuit INH is set to the logic "1" level when the number of lines is greater than the number of comparisons in the comparison circuit, the number of comparisons is set to 523. The number of comparisons can be set to 524 by setting the reset prohibition signal INH to the logic "1" level.

Further, it goes without saying that the gate circuit as the reset pulse generating circuit can also be selected according to the output logic level of the reset inhibit signal.

〔The invention's effect〕

As described above, according to the present invention, even if the image frame signal FP is input at an interval shorter than a predetermined period, the line counter 1 is reset at an interval shorter than the period determined by the AND gate 4. The inhibition has the effect of outputting the frame synchronization signal FRM at a predetermined cycle or a cycle longer than that.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
FIG. 4 is a time chart for explaining the operation of FIG. 1, FIG. 4 is a block diagram of a conventional example, and FIGS. 5 and 6 are time charts for explaining the operation of FIG. 1 ... Line counter, 2 ... Decoder, 3 ... Comparison circuit, 4 ... AND gate, 11 ... Frame pulse input terminal, 12 ... Line clock input terminal, 13 ... Frame synchronization signal output terminal, 14 ... … Comparison input terminal.

Claims (1)

[Claims] 1. A frame synchronization signal generation circuit for generating a frame synchronization signal from a line clock generated for each line of an image signal and a frame pulse generated for each frame of the image signal. A line counter that counts up and outputs the value as the number of lines and is reset by the frame pulse; a decoder that detects that the number of lines has become 0 and generates the frame synchronization signal; The number of lines per frame that is uniquely determined by the signal system is compared with the value of the counter, and when the value of the counter is smaller than the number of lines per frame, a prohibition signal that prohibits resetting of the counter is output. A frame synchronization signal that includes a comparator circuit and secures an interval of at least the number of lines A frame synchronization signal generation circuit characterized by generating a signal.